interface device with parallel Rev. November 2001 Product data
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PDIUSBD12
interface device with parallel
Rev. November 2001 Product data
Description
PDIUSBD12 cost feature optimized device. normally used microcontroller based systems communicates with system microcontroller over high-speed general purpose parallel interface. also supports local transfer. This modular approach implementing interface allows designer choose optimum system microcontroller from available wide variety. This flexibility cuts down development time, risks, costs allowing existing architecture minimize firmware investments. This results fastest develop most cost effective peripheral solution. PDIUSBD12 fully conforms specification Rev. 1.1. also designed compliant with most device class specifications: Imaging Class, Mass Storage Devices, Communication Devices, Printing Devices, Human Interface Devices. such, PDIUSBD12 ideally suited many peripherals like Printer, Scanner, External Mass Storage (Zip Drive), Digital Still Camera, etc. offers immediate cost reduction applications that currently SCSI implementations. PDIUSBD12 suspend power consumption along with LazyClock output allows easy implementation equipment that compliant ACPITM, OnNOWTM, power management requirements. operating power allows implementation powered peripherals. addition, also incorporates features like SoftConnectTM, GoodLinkTM, programmable clock output, frequency crystal oscillator, integration termination resistors. these features contribute significant cost savings system implementation same time ease implementation advanced functionality into peripherals.
Features
Complies with Universal Serial specification Rev. High performance interface device with integrated SIE, FIFO memory, transceiver voltage regulator Compliant with most Device Class specifications High-speed Mbytes/s) parallel interface external microcontroller microprocessor Fully autonomous operation Integrated bytes multi-configuration FIFO memory Double buffering scheme main endpoint increases throughput eases real-time data transfer
Philips Semiconductors
PDIUSBD12
interface device with parallel
Data transfer rates: Mbytes/s achievable Bulk mode, Mbits/s achievable Isochronous mode Bus-powered capability with very good performance Controllable LazyClock output during suspend Software controllable connection (SoftConnectTM) Good connection indicator that blinks with traffic (GoodLinkTM) Programmable clock frequency output Complies with ACPI, OnNOW power management requirements Internal Power-on reset low-voltage reset circuit Available SO28 TSSOP28 packages Full industrial grade operation from Higher than in-circuit protection lowers cost extra components Full-scan design with high fault coverage (>99%) ensures high quality Operation with dual voltages: ±0.3 extended supply range Multiple interrupt modes facilitate both bulk isochronous transfers.
Pinning information
Pinning
configuration.
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PDIUSBD12
interface device with parallel
description
Table Symbol DATA DATA DATA DATA DATA DATA DATA DATA description Type[1] Description bidirectional data. Slew-rate controlled. bidirectional data. Slew-rate controlled. bidirectional data. Slew-rate controlled. bidirectional data. Slew-rate controlled. Ground. bidirectional data. Slew-rate controlled. bidirectional data. Slew-rate controlled. bidirectional data. Slew-rate controlled. bidirectional data. Slew-rate controlled. Address Latch Enable. falling edge used close latch address information multiplexed address/ data bus. Permanently tied separate address/ data configuration. Chip Select (Active LOW). Device Suspend state. Programmable Output Clock (slew-rate controlled). Interrupt (Active LOW). Read Strobe (Active LOW). Write Strobe (Active LOW). Request. Acknowledge (Active LOW). Transfer (Active LOW). Double VBUS sensing. EOT_N only valid when asserted together with DMACK_N either RD_N WR_N. Reset (Active asynchronous). Built-in Power-on reset circuit present chip, tied HIGH VCC. GoodLink indicator (Active LOW) Crystal Connection MHz). Crystal Connection MHz). external clock signal, instead crystal, connected XTAL1, then XTAL2 should floated. Voltage supply (4.0 operate supply both VOUT3.3 pins. data line. data line.
CS_N CLKOUT INT_N RD_N WR_N DMREQ EOT_N
I,OD4
SUSPEND
DMACK_N
RESET_N GL_N XTAL1 XTAL2
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PDIUSBD12
interface device with parallel
description.continued Type[1] Description regulated output. operate supply both VOUT3.3 pins. Address bit. selects command instruction; selects data phase. This don't care multiplexed address data configuration should tied HIGH.
Table Symbol VOUT3.3
Output with drive OD4: Output Open Drain with drive OD8: Output Open Drain with drive IO2: Input Output with drive Output with drive.
Ordering information
Table Packages 28-pin plastic 28-pin plastic TSSOP Ordering information Temperature range Outside North America PDIUSBD12 PDIUSBD12 North America PDIUSBD12 PDIUSBD12PW Pkg. Dwg. SOT136-1 SOT361-1
Block diagram
This conceptual block diagram does include each individual signal.
Block diagram.
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PDIUSBD12
interface device with parallel
Functional description
Analog transceiver
integrated transceiver interfaces directly cables through termination resistors.
Voltage regulator
regulator integrated on-chip supply analog transceiver. This voltage also provided output connect external pull-up resistor. Alternatively, PDIUSBD12 provides SoftConnect technology with integrated pull-up resistor.
clock multiplier (Phase-Locked Loop) integrated on-chip. This allows low-cost crystal. also minimized lower frequency crystal. external components needed operation PLL.
clock recovery
clock recovery circuit recovers clock from incoming data stream using oversampling principle. able track jitter frequency drift specified specification.
Philips Serial Interface Engine (PSIE)
Philips implements full protocol layer. completely hardwired speed needs firmware intervention. functions this block include: synchronization pattern recognition, parallel/serial conversion, stuffing/de-stuffing, checking/generation, verification/generation, address recognition, handshake evaluation/generation.
SoftConnect
connection accomplished bringing (for high-speed device) HIGH through pull-up resistor. PDIUSBD12, pull-up resistor integrated on-chip connected default. connection established through command sent external/system microcontroller. This allows system microcontroller complete initialization sequence before deciding establish connection USB. Re-initialization connection also performed without requiring pull cable. PDIUSBD12 will check VBUS availability before connection established. VBUS sensing provided through EOT_N. Section "Pin description" details. Sharing VBUS sensing EOT_N easily accomplished using VBUS voltage pull-up voltage normally open-drain output controller pin.
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PDIUSBD12
interface device with parallel
should noted that tolerance internal resistors higher (25%) than that specified specification (5%). However, overall voltage specification connection still with good margin. decision make sure this feature lies with users.
GoodLink
Good connection indication provided through GoodLink technology. During enumeration, indicator will blink momentarily corresponding enumeration traffic. When PDIUSBD12 successfully enumerated configured, indicator will permanently Subsequent successful (with acknowledgement) transfer from PDIUSBD12 will blink LED. During suspend, will OFF. This feature provides user-friendly indicator status device, connected traffic. useful field diagnostics tool isolate faulty equipment. This feature helps lower field support hotline costs.
Memory Management Unit (MMU) Integrated
integrated buffer difference speed between USB, running bursts Mbits/s parallel interface microcontroller. This allows microcontroller read write packets speed.
Parallel Interface
generic parallel interface defined ease-of-use, speed, allows direct interfacing major microcontrollers. microcontroller, PDIUSBD12 appears memory device with 8-bit data address (occupying locations). PDIUSBD12 supports both multiplexed non-multiplexed address data bus. PDIUSBD12 also supports (Direct Memory Access) transfer which allows main endpoint (endpoint directly transfer from local shared memory. Both single-cycle burst mode transfers supported.
6.10 Example parallel interface 80C51 microcontroller
example shown Figure permanently tied signify separate address data configuration. PDIUSBD12 connects 80C51 ports. This port controls command data phase PDIUSBD12. multiplexed address data 80C51 connected directly data PDIUSBD12. address phase will ignored PDIUSBD12. clock input signal 80C51 (pin XTAL1) provided output CLKOUT PDIUSBD12.
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Product data
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PDIUSBD12
interface device with parallel
PDIUSBD12
INT_N DATA [7:0] WR_N RD_N CLKOUT CS_N
80C51
INTO/P3.2 PORT (e.g. P3.3) [0.7:0.0] [7:0] WR/P3.6 RD/P3.7 XTAL1
SV00870
Example parallel interface 80C51 microcontroller.
transfer
Direct Memory Address (DMA) allows efficient transfer block data between host local shared memory. Using controller, data transfer between PDIUSBD12's main endpoint (endpoint local shared memory happen autonomously without local intervention. Preceding transfer, local receives from host necessary setup information programs controller accordingly. Typically, controller demand transfer mode byte count register address counter programmed with right values. this mode, transfers occur only when PDIUSBD12 requests them terminated when byte count register reaches zero. After controller been programmed, enable PDIUSBD12 local initiate transfer. PDIUSBD12 programmed single-cycle burst mode DMA. single-cycle DMA, DMREQ deactivated every single acknowledgement DMACK_N before being re-asserted. burst mode DMA, DMREQ kept active number bursts programmed device before going inactive. This process continues until PDIUSBD12 receives termination notice through EOT_N. This will generate interrupt notify local that operation completed. read operation, DMREQ will only activated whenever buffer full, signalling that host successfully transferred packet PDIUSBD12. With double buffering scheme, host start filling second buffer while first buffer being read out. This parallel processing increases effective throughput. When host does fill buffer completely (less than bytes bytes single direction configuration), DMREQ will deactivated last byte buffer regardless current burst count. will re-asserted next packet with refreshed burst count. Similarly, write operations, DMREQ remains active whenever buffer full. When buffer filled packet sent over host next token DMREQ will reactivated transfer successful. Also, double buffering scheme here will improve throughput. non-isochronous transfer (bulk interrupt), buffer needs completely filled write
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PDIUSBD12
interface device with parallel
operation before data sent host. only exception transfer, when reception EOT_N will stop write operation buffer content will sent host next token. isochronous transfers, local controller have guarantee that they able sink source maximum packet size frame ms). assertion DMACK_N automatically selects main endpoint (endpoint regardless current selected endpoint. operation PDIUSBD12 interleaved with normal access other endpoints. operation terminated resetting enable register assertion EOT_N together with DMACK_N either RD_N WR_N. PDIUSBD12 supports transfer single address mode also work dual address mode controller. single address mode, transfer done DREQ, DMACK_N, EOT_N, WR_N RD_N control lines. dual address mode, pins DMREQ, DMACK_N EOT_N used; instead CS_N, WR_N RD_N control signals used. mode Transfer Protocol PDIUSBD12 needs followed. source DMAC accessed during read cycle destination during write cycle. Transfer needs done separate cycles, storing data temporarily DMAC.
Endpoint description
PDIUSBD12 endpoints sufficiently generic used various device classes ranging from Imaging, Printer, Mass Storage Communication device classes. PDIUSBD12 endpoints configured operating modes depending mode command. modes are: Mode Mode Mode Mode Non-isochronous transfer (Non-ISO mode) Isochronous output only transfer (ISO-OUT mode) Isochronous input only transfer (ISO-IN mode) Isochronous input output transfer (ISO-I/O mode).
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PDIUSBD12
interface device with parallel
Endpoint Configuration Endpoint index Transfer type Direction[1] Max. Packet size (bytes) 64[4]
Table Endpoint number
Mode (Non-ISO mode) Control Generic[2] Generic[2][3] Control Generic[2] Isochronous[3] Control Generic[2] Isochronous[3] Control Generic[2] Isochronous[3]
Mode (ISO-OUT mode)
Mode (ISO-IN mode)
Mode (ISO-I/O mode)
input host; OUT: output from host. Generic endpoints used either Bulk Interrupt endpoint. main endpoint (endpoint number double-buffered ease synchronization with real-time applications increase throughput. This endpoint supports access. Denotes double buffering. size shown single buffer.
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PDIUSBD12
interface device with parallel
Main endpoint
main endpoint (endpoint number primary endpoint sinking sourcing relatively large amounts data. implements following features ease this task:
Double buffering. This allows parallel operation between access local
access thus increasing throughput. Buffer switching handled automatically. This results transparent buffer operation.
(Direct Memory Access) operation. This interleaved with normal
operation other endpoints.
Automatic pointer handling during operation. local intervention
necessary when `crossing' buffer boundary.
Configurable endpoint either isochronous transfer non-isochronous (bulk
interrupt) transfer.
Command summary
Table Name Initialization commands Address/Enable Endpoint Enable mode Data flow commands Read Interrupt Register Select Endpoint Device Control Control Endpoint Endpoint Endpoint Endpoint Read Last Transaction Status Control Control Endpoint Endpoint Endpoint Endpoint Read Buffer Write Buffer Selected Endpoint Selected Endpoint Read bytes Read byte (optional) Read byte (optional) Read byte (optional) Read byte (optional) Read byte (optional) Read byte (optional) Read byte Read byte Read byte Read byte Read byte Read byte Read bytes Write bytes Device Device Device Device Write byte Write byte Write bytes Write/Read byte Command summary Destination Code (Hex) Transaction
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PDIUSBD12
interface device with parallel
Command summary.continued Destination Control Control Endpoint Endpoint Endpoint Endpoint Code (Hex) Transaction Write byte Write byte Write byte Write byte Write byte Write byte None None None None Read bytes
Table Name
Endpoint Status
Acknowledge Setup Clear Buffer Validate Buffer General commands Send Resume Read Current Frame Number
Selected Endpoint Selected Endpoint Selected Endpoint
Command description
11.1 Command procedure
There three basic types commands: Initialization, Data Flow General commands. Respectively, these used initialize function; data flow between function host; some general commands.
11.2 Initialization commands
Initialization commands used during enumeration process network. These commands used enable function endpoints. They also used assigned address. 11.2.1 Address/Enable Code (Hex) Transaction write byte This command used assigned address enable function.
POWER VALUE ADDRESS ENABLE
SV00825
ADDRESS: value written becomes address. ENABLE: enables this function.
Address/Enable command: allocation.
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interface device with parallel
11.2.2
endpoint enable Code (Hex) Transaction write byte generic/Isochronous endpoints only enabled when function enabled Address/Enable command.
GENERIC/ISOCHRONOUS ENDPOINT: value indicates generic/isochronous endpoints enabled.
endpoint enable command: allocation.
11.2.3
mode Code (Hex) Transaction write bytes mode command followed data writes. first byte contains configuration bits. second byte clock division factor byte.
Table allocation.
mode command, Configuration byte.
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PDIUSBD12
interface device with parallel
mode command, Configuration byte: allocation Symbol Description ENDPOINT These bits endpoint configurations follows: CONFIGURAT mode (Non-ISO mode) mode (ISO-OUT mode) mode (ISO-IN mode) mode (ISO-I/O mode) Section "Endpoint description" more details.
Table
SoftConnect
indicates that upstream pull-up resistor will connected VBUS available. means that upstream resistor will connected. programmed value will changed reset. indicates that errors "NAKing" reported will generate interrupt. indicates that only reported. programmed value will changed reset. indicates that internal clocks always running even during Suspend state. indicates that internal clock, crystal oscillator stopped whenever needed. meet strict Suspend current requirement, this needs `0'. programmed value will changed reset. indicates that CLKOUT will switch LazyClock. indicates that CLKOUT switches LazyClock after Suspend goes HIGH. LazyClock frequency 40%. programmed value will changed reset.
INTERRUPT MODE CLOCK RUNNING
LAZYCLOCK
POWER VALUE CLOCK DIVISION FACTOR RESERVED SET_TO_ONE SOF-ONLY INTERRUPT MODE
SV00862
Table allocation.
mode command, Clock division factor byte.
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PDIUSBD12
interface device with parallel
Clock division factor byte: allocation Description
Table
Symbol
SOF-ONLY Setting this will cause interrupt line activated INTERRUPT MODE Start Frame clock (SOF) only, regardless setting Pin-Interrupt mode, DMA. SET_TO_ONE This needs prior read write operation. This should always after power. zero after Power-on reset. value indicates clock division factor CLKOUT. output frequency MHz/(N+1) where Clock Division Factor. reset value This will produce output frequency which then programmed down user. minimum value giving range frequency from MHz. minimum value giving maximum frequency MHz. maximum value giving minimum frequency MHz. PDIUSBD12 design ensures glitching during frequency change. programmed value will changed reset.
CLOCK DIVISION FACTOR
11.2.4
Code (Hex) Transaction read/write byte command followed data write/read to/from configuration register. Configuration register: During operation, two-byte buffer header (status byte length information) transferred to/from local CPU. This allows data continuous interleaved chunks these headers. read operations, header will skipped PDIUSBD12. Section 11.3.5 "Read buffer" command. write operations, header will automatically added PDIUSBD12. This provides clean simple data transfer.
Table allocation.
command.
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interface device with parallel
command: allocation Symbol ENDPOINT INDEX INTERRUPT ENABLE Description allows interrupt generated whenever endpoint buffer validated (see Section 11.3.8 "Validate buffer" command). Normally turned operation reduce unnecessary servicing. allows interrupt generated whenever endpoint buffer contains valid packet. Normally turned operation reduce unnecessary servicing. signifies normal interrupt mode where interrupt generated logical bits interrupt registers. signifies that interrupt will occur when Start Frame clock (SOF) seen upstream bus. other normal interrupts still active. When this `1', operation will automatically restart. This determines direction data flow during transfer. means external shared memory PDIUSBD12 (DMA Write); means PDIUSBD12 external shared memory (DMA Read). Writing this will start operation through assertion DMREQ. main endpoint buffer needs full (for Read) empty (for Write) before DMREQ will asserted. single cycle mode, DMREQ deactivated upon receiving DMACK_N. burst mode DMA, DMREQ deactivated after number burst exhausted. then asserted again next burst. This process continues until EOT_N asserted together with DMACK_N either RD_N WR_N, which will reset this terminate operation. operation also terminated writing this bit. Selects burst length operation: Single-cycle Burst (4-cycle) Burst (8-cycle) Burst (16-cycle)
Table
ENDPOINT INDEX INTERRUPT ENABLE
INTERRUPT MODE
AUTO RELOAD DIRECTION
ENABLE
BURST
11.3 Data flow commands
Data flow commands used manage data transmission between endpoints external microcontroller. Much data flow initiated interrupt microcontroller. microcontroller utilizes these commands access determine whether endpoint FIFOs have valid data. 11.3.1 Read interrupt register Code (Hex) Transaction read bytes
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interface device with parallel
This command indicates origin interrupt. endpoint interrupt bits (bits cleared reading endpoint last transaction status register through Read Last Transaction Status command. other bits cleared after reading interrupt registers.
Table allocation.
Interrupt Register, byte
EOT: This signifies that operation completed.
Interrupt Register, byte allocation. Table Read interrupt register, byte allocation Description
Symbol
SUSPEND CHANGE When PDIUSBD12 receive SOFs, will into suspend state Suspend Change will HIGH. change suspend awake state will this HIGH generate interrupt. RESET After reset interrupt will generated this will `1'. reset identical hardware reset through RESET_N with exception that reset generates interrupt notification device enabled default address
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interface device with parallel
11.3.2
Select Endpoint Code (Hex) Transaction read byte (optional) Select Endpoint command initializes internal pointer start selected buffer. Optionally, this command followed data read, which returns this byte.
FULL/EMPTY: indicates buffer full, indicates empty buffer. STALL: indicates selected endpoint stall state.
Select Endpoint command: allocation.
11.3.3
Read Endpoint status Code (Hex) Transaction read byte
RESERVED SETUP PACKET RESERVED BUFFER FULL BUFFER FULL ENDPOINT STALLED
004aaa056
Read Endpoint status: allocation.
11.3.4
Read last transaction status register Code (Hex) Transaction read byte Read Last Transaction Status command followed data read that returns status last transaction endpoint. This command also resets corresponding interrupt flag interrupt register, clears status, indicating that read.
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This command useful debugging purposes. Since keeps track every transaction, status information overwritten each transaction.
Table allocation.
Read last transaction status register. Table Read last transaction status register: allocation Symbol PREVIOUS STATUS READ DATA PACKET SETUP PACKET ERROR CODE DATA RECEIVE/TRANSMIT SUCCESS Error codes Description Error encoding Error; bits inversion bits unknown; encoding valid, does exist Unexpected packet; packet type expected token, data acknowledge), SETUP token non-control endpoint Token Error Data Error Time Error Never happens Unexpected End-Of-Packet Sent received Sent Stall, token received, endpoint stalled Description indicates second event occurred before previous status read. indicates last successful received sent packet DATA1 PID. indicates last successful received packet SETUP token (this will always read buffers). Table "Error codes". indicates data been received transmitted successfully.
Table
Error code (Binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010
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interface device with parallel
Error codes.continued Description Overflow Error, received packet longer than available buffer space Bitstuff Error Wrong DATA PID; received DATA expected
Table
Error code (Binary) 1011 1101 1111
11.3.5
Read buffer Code (Hex) Transaction read multiple bytes (max. 130) Read Buffer command followed number data reads, which returns contents selected endpoint data buffer. After each read, internal buffer pointer incremented buffer pointer reset buffer Read Buffer command. This means that reading writing buffer interrupted other command (except Select Endpoint). data buffer organized follows:
byte reserved; have value byte number/length data bytes byte data byte byte data byte etc.
first bytes will skipped read operation. Thus, first read will Data byte second read will Data byte etc. PDIUSBD12 determine last byte this packet through termination packet. 11.3.6 Write buffer Code (Hex) Transaction write multiple bytes (max. 130) Write Buffer command followed number data writes, which load endpoints buffer. data must organized same described Read Buffer command. first byte (reserved) should always `0'. During write operation, first bytes will bypassed. Thus, first write will write into Data byte second write will write into Data byte etc. non-isochronous transfer (bulk interrupt), buffer should completely filled before data sent host switch next buffer occurs. exception transfer indicated activation EOT_N, when current buffer content (completely full not) will sent host. Remark: There protection against writing reading over buffer's boundary against writing into buffer reading from buffer. these actions could cause incorrect operation. Data buffer only meaningful after
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successful transaction. exception during operation main endpoint (endpoint which case pointer automatically pointed second buffer after reaching boundary (double buffering scheme). 11.3.7 Clear buffer Code (Hex) Transaction none When packet received completely, internal endpoint buffer full flag set. subsequent packets will refused returning NAK. When microcontroller read data, should free buffer Clear Buffer command. When buffer cleared, packets will accepted. 11.3.8 Validate buffer Code (Hex) Transaction none When microprocessor written data into buffer, should buffer full flag Validate Buffer command. This indicates that data buffer valid sent host when next token received. 11.3.9 endpoint status Code (Hex) Transaction write byte stalled control endpoint automatically unstalled when receives SETUP token, regardless content packet. endpoint should stay stalled state, microcontroller re-stall When stalled endpoint unstalled (either Endpoint Status command receiving SETUP token), also re-initialized. This flushes buffer buffer waits DATA PID, buffer writes DATA PID. Even when unstalled, writing Endpoint Status initializes endpoint.
STALLED: indicates endpoint stalled.
endpoint status: allocation.
11.3.10
Acknowledge setup Code (Hex) Transaction none
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arrival SETUP packet flushes buffer disables Validate Buffer Clear Buffer commands both endpoints. microcontroller needs re-enable these commands Acknowledge Setup command. This ensures that last SETUP packet stays buffer packet sent back host until microcontroller acknowledged explicitly that seen SETUP packet. microcontroller must send Acknowledge Setup command both endpoints.
11.4 General commands
11.4.1 Send resume Code (Hex) Transaction none Sends upstream resume signal This command normally issued when device suspend. RESUME command followed data read write. 11.4.2 Read current frame number Code (Hex) Transaction read bytes This command followed data reads returns frame number last successfully received SOF. frame number returned Least Significant byte first.
Read current frame number.
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Interrupt modes
Table
Interrupt modes INTERRUPT MODE[2] Interrupt types Normal[3] Normal only
SOF-ONLY INTERRUPT MODE[1]
Clock division factor byte mode command (see Table command (see Table Normal interrupts from Interrupt Register.
Limiting values
Table Limiting values accordance with Absolute Maximum Rating System (IEC 60134). Symbol Ilatchup Vesd Tstg Ptot
Parameter supply voltage input voltage latchup current electrostatic discharge voltage storage temperature total power dissipation
Conditions
-0.5 -0.5
+6.0 ±2000 +150
Unit
[1][2]
Equivalent discharging capacitor resistor. Values given device only; in-circuit Vesd(max) ±8000
Table Symbol VCC1 VCC2
Recommended operating conditions Parameter supply voltage (Main mode) supply voltage (Alternate mode) input voltage input voltage input voltage analog output voltage operating ambient temperature free Section Section device. Conditions apply VCC1 only apply VCC2 both Vout3.3 pins Unit
VI/O VAI/O Tamb
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Static characteristics
Table Symbol VHYS characteristics (digital pins) Parameter level input voltage HIGH level input voltage hysteresis voltage level output voltage HIGH level output voltage (Schmitt Trigger) pins rated drive rated drive Leakage current Table Symbol ZDRV
Conditions
Unit
Input levels
Output levels
OFF-state current input leakage current suspend current operating current characteristics (AI/O pins) Parameter Hi-Z state data line leakage differential input sensitivity differential common mode range single-ended receiver threshold static output static output HIGH transceiver capacitance driver output resistance pull-up resistance
(Open Drain) pins oscillator stopped inputs GND/VCC
Conditions |(D+) (D-)| includes range
Unit
Leakage current Input levels
Output levels steady state drive SoftConnect
Capacitance Output resistance Pull-up resistance
Includes external resistors
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Dynamic characteristics
Table characteristics (AI/O pins; FULL speed)[1] VCC; unless otherwise specified. Symbol Parameter Driver characteristics tRFM VCRS tEOPT tDEOP tJR1 tJR2 tEOPR1 tEOPR2 rise time fall time rise/fall time matching (tR/tF) output signal crossover voltage source width differential data transition skew receiver data jitter tolerance next transition receiver data jitter tolerance paired transitions width receiver width receiver must reject EOP; Figure must accept EOP; Figure
Conditions
Unit
Driver timings Figure Figure
Receiver timings: -18.5 +18.5
Test circuit, Figure Characterized implemented production test. Guaranteed design.
tPERIOD CROSSOVER POINT EXTENDED CROSSOVER POINT DIFFERENTIAL DATA LINES
SOURCE WIDTH: tEOPT DIFFERENTIAL DATA SEO/EOP SKEW tPERIOD tDEOP RECEIVER WIDTH: tEOPR1, tEOPR2
SV00837
Differential data-to-EOP transition skew width.
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Table Symbol tAVLL tLLAX tCLWL tWHCH tAVWL tWHAX tWDSU tWDH t(WC tCLRL tRHCH tAVRL tRLDD tRHDZ t(WC
characteristics (parallel interface) Parameter HIGH pulse width address valid time Address transition time CS_N (DMACK_N) WR_N time WR_N HIGH CS_N (DMACK_N) HIGH time Valid WR_N time WR_N HIGH transition time WR_N pulse width write data setup time write data hold time write cycle time write command write data CS_N (DMACK_N) RD_N time RD_N HIGH CS_N (DMACK_N) HIGH time Valid RD_N time RD_N pulse width RD_N Data Driven time RD_N HIGH Data Hi-Z time read cycle time write command read data Conditions 130[2] 500[3] 130[2] 500[3] Unit
timings
Write timings
Read timings
negative. access only module 64th byte second last (EOT-1)byte. timings valid back-to-back data access only.
timing.
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tCLRL tCLWL CS_N DMACK_N tAVRL tAVWL COMMAND DATA
tRHCH tWHCH
tWHAX
WR_N
t(WC t(WC tWDSU tWDH
DATA[7:0]
VALID DATA
RD_N
tRHNDV tRLDD tRHDZ
DATA[7:0]
VALID DATA tRLDD
VALID DATA
004aaa058
Parallel interface timing (I/O DMA). Table characteristics (DMA) Conditions simultaneous DMACK_N, RD_N/WR_N EOT_N time Unit
Symbol Parameter Single-cycle timings tAHRH tSHAH tRHSH DMACK_N HIGH DMREQ HIGH time RD_N/WR_N HIGH DMACK_N HIGH time DMREQ HIGH RD_N/WR HIGH time EOT_N pulse width
Burst timings tSLRL tRHNDV tELRL RD_N/WR_N DMREQ time RD_N (only) HIGH next data valid EOT_N DMREQ time
timings
9397 08969
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
tRHSH DMREQ
tAHRH
DMACK_N tSHAH RD_N/WR_N EOT_N
SV00874
EOT_N considered valid when DMACK_N, RD_N/WR_N EOT_N LOW.
Single-cycle timing.
tRHSH DMREQ tSLRL DMACK_N tSHAH
RD_N/WR_N
SV00875
Burst timing.
terminated EOT.
9397 08969 Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Test information
dynamic characteristics analog ports listed Table were determined using circuit shown Figure
1.5k INTERNAL TEST POINT 50pF
SV00849
Load D+/D-.
9397 08969
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Package outline
SO28: plastic small outline package; leads; body width SOT136-1
index detail
scale
DIMENSIONS (inch dimensions derived from original dimensions) UNIT inches max. 2.65 0.10 0.30 0.10 2.45 2.25 0.25 0.01 0.49 0.36 0.32 0.23 18.1 17.7 0.71 0.69 0.30 0.29 1.27 10.65 10.00 0.043 0.039 0.25 0.01 0.25 0.01
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.050 0.055 0.394 0.016
0.035 0.004 0.016
Note Plastic metal protrusions 0.15 maximum side included. OUTLINE VERSION SOT136-1 REFERENCES 075E06 JEDEC MS-013 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
SO28 package outline.
9397 08969 Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
TSSOP28: plastic thin shrink small outline package; leads; body width
SOT361-1
index
detail
scale
DIMENSIONS original dimensions) UNIT max. 1.10 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.65 0.75 0.50 0.13
Notes Plastic metal protrusions 0.15 maximum side included. Plastic interlead protrusions 0.25 maximum side included. OUTLINE VERSION SOT361-1 REFERENCES JEDEC MO-153 EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27
TSSOP28 package outline.
9397 08969 Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Soldering
18.1 Introduction soldering surface mount packages
This text gives very brief insight complex technology. more in-depth account soldering found Data Handbook IC26; Integrated Circuit Packages (document order number 9398 90011). There soldering method that ideal surface mount packages. Wave soldering still used certain surface mount ICs, suitable fine pitch SMDs. these situations reflow soldering recommended.
18.2 Reflow soldering
Reflow soldering requires solder paste suspension fine solder particles, flux binding agent) applied printed-circuit board screen printing, stencilling pressure-syringe dispensing before package placement. Several methods exist reflowing; example, convection convection/infrared heating conveyor type oven. Throughput times (preheating, soldering cooling) vary between seconds depending heating method. Typical reflow peak temperatures range from top-surface temperature packages should preferable kept below thick/large packages, below small/thin packages.
18.3 Wave soldering
Conventional single wave soldering recommended surface mount devices (SMDs) printed-circuit boards with high component density, solder bridging non-wetting present major problems. overcome these problems double-wave soldering method specifically developed. wave soldering used following conditions must observed optimal results:
double-wave soldering method comprising turbulent wave with high
upward pressure followed smooth laminar wave.
packages with leads sides pitch (e):
larger than equal 1.27 footprint longitudinal axis preferred parallel transport direction printed-circuit board; smaller than 1.27 footprint longitudinal axis must parallel transport direction printed-circuit board. footprint must incorporate solder thieves downstream end.
packages with leads four sides, footprint must placed angle
transport direction printed-circuit board. footprint must incorporate solder thieves downstream side corners.
9397 08969
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
During placement before soldering, package must fixed with droplet adhesive. adhesive applied screen printing, transfer syringe dispensing. package soldered after adhesive cured. Typical dwell time seconds mildly-activated flux will eliminate need removal corrosive residues most applications.
18.4 Manual soldering
component first soldering diagonally-opposite leads. voltage less) soldering iron applied flat part lead. Contact time must limited seconds When using dedicated tool, other leads soldered operation within seconds between
18.5 Package related soldering information
Table Package BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, PLCC[3], LQFP, QFP, TQFP SSOP, TSSOP,
Suitability surface mount packages wave reflow soldering methods Soldering method Wave suitable suitable[2] Reflow[1] suitable suitable suitable suitable suitable
suitable recommended[3][4] recommended[5]
surface mount (SMD) packages moisture sensitive. Depending upon moisture content, maximum temperature (with respect time) body size package, there risk that internal external package cracks occur vaporization moisture them (the called popcorn effect). details, refer Drypack information Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. These packages suitable wave soldering. versions with heatsink bottom side, solder cannot penetrate between printed-circuit board heatsink. versions with heatsink side, solder might deposited heatsink surface. wave soldering considered, then package must placed angle solder wave direction. package footprint must incorporate solder thieves downstream side corners. Wave soldering only suitable LQFP, TQFP packages with pitch equal larger than definitely suitable packages with pitch equal smaller than 0.65 Wave soldering only suitable SSOP TSSOP packages with pitch equal larger than 0.65 definitely suitable packages with pitch equal smaller than
9397 08969
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Revision history
Table Date 20011127 Revision history CPCN Description Product specification (7379 08969). Modifications:
Changed Section "Features" second last item: into Section "DMA transfer" paragraph changed `activation' `reception'. Section 11.3.5 "Read buffer" first paragraph added. Section "Limiting values" Table "Limiting values" last note removed. Section "Static characteristics" Table characteristics (supply pins)" been removed; applicable Parameters have been moved next Table their Symbols have been changed. Section "Static characteristics" Table characteristics (AI/O pins)" first item both Symbol Parameter changed. Section "Dynamic characteristics" made following changes Table "Thermal characteristics" Third item both Symbol Parameter changed Second last item value moved column.
Section "Dynamic characteristics" Table characteristics (parallel interface)" locations value `130' been added column. Added Section 11.3.3 "Read Endpoint status". Made following changes Table characteristics (parallel interface)" Added t(WC Write Timings section. Added t(WC Read Timings section. Added last table notes.
Figure "Parallel interface timing (I/O DMA).", added t(WC WD), t(WC tRHNDV. Table "Limiting values" page changed Section "SoftConnect" added sentence "The decision make sure this feature lies with users." last sentence. Table "Set mode command, Configuration byte: allocation", changed from first row. Table "Clock division factor byte: allocation", added sentence "The minimum value giving range frequency from MHz" description Changed flow Section 11.3.1 "Read interrupt register". Moved Figure "Interrupt Register, byte allocation."before Table "Read interrupt register, byte allocation". Table "Limiting values": changed value field Ilatchupfrom changed value field Vesd from 4000 2000 added Conditions field Ptot.
Table "Recommended operating conditions", added field VCC1. Table characteristics (AI/O pins; FULL speed)[1]", removed |VOH VOL| from condition column first symbols.
9397 08969
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Table Date
Revision history.continued CPCN Description Modifications (continued):
20011127
Made following changes Table characteristics (DMA)": Parameter `DMACK_N HIGH DMREQ HIGH time' changed value from 330. Removed timings tALRL. Added timing tRHSH row. Changed value tSHAH from 130. Removed timing tWSH row. Section `Burst timings' changed Parameters their values. Added timing tRHNDV row.
20010423
Product specification; version Supersedes PDUIUSBD12_5 19990108 (9397 04979). Data sheet modifications:
Converted DBII template. Section "Interrupt modes" added. Section "Test information" created.
9397 08969
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Data sheet status
Data sheet status[1] Objective data Preliminary data Product status[2] Development Qualification Definition This data sheet contains data from objective specification product development. Philips Semiconductors reserves right change specification manner without notice. This data sheet contains data from preliminary specification. Supplementary data will published later date. Philips Semiconductors reserves right change specification without notice, order improve design supply best possible product. This data sheet contains data from product specification. Philips Semiconductors reserves right make changes time order improve design, manufacturing supply. Changes will communicated according Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
Please consult most recently issued data sheet before initiating completing design. product status device(s) described this data sheet have changed since this data sheet published. latest information available Internet
Definitions
Short-form specification data short-form specification extracted from full data sheet with same type number title. detailed information relevant data sheet data handbook. Limiting values definition Limiting values given accordance with Absolute Maximum Rating System (IEC 60134). Stress above more limiting values cause permanent damage device. These stress ratings only operation device these other conditions above those given Characteristics sections specification implied. Exposure limiting values extended periods affect device reliability. Application information Applications that described herein these products illustrative purposes only. Philips Semiconductors make representation warranty that such applications will suitable specified without further testing modification.
customers using selling these products such applications their risk agree fully indemnify Philips Semiconductors damages resulting from such application. Right make changes Philips Semiconductors reserves right make changes, without notice, products, including circuits, standard cells, and/or software, described contained herein order improve design and/or performance. Philips Semiconductors assumes responsibility liability these products, conveys licence title under patent, copyright, mask work right these products, makes representations warranties that these products free from patent, copyright, mask work right infringement, unless otherwise specified.
Trademarks
ACPI open industry specification power management, co-developed Intel Corp., Microsoft Corp. Toshiba GoodLink trademark Koninklijke Philips Electronics N.V. OnNow trademark Microsoft Corp. SoftConnect trademark Koninklijke Philips Electronics N.V.
Disclaimers
Life support These products designed life support appliances, devices, systems where malfunction these products reasonably expected result personal injury. Philips Semiconductors
Contact information
additional information, please visit sales office addresses, send e-mail
9397 08969
Fax: 24825
Koninklijke Philips Electronics N.V. 2001. rights reserved.
Product data
Rev. November 2001
Philips Semiconductors
PDIUSBD12
interface device with parallel
Contents
6.10 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.3.8 11.3.9 11.3.10 11.4 11.4.1 11.4.2 Description Features Pinning information Pinning description Ordering information Block diagram Functional description Analog transceiver Voltage regulator. clock recovery Philips Serial Interface Engine (PSIE) SoftConnect GoodLink Memory Management Unit (MMU) Integrated RAM. Parallel Interface Example parallel interface 80C51 microcontroller transfer Endpoint description Main endpoint. Command summary Command description Command procedure Initialization commands Address/Enable endpoint enable mode Data flow commands Read interrupt register Select Endpoint. Read Endpoint status Read last transaction status register Read buffer Write buffer Clear buffer Validate buffer endpoint status Acknowledge setup. General commands Send resume Read current frame number Interrupt modes Limiting values. Static characteristics. 18.1 18.2 18.3 18.4 18.5 Dynamic characteristics Test information. Package outline Soldering Introduction soldering surface mount packages Reflow soldering. Wave soldering. Manual soldering Package related soldering information Revision history Data sheet status. Definitions Disclaimers Trademarks
Koninklijke Philips Electronics N.V. 2001. Printed Netherlands
rights reserved. Reproduction whole part prohibited without prior written consent copyright owner. information presented this document does form part quotation contract, believed accurate reliable changed without notice. liability will accepted publisher consequence use. Publication thereof does convey imply license under patent- other industrial intellectual property rights. Date release: November 2001 Document order number: 9397 08969
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