basic Integrated Multiport Repeater (bIMR) DISTINCTIVE CHARACTERI
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Am79C982
basic Integrated Multiport Repeater (bIMR)
DISTINCTIVE CHARACTERISTICS
Fully backward-compatible with existing IMR/IMR+ device non-managed designs Pin/socket-compatible with Am79C980 (IMR) Am79C981 (IMR+) devices Repeater functions comply with IEEE 802.3 Repeater Unit specifications Four eight 10BASE-T port options available Low-cost, flexible solutions suitable non-managed repeater designs Integral 10BASE-T transceivers utilize required predistortion transmission technique Attachment unit interface (AUI) port allows connectivity with 10BASE-5 (Ethernet) 10BASE-2 (Cheapernet) networks, well 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) segments Minimum mode facilitates implementation provides four display options port status Built-in pulse stretching carrier sense display On-board PLL, Manchester encoder/decoder, display FIFO Expandable increase number repeater ports ports separately isolated (partitioned) response excessive collision conditions fault conditions Network management optional features accessible through dedicated serial management port Twisted-pair Link Test capability conforming 10BASE-T standard. receive Link Test function optionally disabled through management port facilitate interoperability with devices that implement Link Test function Programmable option Automatic Polarity Detection Correction permits automatic recovery wiring errors Full amplitude timing regeneration retransmitted waveforms Preamble loss effects eliminated deep FIFO CMOS device features high integration power with single supply
GENERAL DESCRIPTION
basic Integrated Multiport Repeater (bIMRTM) chip VLSI circuit that provides system-level solution designing compliant 802.3 repeater incorporating 10BASE-T transceivers. device integrates Repeater functions specified Section IEEE 802.3 standard twisted-pair Transceiver functions complying 10BASE-T standard. Am79C982-4 provides four Am79C982-8 provides eight integral twisted-pair medium attachment units (MAUs), attachment unit interface (AUI) port 84-pin plastic leaded chip carrier (PLCC). network based 10BASE-T standard uses unshielded twisted-pair cables, therefore providing economical solution networking allowing low-cost unshielded twisted-pair (UTP) cable existing telephone wiring. total number ports repeater unit increased connecting multiple bIMR devices through their expansion ports, hence minimizing total cost repeater port. Furthermore, general-purpose attachment unit interface (AUI) provides connection capability 10BASE-5 (Ethernet) 10BASE-2 (Cheapernet) coaxial networks, well 10BASE-F and/or Fiber Optic Inter-Repeater Link (FOIRL) fiber segments. Network management test functions provided through TTL-compatible pins. device fabricated CMOS technology requires single supply.
Publication# 19406 Rev: Amendment/0 Issue Date: January 1999
This document contains information product under development Advanced Micro Devices. information intended help evaluate this product. reserves right change discontinue work this proposed product without notice.
BLOCK DIAGRAM
Phase Locked Loop Port Manchester Decoder FIFO Preamble Sequence FIFO Control
RXD± TXD± TXP±
Port
Manchester Encoder
RXD± TXD± TXP± Port (Note) bIMR Chip Control Expansion Port Partitioning Link Test Reset
Clock Timers Test Management Port SCLK TEST 19406B-1
Note: Am79C982-4 Am79C982-8.
RELATED PRODUCTS
Part Am79C98 Am79C100 Am7996 Am79C981 Am79C987 Am79C940 Am79C90 Am79C900 Am79C960 Am79C961 Am79C965 Am79C970 Am79C974 Description Twisted Pair Ethernet Transceiver (TPEX) Twisted Pair Ethernet Transceiver Plus (TPEX+) IEEE 802.3/Ethernet/Cheapernet Transceiver Integrated Multiport Repeater Plus (IMR+) Hardware Implemented Management Information Base(HIMIBTM) Media Access Controller Ethernet (MACETM) CMOS Local Area Network Controller Ethernet (C-LANCE) Integrated Local Area Communications Controller(ILACCTM) PCnet-ISA Single-Chip Ethernet Controller (for bus) PCnet-ISA+ Single-Chip Ethernet Controller (with Microsoft® Plug Play® Support) PCnet-32 Single-Chip 32-Bit Ethernet Controller PCnet-PCI Single-Chip Ethernet Controller (for bus) PCnet-SCSI Combination Ethernet SCSI Controller Systems
Am79C982
CONNECTION DIAGRAM
PLCC
RXD0+ RXD0- AVSS RXD1+ RXD1- RXD2+ RXD2- RDX3+ RXD3- AVDD
RXD4+ RXD4- RXD5+ RXD5- RXD6+ RXD6-
TXD0+ TXD0- DVSS TXP0+ TXP0- DVDD TXD1+ TXD1- TXP1+ TXP1- TXD2+ TXD2- TXP2+ TXP2- DVDD TXD3+ TXD3- DVSS TXP3+ TXP3- DVSS DVSS SCLK TEST DVDD DVSS DVDD DVSS RXD7- TXD7+ TXD7- DVSS TXP7+ TXP7- DVDD TXD6+ TXD6- TXP6+ TXP6- TXD5+ TXD5- TXP5+ TXP5- DVDD TXD4+ TXD4- DVSS TXP4+ TXP4-
bIMR Chip Am79C982-8
RXD7+
19406B-2
Am79C982
CONNECTION DIAGRAM
PLCC
(Note) AVSS RXD0+ RXD0- (Note) RDX1+ RXD1- AVDD (Note) RXD2+ RXD2- (Note)
DVSS DVDD TXD0+ TXD0- TXP0+ TXP0- DVDD TXD1+ TXD1- DVSS TXP1+ TXP1- DVSS DVSS SCLK TEST DVDD DVSS DVDD DVSS RXD3- TXD3+ TXD3- DVSS TXP3+ TXP3- DVDD TXD2+ TXD2- TXP2+ TXP2- DVDD DVSS
bIMR Chip Am79C982-4
RXD3+
19406B-3
Note: Recommended tied together.
Am79C982
LOGIC SYMBOL
DVDD Management Port SCLK TEST DVSS
AVDD TXD+ TXP+ TXD- TXP- RXD+ RXD- Twisted Pair Ports Ports)
Am79C982
Expansion Port
AVSS
Port Activity Monitor
19406B-4
LOGIC DIAGRAM
Management Port
Repeater State Machine
Expansion Port
Twisted Pair Port
Twisted Pair Port (Note)
Note: Am79C982-4 Am79C982-8.
19406B-5
Am79C982
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (valid combination) formed combination elements below.
Am79C982
OPTIONAL PROCESSING Blank Standard Processing
TEMPERATURE RANGE Commercial (0°C +70°C)
PACKAGE TYPE 84-Pin Plastic Leaded Chip Carrier 084)
SPEED OPTION bIMR 10BASE-T ports bIMR 10BASE-T ports DEVICE NUMBER/DESCRIPTION Am79C982 basic Integrated Multiport Repeater (bIMR)
Valid Combinations Am79C982-4 Am79C982-8
Valid Combinations Valid combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C982
DESCRIPTION
Acknowledge Input, Active When this input asserted, signals requesting bIMR device that control pins. bIMR chip requesting control line (REQ HIGH), then assertion signal indicates presence valid collision status valid data line.
occurred, corresponding output stream will remain 2-ms period will reset this period.
Data Input/Output/3-State non-collision conditions, active bIMR device will drive with data, including regenerated preamble. During collision, when HIGH, used signal multiport (DAT single-port (DAT condition. When asserted, high impedance. both asserted, then output. asserted asserted, then input. This needs either pulled pulled down through high-value resistor.
AVDD
Analog Power Power These pins supply RXD+/- receivers, DI+/- CI+/- receivers, DO+/- drivers, internal PLL, internal voltage reference bIMR device. These power pins should decoupled kept separate from other power ground planes.
DI+,
Data Input port differential receiver. Signals comply with IEEE 802.3, Section
AVSS
Analog Ground Ground These pins reference AVDD.
Expansion Collision Input, Active When this input asserted external arbiter, signifies that more than bIMR device active that each bIMR device should generate Collision sequence independently.
DO+,
Data Output port differential driver. Signals comply with IEEE 802.3, Section
DVDD
Digital Power Power These pins supply logic portions bIMR chip TXP+/-, TXD+/-, DO+/- line drivers.
CI+,
Control Input port differential receiver. Signals comply with IEEE 802.3, Section
DVSS
Digital Ground Ground These pins reference DVDD.
DVDD DVSS Function ports drivers ports drivers Core logic expansion control pins ports drivers ports drivers
Carrier Sense Output states internal carrier sense signals port eight twisted-pair ports serially output this continuously. output serial stream synchronized clock. resolution signal incoming data sampled repeatedly during each 2-ms period. activity occurs (regardless length) during 2-ms period, this activity will latched. start next 2-ms period bIMR device will examine latches each port. port which activity
Am79C982
Input/Output/3-State When asserted, state will indicate either multiport (DAT single-port (DAT collision condition. When asserted, high impedance. both asserted, then output. asserted asserted, then input. This needs either pulled pulled down through high-value resistor.
Minimum mode, state deassertion signal determines programming automatic polarity detection/correction 10BASE-T ports.
Serial Output normal operating mode, used test/ management serial output port. Management results clocked this synchronous SCLK input. Minimum mode, used output various status information serially based state SCLK pins.
SCLK Output Ports Receive Polarity Status Test Error Status Rate Error (all ports) Ports Link Status Loopback Status Port Partitioning Status (all ports)
Request Output, Active This driven when bIMR chip active. bIMR chip active when more ports receiving colliding state where still transmitting data from internal FIFO. assertion this signal signifies that bIMR device requesting lines transfer repeated data collision status other bIMR devices.
Store Output goes HIGH clock cycle times after nine carrier sense bits output pin. Note that carrier sense signals arriving from each port latched internally, that active transition remembered between samples.
Reset Input, Active Driving this resets internal logic bIMR device. Reset should synchronized clock either expansion port activity monitor used.
RXD+0-7, RXD-0-7 (RXD+0-3, RXD-0-3)
Receive Data Input 10BASE-T port differential receive inputs ports).
TEST
Test Input, Active HIGH This should tied normal operation. this driven HIGH, then bIMR device programmed Loopback Test mode. Also, this HIGH when deasserted, bIMR device will enter Minimum mode. inverted version signal used program device into Minimum mode.
Test Functions Normal Management Mode Normal Management Mode Minimum Mode, Receive Polarity Correction Disabled Minimum Mode, Receive Polarity Correction Enabled
SCLK
Serial Clock Input normal operating mode, serial data (input output) clocked out) rising edge signal this pin. SCLK asynchronous operate MHz. Minimum mode, this pin, together with pin, controls which information output pin.
Serial Input normal operating mode, used test/ management serial input port. Management commands clocked this synchronous SCLK input. Minimum mode, this pin, together with SCLK pin, controls which information output pin.
1-10
Am79C982
TXD+0-7, TXD-0-7 (TXD+0-3, TXD-0-3)
Transmit Data Output 10BASE-T port differential drivers ports).
Crystal Crystal Connection internal clock generator uses crystal attached pins Alternatively, external 20MHz CMOS clock signal used drive this pin.
TXP+0-7, TXP-0-7 (TXP+0-3, TXP-0-3)
Transmit Predistortion Output 10BASE-T transmit waveform predistortion control differential outputs ports).
Crystal Crystal Connection internal clock generator uses crystal attached pins external clock source used, this should left unconnected.
Am79C982
1-11
PRELIMINARY conditions correctly specified Section 802.3 specification.
FUNCTIONAL DESCRIPTION
Am79C982 Basic Integrated Multiport Repeater device single chip implementation IEEE 802.3/Ethernet repeater hub). offered either with four eight integral 10BASE-T ports plus port comprising basic repeater. bIMR device also expandable, enabling implementation high port count repeaters based several bIMR devices. bIMR chip complies with full repeater basic functions defined section 8802.3 (ANSI/IEEE 802.3c). These functions summarized below.
Fragment Extension
total packet length received bIMR device less than bits, including preamble, bIMR chip will extend repeated packet length bits appending sequence original fragment.
Auto Partitioning/Reconnection
integral ports port partitioned under excessive duration frequency collision conditions. Once partitioned, bIMR device will continue transmit data packets partitioned port, will respond repeater) activity partitioned port's receiver. bIMR chip will monitor port reconnect once certain criteria indicating port `wellness' met. criteria reconnection specified 802.3 standard. addition standard reconnection algorithm, bIMR device implements alternative reconnection algorithm which provides more robust partitioning function ports and/or port. Each port port partitioned and/or reconnected separately independently other network ports. Either following conditions occuring enabled bIMR device network port will cause port partition: collision condition exists continuously time between 1024- 2048-bit times (AUI port-SQE signal active; port-simultaneous transmit receive) collision condition occurs during each consecutive attempts transmit that port. Once network port partitioned, bIMR device will reconnect that port following met: Standard reconnection algorithm-A data packet longer than 512-bit times (nominal) transmitted received partitioned port without collision. Alternate reconnection algorithm-A data packet longer than 512-bit times (nominal) transmitted partitioned port without collision. reconnection algorithm option (standard alternate) global function ports, i.e. ports same reconnection algorithm. reconnection algorithm option programmed independently port reconnection option.
Repeater Function
single network port senses start valid packet receive lines, then bIMR device will retransmit received data other enabled network ports. repeated data will also presented line facilitate multiple-bIMR device repeater applications.
Signal Regeneration
When re-transmitting packet, bIMR device ensures that outgoing packet complies with 802.3 specification terms preamble structure, voltage amplitude, timing characteristics. Specifically, data packets repeated bIMR chip will contain minimum preamble bits before Start Frame Delimiter. addition, voltage amplitude repeated packet waveform will restored levels specified 802.3 specification. Finally, signal symmetry restored data packets repeated bIMR device, removing jitter distortion caused network cabling.
Jabber Lockup Protection
bIMR chip implements built-in jabber protection scheme ensure that network disabled transmission excessively long data packets. This protection scheme will automatically interrupt transmitter circuits bIMR device 96-bit times bIMR device been transmitting continuously more than 65,536-bit times. This referred Jabber Lockup Protection (MJLP). MJLP status bIMR chip read through Management Port using MJLP Status command returned).
Collision Handling
bIMR chip will detect respond collision conditions specified 802.3. multiple-bIMR device repeater implementation also complies with 802.3 specification inter-bIMR chip status communication provided expansion port. Specifically, repeater based more bIMR devices will handle transmit collision one-port-left collision 1-12
Link Test
integral ports implement Link Test function specified 802.3 10BASE-T standard. bIMR device will transmit Link Test pulses port after
Am79C982
PRELIMINARY that port's transmitter been inactive more than Conversely, port does receive data packets Link Test pulses more than Link Test function enabled that port then that port will enter link fail state. port link fail state will disabled bIMR chip (repeater transmit receive functions disabled) until receives either four consecutive Link Test pulses data packet. Link Test receive function itself disabled bIMR chip management port port-by-port basis allow bIMR device interoperate with pre-10BASE-T twisted pair networks that implement Link Test function. This interoperability possible because bIMR device will allow port enter link fail state, even Link Test pulses data packets being received. Note however that bIMR chip will always transmit Link Test pulses ports regardless whether port enabled, partitioned, link fail state, Link Test receive function disabled.
Reset
bIMR device enters reset state when driven LOW. After initial application power, must held minimum (3000 clock cycles). subsequently asserted while power maintained bIMR device, reset duration only required. bIMR chip continues reset state clocks (0.5 following rising edge RST. During reset, output signals placed their inactive states. This means that analog signals placed their idle states, bidirectional signals driven, active signals driven HIGH, active HIGH signals driven LOW. internal circuit ensures that minimum reset pulse generated internal circuits. input with slow rising edge, input buffer threshold crossed several times ripple input waveform. multiple bIMR chip repeater signal should applied simultaneously bIMR devices should synchronized external clock. Reset synchronization also required when accessing (Port Activity Monitor). signal should held HIGH least following rising edge RST. Table summarizes state bIMR chip following reset.
Polarity Reversal
ports have optional (programmable) ability invert (correct) polarity received data port senses that received data packet waveform polarity reversed wiring error. This receive circuitry polarity correction allows subsequent packets repeated with correct polarity. This function executed once following reset link fail, programmable enable/disable option port-by-port basis. This function disabled upon reset enabled bIMR chip Management Port.
Table bIMR Chip After Reset
Function Active outputs Active HIGH outputs Output DAT, Transmitters AUI) Receivers AUI) Partitioning/Reconnection Algorithm Port Partitioning/Reconnection Algorithm Link Test Function Ports Automatic Receiver Polarity Reversal Function HIGH HIGH HI-IMPEDANCE IDLE ENABLED STANDARD ALGORITHM STANDARD ALGORITHM ENABLED, PORTS LINK FAIL DISABLED State After Reset Pull Up/Pull Down Either Terminated
Am79C982
1-13
PRELIMINARY than active bIMR device time constitutes collision condition, bIMR devices notified this occurence line Expansion Port. Note that transition from multiple bIMR devices arbitrating pins (with asserted, deasserted) condition when only bIMR chip arbitrating pins (with asserted, deasserted) involves expansion port cycle (100 ns). During this transitional cycle, deasserted, asserted, pins driven. However, each bIMR device will remain collision state (transmitting sequence) during this transitional cycle. subsequent expansion port cycles (REQ still asserted), bIMR devices will return `master slaves' condition where only bIMR device active (with collision) driving pins. understanding this sequence crucial nonbIMR devices (such Ethernet controller) connected expansion bus. Specifically, last device back Expansion Port after multibIMR chip collision must assert line until drops request Expansion Port.
Expansion Port
bIMR chip Expansion Port comprised five pins; bi-directional signals (DAT JAM), input signals (ACK COL), output signal (REQ). These signals used when multiple-bIMR device repeater application employed. this configuration, bIMR chips must clocked synchronously with common clock connected inputs bIMR devices. Reset needs synchronized clock. bIMR device expansion scheme allows multiple bIMR chips single board repeater modular multiport repeater with backplane architecture. bidirectional which used transfer data between bIMR devices multiple-bIMR chip design. data sent over line format synchronized common clock. another bidirectional that used active bIMR chip communicate internal status remaining (inactive) bIMR devices. When asserted HIGH, indicates that active bIMR device detected collision condition generating Sequence. During this time when asserted HIGH, line used indicate whether active bIMR chip detecting collision port only more than port. When driven HIGH bIMR chip (while asserted bIMR chip), then active bIMR device detecting collision condition port only. This `one-port-left' signaling necessary multiple-bIMR device repeater function correctly single multiport repeater unit. bIMR chip also signals `one port left' collision condition event runt packet collision fragment; this signal will continue expansion port cycle (100 before deasserting REQ. arbitration access bussed bi-directional signals (DAT JAM) provided output (REQ) inputs (ACK COL). bIMR chip asserts indicate that active wishes drive pins. external arbiter senses lines from bIMR devices asserts line when only bIMR chip asserting line. more than bIMR chip asserting line, arbiter must assert signal, indicating that more than bIMR device active. More
External Arbiter
simple arbitration scheme required when multiple bIMR devices connected together increase total number repeater ports. arbiter should have input (REQ1.REQn) each bIMR devices used, global outputs (COL ACK). This function easily implemented PAL® device, with following logic equations:
REQ1 REQ2 REQ3 .REQn REQ1 REQ2 REQ3 .REQn
REQ1 REQ2 REQ3 REQn (REQ1 REQ2 REQ3 REQn)
Above equations positive logic, i.e., variable true when asserted. single PALCE16V8 will perform arbitration function repeater based several bIMR devices.
1-14
Am79C982
REQ2 REQ3 REQ1 ARBITER
transceivers needed buses exceed loading.
ASYNC RESET Note
Am79C982 bIMR Chip
XTAL OSC.
Am79C982 bIMR Chip
Note Direction HIGH
Am79C982
bIMR Chip
19406B-6
Figure Multiple bIMR Devices
Modular Repeater Design
expansion port bIMR chip also allows modular expansion. sharing arbitration duties between backplane architecture several separate repeater modules build expandable
repeater based modular `plug-in' cards. Each repeater module performs local arbitration function bIMR devices that module, provides signals backplane global arbiter.
Am79C982
1-15
PRELIMINARY necessary loading this example. this case, arbiter simply asserts signal asserted both signals asserted. arbiter does assert either signal neither asserted. Note that both logic when asserted. type flip flop used synchronize reset signals both bIMR devices order ensure that internal clocks these devices phase. More complex repeaters, including stackable hubs, built using bIMR family. these cases, transceivers necessary arbitration distributed throughout system.
Implementing 12-Port Unmanaged
Both bIMR4 bIMR8 chips have expansion that allows multiple devices connected together, allowing high port count repeaters designed. operation expansion identical bIMR4 bIMR8. Minimum Mode available both bIMR4 bIMR8 devices. This mode facilitates implementation display unmanaged hub. Figure shows simple example where four port bIMR device eight port bIMR device connected together form twelve port logical unmanaged repeater. both devices same board arbiter function local, transceivers shown right Figure
1-16
Am79C982
REQ1 REQ2
ARBITER
bIMR8
ASYNC RESET TEST SCLK
TEST
bIMR4
SCLK
SHIFT
SHIFT
SHIFT
SHIFT
PORT STATUS LEDS
Notes: Both bIMR8 bIMR4 devices used Minimum Mode.
PORT ACTIVITY LEDS
19406B-7
information displayed Port Status LEDs selected SW1. this design, only Link Status Port Partition Status selected. Users implement more display options changing state SCLK input (see section Minimum Mode detail). Polarity correction feature shown disabled since high reset. Users enable this feature keeping input upon reset.
Figure Implementing 12-Port Unmanaged using bIMR8 bIMR4
Am79C982
1-17
PRELIMINARY setup hold times with respect input pattern. latter method used, noted that SCLK clock transitions required proper execution management commands that produce data, that SCLK clock transitions needed execute management commands that produce data.
Management Port
bIMR device management functions enabled when TEST tied LOW. management commands byte oriented data input serially pin. responses generated during execution management command output serially byteoriented format bIMR device pin. Both input output data streams clocked with rising edge SCLK pin. serial command data stream associated results data stream structured manner similar RS232 serial data format, i.e., Start followed eight Data Bits. externally generated clock SCLK either free running clock synchronized input patterns series individual transitions meeting
Command Execution Phase
Management Commands
following section details operation each management command available bIMR chip. cases, individual bits each command byte shown with left right. Data bytes received transmitted first last. Table summary management commands.
Results Phase
Next Command
SCLK
STRT
STRT 19406B-8
Management Command/Response Timing
Command Execution Phase
Next Command Execution Phase
SCLK
STRT STRT 19406B-9
Management Command Timing with Response
1-18
Am79C982
PRELIMINARY Table Management Port Command Summary
Commands (Write) Opcodes bIMR Chip Programmable Options Alternate Partitioning Algorithm Alternate Partitioning Algorithm Port Disable Port Enable Port Disable Port Enable Disable Link Test Function (per port) Enable Link Test Function (per port) Disable Automatic Receiver Polarity Reversal (per port) Enable Automatic Receiver Polarity Reversal (per port) (Read) Opcodes Port Status Cleared) Port Partitioning Status Rate Status ports Link Test Status ports Receive Polarity Status ports MJLP Status Version Port Status Cleared) Port Status Cleared) Port Status (None Cleared) 1000 1111 1000 0000 1010 0000 1101 0000 1110 0000 1111 0000 1111 1111 1000 1011 1000 1101 1000 1001 PBSL 0000 0000 10SA 0001 1111 0001 0000 0010 1111 0011 1111 0010 0### (note 0011 0### 0100 0### 0101 0### 0110 0### 0111 0### Data Data
C7.C0 (bIMR8), C3.C0 (bIMR4) E7.E0 (bIMR8), E3.E0 (bIMR4) L7.L0 (bIMR8), L3.L0 (bIMR4) P7.P0 (bIMR8), P3.P0 (bIMR4) M000 0000 XXXX 0101 PBSL 0000 PBSL 0000 PBSL 0000
Notes: Unused opcodes reserved future use. Select code twisted pair ports (TP0 TP7).
bIMR8
bIMR4
Am79C982
1-19
PRELIMINARY stream) masked port either disabled partitioned. This does allow Repeater Management software sense activity segments times. ability monitor partitioned disabled ports allows fault tolerance built into Repeater Management software. Alternate Port Partitioning Algorithm data: data: 00011111 None
(Write) Opcodes
bIMR Chip Programmable Options data: data: 0000 10SA None
bIMR Chip Programmable Options enabled (disabled) setting (resetting) appropriate command string. programmable bits are: S-AUI Test Mask, A-Alternative Port Activity Monitor (PAM) Function. These options enabled (disabled) setting (resetting) appropriate command string. S-AUI Test Mask Setting this allows bIMR chip ignore activity signal pair, Test Window, following transmission port. This event occurs when attached Test option enabled, therefore generating burst activity following every transmission. This interpreted bIMR device collision, causing bIMR device generate full pattern. Although attached repeater required have test function active, this common installation error, causing difficulty diagnosing network throughput problems. Test Window, defined IEEE 802.3 (Section 7.2.2.2.4), from 6-bit times 34-bit times (0.6 µs). This includes delay introduced AUI. activity that occurs outside this window ignored treated true collision. Note that enabling this function does prevent reporting this condition bIMR device functions operate independently. A-Alternative Port Activity Monitor (PAM) Function Setting Alternative Port Activity Monitor Function allows function altered such that Carrier Sense data presented unmodified. default operation output (Carrier Sense bits
port Partitioning/Reconnection scheme programmed alternate (transmit only) reconnection algorithm invoking this command. return back standard (transmit receive) reconnection algorithm, necessary reset bIMR device. Standard partitioning algorithm selected upon reset. Alternate Ports Partitioning Algorithm data: data: 00010000 None
ports Partitioning/Reconnection scheme programmed alternate (transmit only) reconnection algorithm invoking this command. ports affected group this command. return ports back standard (transmit receive) reconnection algorithm, necessary reset bIMR device. standard partitioning algorithm selected upon reset. Port Disable data: data: 00101111 None
port will disabled upon receiving this command. Subsequently, bIMR chip will ignore inputs (Carrier Sense SQE) appearing port will transmit data Sequence port. Issuing this command will also cause port have internal partitioning state machine forced idle state. Therefore, Partitioned Port reconnected first disabling then re-enabling port.
1-20
Am79C982
PRELIMINARY Port Enable data: data: 00111111 None Enable Link Test Function Port data: data: 01010### None
This command enables previously disabled port. Note that partitioned port reconnected first disabling (AUI Port Disable Command) then reenabling port with this command. ports enabled upon reset. Port Disable data: data: 00100### None
(### selects port number, note page This command re-enables Link Test Function port designated command byte. This command executes only designated port Link Test Function disabled Disable Link Test Function command. Otherwise, command ignored. Link Test enabled upon reset. Disable Automatic Receiver Polarity Reversal data: data: 01100### None
(### selects port number, note page port designated command byte will disabled upon receiving this command. Subsequently, bIMR device will ignore inputs appearing disabled port's receive pins will transmit data Sequence that port's transmit pins. Issuing this command will also cause port have partitioning state machine returned Idle State (Port Reconnected). Therefore, partitioned port reconnected first disabling then re-enabling port. disabled port will continue report correct Link Test Status. Port Enable data: data: 00110### None
(### selects port number, note page This command disables Automatic Receiver Polarity Reversal Function port designated command byte. this function disabled port with reverse polarity (due wiring error), then port will fail Link Test reversed polarity Link Pulses. Link Test Function also disabled port, then received reversed polarity packets would repeated other network ports bIMR chip inverted data. Automatic Polarity reversal disabled upon reset. Enable Automatic Receiver Polarity Reversal data: data: 01110### None
(### selects port number, note page This command enables previously disabled port. Re-enabling disabled port causes port placed into Link Test Fail state. This ensures that packet fragments received port repeated rest network. Note that force port into Link Fail state and/or reconnect partitioned port, port should first disabled Port Disable Command) then re-enabled with this command. ports enabled upon reset. Disable Link Test Function Port data: data: 01000### None
(### selects port number, note page This command enables Automatic Receiver Polarity Reversal Function port designated command byte. enabled port, bIMR chip will automatically invert polarity that port's receiver circuitry port detected having reversed polarity (due wiring error). After reversing receiver polarity, port could then receive subsequent (reverse polarity) packets correctly.
(Read) Opcodes
Port Status data: data: 10001111 PBSL0000
(### selects port number, note page This command disables Link Test Function port designated command byte, i.e., port will longer disconnected Link Fail. port which Link Test Function disabled will continue transmit Link Test Pulses. twisted pair port Link Test disabled, then reading Link Test Status indicates being Link Test Pass.
combined status allows single instruction used monitoring port. four status bits reported are: Partitioning Status. This port partitioned connected.
Am79C982
1-21
PRELIMINARY Port Link Test Fail Port Link Test Pass
Rate Error. This there been instance FIFO Overflow Underflow, caused data received port. This cleared when status read. Test Status. This Test detected bIMR chip. This cleared when status read. attached repeater must have Test disabled. This even port disabled partitioned. Loop Back Error. attached required loopback data transmitted onto circuit. loopback carrier detected bIMR device, then this report this condition. This cleared when status read. repeater this only indication broken missing MAU. Port Partitioning Status data: data: data: 10000000 P7.P0 (bIMR8) (bIMR4) don't care port partitioned port connected
Link Test Status eight (four) ports accessed this command. disabled port continues report correct Link Test Status. Re-enabling disabled port causes port placed into Link Test Fail state. This ensures that packet fragments received port repeated rest network. Receive Polarity Status Ports data: data: data: 11100000 P7.P0 (bIMR8) (bIMR4) don't care Port Polarity Correct Port Polarity Reversed
statuses eight (four) port polarities accessed with this command. bIMR chip ability detect correct reversed polarity ports' RXD+/- pins. polarity detected reversed port, then bIMR chip will appropriate this command's result byte only Polarity Reversal Function enabled that port. MJLP Status data: data: 11110000 M00000000
partitioning Status four eight ports accessed this command. port disabled, reading partitioning status will indicate that connected. Rate Error Status Ports data: data: data: 10100000 E7.E0 (bIMR8) (bIMR4) don't care
This allows single command used report Rate Error condition (FIFO Overflow Underflow) Twisted Pair ports. bits bits) output pattern correspond each ports, with least significant corresponding port status port there been instance when data received from that port caused FIFO error. status bits stay until status read. Link Test Status Ports data: data: data: 11010000 L7.L0 (bIMR8) (bIMR4) don't care
Each bIMR chip contains independent Jabber Lock Protection Timer. timer designed inhibit bIMR device transmit function, been transmitting continuously more than 65536 Times. MJLP Status this happens. This remains only cleared when MJLP status read using this command. Version data: data: 11111111 XXXX0001
This command (1111 1111) used determine device version. bIMR chip responds pattern: XXXX 0101
1-22
Am79C982
Minimum Mode
Minimum Mode reconfigures bIMR device Management Port intended provide support end, non-managed repeaters, requiring minimal external logic provide indication
Twisted Pair Ports Link Status indication
Minimum Mode, used serially output various status information based state SCLK pins. summary status information provided following table.
SCLK Output Ports Receive Polarity Status Test Error Status. Rate Error (all ports). Ports Link Status LoopBack Status Port Partitioning Status (all ports)
Loopback Status
Port Partitioning Status Twisted Pair Ports Receiver Polarity Status
Test Error Status
Port Rate Error Status
Minimum Mode selected controlling state TEST while asserted. TEST High (asserted), while reset active (RST LOW), then Minimum Mode selected. state pin, deassertion signal, determines whether bIMR chip programmed Automatic Polarity Detection/Correction. When entering Minimum Mode, TEST input deasserted rising edge reset. maximum delay allowed account slow devices. following table summarizes different modes available.
Test Functions Normal Management Mode Normal Management Mode Minimum Mode, Receive Polarity Correction disabled Minimum Mode, Receive Polarity Correction enabled
When then will output related status bits (LoopBack SQE), followed status bits (Link Polarity), starting with port When Port Partitioning Status Port Rate Error Status scanned with first ports following. Port scanned first.
Note that Rate Error, Loopback, Test Error status bits stay until they scanned out.
state SCLK inputs checked every cycle. rising edge clock, occurring before falling edge STR, used strobe state SCLK pins. this Minimum Mode, Management Port mode active. exit Minimum mode, bIMR device must reset into normal Management Port mode.
XTAL
SIPO
ASYNC RESET TEST
Am79C982 bIMR8 Chip
Register
SCLK
19406B-10
Figure bIMR8 Display Design using Minimum Mode Am79C982 1-23
(Note
(Note
Notes: Externally generated signal illustrates internal bIMR chip clock phase relationship. Minimum Mode
19406B-11
Figure bIMR8 Management Port Minimum Mode Port Activity Monitor Signal Relationship
SHCK XTAL (Note) Shift Register
bIMR4 Chip
ASYNC RESET
19406B-12
Register
Note: When used minimum mode.
Figure bIMR4 Display Design using Minimum Mode
1-24
Am79C982
SHCK (Note)
Note: When used minimum mode.
19406B-13
Figure bIMR4 Management Port Minimum Mode Port Activity Monitor Signal Relationship
Port Activity Monitor
pins, STR, used serially output state internal Carrier Sense signals from eight (four) ports. This function together with external hardware and/or software used monitor repeater receive and/or collision activity. resolution signal incoming data sampled repeatedly during each period. activity occurs (regardless length) during period, this activity will latched. start next period, bIMR device will examine latches each port. port which activity occurred, corresponding output stream will remain period. This means that during time interval output stream represents carrier activity that occurred preceding period (see Figure During last
1000 period, signal reset LOW. Figure illustrates this showing output register recommended drive circuitry Figure used indicate carrier sense nine ports device (five Am79C982-4). This outputs stream that repeats every microsecond. During this period there times (100 ns). Each port "time slot" this repeating stream (see Figure example, activity port represented state during second period microsecond cycle. Because microsecond sequence repeated unchanged most longer cycle, driven latch shift register shown Figure will remain least This minimizes need external pulse stretching logic.
1000
19406B-14
Figure Carrier Sense Signal Output Corresponding States Twisted-Pair Port Activity
Am79C982
1-25
XTAL
Shift Register SIPO
ASYNC RESET
Am79C982 bIMR8 Chip
Register
19406B-15
Carrier Sense Outputs
Figure bIMR8 Port Activity Monitor Implementation
1-26
Am79C982
APPENDIX
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10BASE-T INTERFACE
table below lists recommended resistor values filter transformer modules IMR+ device.
bIMR+ Device Compatible 10BASE-T Media Interface Modules
Manufacturer Part
S556-5999-32 0556-2006-14 A556-2006-DE A556-2006-00 FS02-101Y4 FS12-101Y4 FS22-101Y4 FD02-101G FD12-101G FD22-101G FD22-101R2 5408-37 5408-40 6612-21 EPA1990A EPA1990AG EPA2013D EPA2013DG 78Z034C 78Z1120B-01 78Z1122B-01 PE-68017S PE-68026 PE-68056 PE-68032 TLA-3M601-RS TLA-3M102(-T) TLA-3M103(-T) PT3877 PT3983 FL1012
Package
16-pin 10-pin 16-pin 0.3" 16-pin "Slim SIP" "Slim SIP" "Slim SIP" 16-pin 0.3" 16-pin 0.3" 16-pin 0.3" 16-pin 0.3" 16-pin 9-pin 12-pin 16-pin 0.3" device 16-pin 0.3" device 16-pin 16-pin 16-pin 10-pin 16-pin 16-pin 13-pin PCMCIA-SMT 10-pin 16-pin 16-pin 16-pin 0.3" 8-pin 0.3" 16-pin 0.3"
Description
Transmit receive filters, transformers common mode chokes. Transmit receive filters, transformers common mode chokes. Transmit receive filters transformers. Transmit filter, transformers common mode choke. Receive filter transformer. Transmit receive filters transformers. Transmit receive filters transformers, transmit common mode reduction choke. Transmit receive filters, transformers common mode chokes. Transmit receive filters transformers. Transmit receive filters transformers, transmit common mode choke. Transmit receive filters, transformers common mode chokes. Termination equalization resistors, transmit receive filters, transformers common mode chokes. pole transmit receive filters with 1CT:1CT Xfmrs (transmit receive) separate common mode choke each channel. pole transmit receive filters with 1CT:1CT Xfmrs (transmit receive) separate common mode choke each channel. pole transmit receive filters with 1CT:1CT Xfmrs (transmit receive) separate common mode choke each channel. Transmit receive filters transformers. Transmit receive filters transformers. Transmit receive filters transformers, transmit common mode choke. Transmit receive filters transformers, transmit common mode choke. Transmit receive filters transformers, transmit common mode chokes. Transmit receive filters transformers. Transmit receive filters, transformers common mode chokes. Transmit receive filters, transformers common mode chokes. Transmit receive filters, transformers common mode chokes. Transmit receive filters, transformers common mode chokes. Transmit receive filters transformers, transmit common mode chokes. Transmit receive filters transformers, transmit common mode chokes. Integrated resistors, transmit receive filters transformers, transmit common mode chokes. Transmit receive filters transformers, transmit common mode chokes. Transmit receive filters transformers. Transmit receive common mode chokes. Transmit receive filters transformers, transmit common mode chokes.
Am79C982
1-27
APPENDIX
Glossary
Active Status non-collision state, bIMR chip considered active receiving data network ports, process broadcasting (repeating) FIFO data from recently completed data reception. collision state (the bIMR device generating Sequence), bIMR device considered active more network ports receiving data. bIMR device asserts line indicate that active. Collision carrier sense multiple access/collision detection (CSMA/CD) network such Ethernet, only node successfully transfer data time. When more separate nodes (DTEs repeaters) simultaneously transmitting data onto network, Collision state exists. repeater using more bIMR devices, Collision state exists when more than network port receiving data instant, when more network ports receives data while bIMR device transmitting (repeating) data, when CI+/- pins become active (nominal signal) port. Sequence signal consisting alternating that generated bIMR device when Collision state detected. This signal transmitted bIMR device indicate network that more network ports repeater involved collision. Network Port eight (four) 10BASE-T ports port present bIMR device (i.e. Expansion Port Management Port). Partitioning network port repeater been partitioned repeater internally `disconnected' from repeater localized faults that would otherwise bring entire network down. These faults generally cable shorts opens that tend cause excessive collisions network ports. partitioned network port will internally re-connected network port starts behaving correctly again, usually when successful `collisionless' transmissions and/or receptions resume. Receive Collision network port Receive Collision state when detects collision colliding network 'nodes'. This applies mainly non-transmitting port because remote collision clearly identified presence nominal signal CI+/pins. However, repeater port would considered receive collision state repeater unit receiving data from that port `one-port-left' collision sequence. Transmit Collision network port Transmit Collision state when collision occurs while that port transmitting. port, Transmit Collision indicated presence nominal signal CI+/- pins while port transmitting DO+/- pins. 10BASE-T port, Transmit Collision occurs when incoming data appears RXD+/- pins while 10BASE-T port transmitting TXD+/- TXP+/- pins.
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Am79C982
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