QUALITY SEMICONDUCTOR, INC. SuperSync Controller Clock Driver
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QS5940 PRELIMINARY
QUALITY SEMICONDUCTOR, INC.
SuperSync Controller Clock Driver
DESCRIPTION
QS5940 PRELIMINARY
clock outputs Internal loop filter tolerant inputs Output enable (OE) lock indicator output Extended 85°C operation skew guaranteed between outputs Sense control input output jitter 3.0V 3.6V supply voltage Available 28-pin QSOP package
QS5940 high-performance, skew, jitter phase-locked loop (PLL) clock driver. banks outputs programmed generate multiple copies different clock frequencies from single system clock input. QS5940 been specially designed interface controllers providing 33MHz, 66MHz, 99MHz clock outputs. internal filter which provides excellent jitter characteristics eliminates need external components. LOCK output asserts indicate when phase lock been achieved.
Figure Functional Block Diagram
CLKIN
TEST
LOCK
SENSE
MDSC-00032-01 AUGUST 1998
QUALITY SEMICONDUCTOR, INC.
QS5940 PRELIMINARY Figure Configuration (All Pins View)
QSOP VCCQ TEST GNDN VCCN GNDN VCCN VCCN CLKIN GNDQ SENSE GNDN VCCN LOCK GNDN
Table Frequency Selection
Sense Output CLKIN CLKIN Output
CLKIN CLKIN CLKIN CLKIN CLKIN CLKIN
Table Descriptions
Name CLKIN(1) SENSE(1) 1S(1)
1Q0:2 2S(1) 2Q0:5 LOCK
TEST VCCQ VCCN GNDQ GNDN Total Pins
Functional Description System clock input. Feedback input. Clock output feedback. Sense input from system control bus. When LOW, system clock from 24MHz 33MHz. When HIGH, system clock from 48MHz 66MHz. Select input bank When LOW, divide frequency When HIGH, divide frequency Clock outputs bank Output enable. normal operation. When HIGH, clock outputs 3-stated. Select input bank When LOW, divide frequency When HIGH, divide frequency Clock outputs bank lock indication signal. HIGH indicates positive lock. indicates that locked outputs synchronized inputs. Enables disables PLL. Useful testing purposes. normal operation. Power supply (quiet) Power supply output buffers Ground supply (quiet) Ground output buffers 28-pin QSOP
Note: SENSE control input should ensure operates optimal frequency range from 144MHz 200MHz. When SENSE LOW, running 6xCLKIN. When SENSE HIGH, running 3xCLKIN. Operation with CLKIN input outside specified frequency ranges result invalid out-of-lock outputs.
QUALITY SEMICONDUCTOR, INC.
MDSC-00032-01 AUGUST 1998
QS5940 PRELIMINARY Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 7.0V Input Voltage -0.5V 7.0V Input Diode Current with -20mA Maximum Power Dissipation 70°C 0.80W 85°C 0.66W TSTG Storage Temperature -65° 150°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional reliability type failures.
Table Capacitance
25°C, 1MHz, VOUT QSOP Package Symbol COUT Parameter Input Capacitance Output Capacitance Unit
Note: Limits guaranteed characterization only.
Table Recommended Operating Conditions
Symbol VOUT Description Power Supply Voltage Input Voltage Voltage Applied 3-stated Outputs Ambient Operating Temperature
Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage
Units
Table Electrical Characteristics Over Operating Range
Symbol Parameter Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs 3.0V, 3.0V, -12mA 3.0V, -100uA 3.0V, 12mA 3.0V, 100uA 3.3V, 5.5V Typ(1) -0.7 0.55 -1.2 Unit
Input Leakage Current
Note: Typical values indicate 3.3V 25°C.
MDSC-00032-01 AUGUST 1998
QUALITY SEMICONDUCTOR, INC.
QS5940 PRELIMINARY Table Power Supply Characteristics
Symbol ICCQ ICCD Parameter Quiescent Power Supply Current Dynamic Power Supply Current Test Conditions 3.6, Test VCC, Sense Sense outputs unloaded Unit
Table Switching Characteristics Over Operating Range
Symbol FCLKIN TSK1 TSK2 Parameter Clock input frequency CLKIN input delay(1) Test Conditions SENSE SENSE Measured VCC/2 with test load Measured VCC/2 -700 Unit
TLOCK
Output-to-output skew Same transition, same bank(1) Output-to-output skew Measured VCC/2 Same transition, outputs(1) Cycle-to-cycle jitter(1) fCLKIN=66MHz, 66MHz, 66MHz fCLKIN 66MHz, 66MHz, 33MHz fCLKIN 33MHz, 99MHz, 66MHz Output duty cycle distortion(1,2) Measured VCC/2 CLKIN phase lock Rise time(1) 0.8V 2.0V Fall times 2.0V 0.8V
±100 ±250 ±250
Notes: Limits guaranteed characterization tested. Output signal nominally duty cycle: maximum error period.
QUALITY SEMICONDUCTOR, INC.
MDSC-00032-01 AUGUST 1998
QS5940 PRELIMINARY Figure Test Load Waveforms
2.0V VCC/2 0.8V 3.0V
Output 20pF
2.0V VCC/2 0.8V
1.0ns
1.0ns
Input Test Waveform
Test Load
Output Waveform
Figure Timing Diagram
CLKIN
Gain
Figure F_3dB Closed Loop Frequency
-40dB/decade
Sense 1.1MHz Sense High 2.4MHz
Frequency
MDSC-00032-01 AUGUST 1998
QUALITY SEMICONDUCTOR, INC.
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