System Clock Generator with Power Management Supports Pentium CPU
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SC677
System Clock Generator with Power Management
Supports Pentium CPUs. clocks fixed clocks Super Separate supply pins mixed CPU, IOAPIC, Fixed/PCI clocks 175ps skew among SDRAM clocks. 250ps skew among clocks. Controlled current output buffers clock stop Stop Clock Power Down IOAPIC clocks multiprocessor support. 48-pin SSOP package
FREQUENCY TABLE
Tri-State 66.5 Ref/2 (99.7) Tri-state 33.3 Ref/4 33.41
CONNECTION DIAGRAM
,0,6&
9''5 9'', ,2$3,& ,2$3,& 9''& 9''& 36723 &6723
BLOCK DIAGRAM
VDDR Xout REF[1:3] VDDI IOAPIC[1:2}
;287 3&,,)
VDDC CPU[1:4] VDDP SEL[0:1} CPUSTOP# PCISTOP# PLL1 VDDP PCI[1:7] PCIF
9''3 9''3
VDDF PLL2 48M[1:2]
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
DESCRIPTION
Name TYPE OSC1 Description On-chip reference oscillator input pin. Requires either external parallel resonant crystal (nominally 14.318 MHz) externally generated reference signal O-chip reference oscillator output pin. Drives external parallel resonant crystal when externally generated reference signal used, left unconnected Frequency select input pins. frequency select table page 1.These internal pull-up Clock outputs. frequency table specified page IOAPIC clock multi proscssor support. Fixed frequency 14.31818 Mhz. (2.5 supply VDDI) clocks. frequency select table page
Xout
OSC1
FS(0:2) CPU(1:4) IOAPIC(1:2) PCI(1:7)
VDDC VDDI VDDP
PADI4 BUF1 BUF2 BUF4
PCI_F
VDDP
BUF4
clock that ceases only when (pin ascerted. frequency select table page Ground pins device.
VDDI VDDP VDDF VDDR VDDC REF(1:3) 48M(1:2) PSTOP CSTOP
VDDR VDDF
BUF3 BUF3
Volt power supply pins IOAPIC clock output buffers. Volt power supply pins PCI_F clock output buffers. Volt power supply pins clock output buffers. Volt power supply pins reference clock output buffers. Volt power supply pins clock output buffers. Power supply pins analog circuits core logic Buffered outputs on-chip reference oscillator. Fixed frequency clock outputs. When driven logic level, this will synchronously stop clocks (except PCI_F) logic level. When driven logic level, this will synchronously stop clocks logic level. When this driven logic will enter shutdown mode internal circuitry turned off.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
Outputs Descriptions
Tri-State Test Mode
Hi-Z TCLK/2
PCI, PCIF
Hi-Z TCLK/4
Hi-Z TCLK/2
REF1:3
Hi-Z TCLK
IOAPIC
Hi-Z TCLK
NOTE: TCLK test clock that driven into XTAL_IN input during test mode.
POWER MANAGEMENT FUNCTIONS
(excluding PCI_F) clocks enabled stopped PSTOP CSTOP input pins. clocks stopped state. clocks maintain valid high period transitions from running stopped transitions from stopped running when chip powered down. power (after bring from high state) VCOs will stabilize correct pulse widths within about CPU, clocks transition between running stopped waiting positive edge PCI_F followed negative edge clock interest, after which high levels output either enabled disabled.
CSTOP
PSTOP
CPUCLK RUNNING RUNNING
PCICLK RUNNING RUNNING
OTHER CLKs RUNNING RUNNING RUNNING RUNNING
XTAL VCOs RUNNING RUNNING RUNNING RUNNING
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
POWER MANAGEMENT TIMING
PCICLK_F
PCI_STOP#
PCICLK(0:5)
CPU_STOP#
CPUCLK(0:3)
POWER MANAGEMENT TIMING
Latency Signal
CPU_Stop# PCI_STOP# PWR_DWN#
Signal State
(disabled) (enabled) (disabled) (enabled) (normal operation) (power down)
rising edges free running PCICLK (PCIF)
max.
NOTES: Clock on/off latency defined number rising edges free running PCICLKs between clock disable goes low/high first valid clock comes device. Power latency when PWR_DWN# goes inactive (high) when first valid clocks driven from device.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
MAXIMUM RATINGS
This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Operating Temperature: Maximum Power Supply:
-0.3V 0.3V
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Current Input High Current Output Voltage Output High Voltage Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol Isdd Units 66.6 MHz, 33.3 output time seconds Outputs (see buffer spec) Outputs Using 3.3V Power (see buffer spec) Conditions
VDDP=VDDF =VDDR =3.3V ±5%, VDDC, VDDI 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
SWITCHING CHARACTERISTICS
Characteristic Output Duty Cycle Offset Buffer Skew Buffer Outputs Buffer Skew Buffer Outputs Period Adjacent Cycles Jitter Spectrum Bandwidth from Center Symbol tOFF tSKEW1 tSKEW2 +250 Units Conditions Measured 1.5V Load Measured 1.5V Load Measured 1.5V Load Measured 1.5V
VDDP=VDDF =VDDR =3.3V ±5%, VDDC, VDDI 2.5V ±5%,,
BUFFER CHARACTERISTICS CPUCLK(1:4)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout Vout Vout Load Load
VDDP=VDDF =VDDR =3.3V ±5%, VDDC, VDDI 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
BUFFER CHARACTERISTICS IOAPIC (1:2)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between 2.0V Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout Vout Vout 20pF Load Load
VDDP=VDDF =VDDR =3.3V ±5%, VDDC, VDDI 2.5V ±5%,,
BUFFER CHARACTERISTICS REF(1:3) 48(1:2)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout 3.135 Vout 1.95 Vout Load Load
VDDP=VDDF =VDDR =3.3V ±5%, VDDC, VDDI 2.5V ±5%,,
BUFFER CHARACTERISTICS PCICLK(1:8,F)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout 3.135 Vout 1.95 Vout Load Load
VDDP=VDDF =VDDR =3.3V ±5%, VDDC, VDDI 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571 12/2/97 Page
SC677
System Clock Generator with Power Management
CRYSTAL REFERENCE OSCILLATOR PARAMETERS
Characteristic Frequency Tolerence Symbol Mode Capacitance Bias Voltage Startup time Load Capacitance Effective Series resonant resistance Power Dissipation Shunt Capacitance Load VBIAS 0.3Vdd 12.00 14.31818 Vdd/2 0.7Vdd 16.00 +/-100 Ohms note Units Calibration note Stability +60C) note Aging (first year 25C) note Parallell Resonant Capacitance Xout pins Conditions
0.10
note internal crystal loading gapacitors each ground)
maximum accuracy,the total circuit loading capacitance should equal This loading capacitance effective capacitance across crystal pins includes device capacitance (CP) parallel with circuit traces, clock generator onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, half inch) Load crystal therefore Clock generator internal capacitance Load crystal therefore total parasitic capacitance would therefore 18.0 20.0 pF.(matching
Note recommended manditory that crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
SC677
System Clock Generator with Power Management
PACKAGE DRAWING DIMENSIONS SSOP OUTLINE DIMENSIONS
INCHES SYMBOL
MILLIMETERS 0.110 0.016 0.092 0.0135 0.010 0.630 0.299 2.41 0.20 2.24 0.203 0.127 15.75 7.42 2.59 0.31 2.29 0.254 15.88 7.52 0.635 0.410 0.016 0.040 0.100 10.16 0.25 0.61 2.16 10.31 0.33 0.81 2.36 10.41 0.41 1.02 2.54 2.79 0.41 2.34 0.343 0.254 16.00 7.59
0.095 0.008 0.088 0.008 0.005 0.620 0.292
0.102 0.012 0.090 0.010 0.625 0.296 0.025
0.400 0.10 0.024 0.085
0.406 0.013 0.032 0.093
ORDERING INFORMATION
Part Number IMISC677CYB Note:
Marking:
Package Type SSOP
Production Flow Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below.
Example: SC677CYB Date Code, Flow Commercial, Package SSOP Revision Device Number
IMISC677CYB
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
12/2/97 Page
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