Clock Generator Power Designs with SDRAM Support Preliminary Prod

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Clock Generator Power Designs with SDRAM Support Preliminary Prod

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SC662
Clock Generator Power Designs with SDRAM Support
Preliminary Product Information FREQUENCY TABLE
Sel2
PRODUCT FEATURES
Supports Pentium Cyrix CPU's. host clocks additional SDRAM support. Optional common mixed supply mode VDDRM VDDCPU VDDIO 3.3V VDDRM VDDCPU 3.3V, VDDIO 2.5V VDDRM 3.3V, VDDCPU VDDIO 2.5V 3.3V, VDDRM VDDCPU VDDIO 2.5V
Sel1
Sel0
tristate 66.6 test
tristate a.32 27.5 37.5 33.3 test
skew SDRM* buffers skew buffers Buffer output impedance package minimum board space easy layout
a.32 Asynchronous PCI. Tristate outputs tristate except XOUT.
CONNECTION DIAGRAM
BLOCK DIAGRAM
(1:2) IOAPIC
VDDIO VDDCPU VDDIO REF1 REF2 XOUT SEL2 SEL1 SEL0
XOUT
PLL1
CPU(1:4) SDRM(1:4)
VDDRM
SDRM(5:8) SDRM(9:12) PCI(1:8) 48MHz
VDDRM SDRM8 SDRM7 SDRM6 SDRM5 SDRM4 SDRM3 SDRM2 SDRM1 VDDRM
PLL2
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.1
4/11/97 Page
SC662
Clock Generator Power Designs with SDRAM Support
Preliminary Product Information DESCRIPTION
Xin, Xout These pins form on-chip reference oscillator when connected terminals external parallel resonant crystal (nominally 14.318 MHz). also serve input externally generated reference signal. REF(1:2) Buffered output on-chip reference. Sel0, Sel1, Sel2 Standard frequency select inputs. These inputs have internal pull-ups. 48MHz Frequency output USB. CPU(1:4) skew (<250 clock outputs host frequencies such CPU, Chipset, Cache, etc. CPU1CPU4 voltage level controlled VDDCPU. buffers have switching current 3.3V. SDRM(1:12) skew (<250 clock outputs SDRAM. Voltage level controlled VDDRM. SDRM buffers have switching current 3.3V. IOAPIC Buffered output clock crystal. level controlled VDDIO. This VDDRM 3.3V/2.5V logic level control SDRM(1:12) outputs. Voltage cannot greater than VDD. VDDIO 3.3V/2.5V logic level control IOAPIC output. Voltage cannot greater than VDD. Positive power supply. VDDCPU 3.3V/2.5V logic level control CPU(1:4) outputs. Voltage cannot greater than VDD. Circuit ground. Outputs have 60mA switching current 3.3V. PCI(1:8) skew (<250pS) clock outputs frequencies. 3.3V. This buffer voltage level controlled VDD. these outputs have switching current
buffer switching current 3.3V. Voltage
MAXIMUM RATINGS
This device contains circuitry protect inputs against damage high static voltages electric Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Ambient Temperature: Maximum Power Supply: -0.3V 0.3V field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.1
4/11/97 Page
SC662
Clock Generator Power Designs with SDRAM Support
Preliminary Product Information
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Low, High Current with Pull- Pull-down Output Voltage 12mA Output High Voltage 12mA Tri-State leakage Current Dynamic Supply Current Short Circuit Current Symbol IIL, Units Conditions S0-S2 Inputs Outputs Outputs Outputs 66.6 MHz, 33.3 Load output time seconds
VDDCPU VDDRM 3.3V+5%,
SWITCHING CHARACTERISTICS
Characteristic Output Rise (0.4V 2.0V) Fall (2.0V-0.4V) time Output Duty Cycle Offset Skew Output Skew Outputs Period Cycles, Jitter Absolute, Symbol tTLH, tTHL tOFF tSKEW tSKEP tjab +250 Units Conditions Load outputs Measured 1.5V Load Measured 1.5V Load Measured 1.5V Load Measured 1.5V
VDDCPU VDDRM 3.3V+5%,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.1
4/11/97 Page
SC662
Clock Generator Power Designs with SDRAM Support
Preliminary Product Information LAYOUT SUGGESTION
(10µf) plane island plane
IMISC662
(10µf)
(10µf)
This only layout suggestion best performance lower EMI. designer choose differnent approach such using traces instead islands (dashed areas). Also, designer choose less than three beads. Regardless which layout implemented, Bypass caps C10, (all should always used placed close their pins possible.
NOTES
POWER SUPPLY BYPASS CAPS (O.1UF) MUST POSITIONED CLOSE POSSIBLE PINS EFFECTIVE. BYPASS CAPS MUST LEAKAGE SUCH MULTILAYER CERAMIC MATERIAL WHICH ALSO RESULTS LOWER IMPEDANCE HIGH FREQUENCY. FERRITE BEAD
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.1
4/11/97 Page
SC662
Clock Generator Power Designs with SDRAM Support
Preliminary Product Information PACKAGE DRAWING DIMENSIONS
OUTLINE DIMENSIONS
INCHES SYMBOL .075 .056 .389 .389 .008 .537 .537 .081 .058 .393 .393 0.012 .547 .547 .025 .025 .031 .037 .087 .060 .397 .397 0.016 .557 .557 1.90 1.43 9.90 9.90 0.20 13.65 13.65 MILLIMETERS 2.05 1.48 10.00 10.00 0.30 13.90 13.90 2.20 1.53 10.10 10.10 0.40 14.15 14.15
ORDERING INFORMATION
Part Number IMISC662AAB Note:
Marking:
Package Type
Production Flow Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below.
Example: SC662AAB Date Code,
IMISC662AAB Flow Commercial, Package Revision Device Number
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.1
4/11/97 Page

Clock Generator Power Designs with SDRAM Support Preliminary Prod

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