Clock Generator w/Power Management Mobile Application FREQUENCY T
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SC657
Clock Generator w/Power Management Mobile Application
FREQUENCY TABLE
Supports clock requirements Mobile Pentium Processor Host clocks Separate supply pins mixed (3.3/2.5V) voltage application. <175ps skew among clocks. 250ps skew among clocks. Power Management Function. 28-pin SSOP package minimum board space. Power management PCI, entire device shutdown logic functions
SEL100/66#
66.4 99.8 Tri-State Ref/2
33.3 33.2 Tri-State Ref/4
CONNECTION DIAGRAM
BLOCK DIAGRAM
XOUT VDDR
VDDC CPU_STOP# PCI_STOP# SEL100/66#
CPU(0:1)
VDDP
PCI(1:5) PCI_F
XOUT PCI_F PCI1 VDDP PCI2 PCI3 VDDP PCI4 PCI5
VDDR VDDC CPU0 CPU1 PCI_STOP# CPU_STOP# SEL100/66#
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
Rev.
4/20/98 Page
SC657
Clock Generator w/Power Management Mobile Application
DESCRIPTION
Name TYPE OSC1 Description On-chip reference oscillator input pin. Requires either external parallel resonant crystal (nominally 14.318 MHz) externally generated reference signal On-chip reference oscillator output pin. Drives external parallel resonant crystal. When externally generated reference signal used, left unconnected Frequency select input pins. frequency select table page 1.This internal pull-up resistor. Test mode select input. When logic level enables device test mode. table page Clock outputs. frequency table specified page Free running clock. When PCI_STOP# this clock does stop. clocks. frequency select table page Ground pins device.
XOUT
OSC1
SEL100/66# (0:1) PCI_F PCI(1:5)
VDDC VDDP VDDP
PADI4 BUF1 BUF4 BUF4
VDDP VDDC VDDR PCI_STOP# CPU_STOP
VDDR
BUF3
Volt power supply pins PCI(1:5) PCI_F clock output buffers. Volt power supply CPU(0:1) outputs. Volt power supply pins reference clock output buffers crystal circuit. Buffered outputs on-chip reference oscillator. When driven logic level, this will synchronously stop clocks (except PCI_F) logic level. When driven logic level, this will synchronously stop clocks logic level. volt power supply core logic. Power down. Removes power from internal logic clock buffers when driven low.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
Rev.
4/20/98 Page
SC657
Clock Generator w/Power Management Mobile Application
Outputs Descriptions
Tri-State Test Mode
Hi-Z TCLK/2
PCI, PCI_F
Hi-Z TCLK/4
Hi-Z TCLK
NOTE: TCLK test clock that driven into XTAL_IN input during test mode.
POWER MANAGEMENT FUNCTIONS
(excluding PCI_F) clocks enabled stopped PCI_STOP CPU_STOP input pins. clocks stopped state. clocks maintain valid high period transitions from running stopped transitions from stopped running when chip powered down. power (after bring from high state) VCOs will stabilize correct pulse widths within about CPU, clocks transition between running stopped waiting positive edge PCI_F followed negative edge clock interest, after which high levels output either enabled disabled.
CPU_STOP# PCI_STOP# RUNNING RUNNING RUNNING RUNNING OTHER CLKs RUNNING RUNNING RUNNING RUNNING XTAL VCOs RUNNING RUNNING RUNNING RUNNING
POWER MANAGEMENT TIMING
PCI_F
PCI_STOP#
PCI(1:5)
CPU_STOP#
CPU(0:1)
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
Rev.
4/20/98 Page
SC657
Clock Generator w/Power Management Mobile Application
POWER MANAGEMENT TIMING
Signal
CPU_STOP# PCI_STOP#
Signal State
(disabled) (enabled) (disabled) (enabled)
Latency rising edges free running (PCI_F)
NOTES: Clock on/off latency defined number rising edges free running PCIs between clock disable goes low/high first valid clock comes device.
MAXIMUM RATINGS
This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, should constrained range: VSS<(Vin)<VDD Unused inputs must always tied appropriate logic voltage level (either VDD).
Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Operating Temperature: Maximum Power Supply:
-0.3V 0.3V
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Current Input High Current Output Voltage Output High Voltage Tri-State leakage Current Dynamic Supply Current Static Supply Current Short Circuit Current Symbol Isdd Units Conditions
Outputs (see buffer spec) Outputs Using 3.3V Power (see buffer spec) 66.6 MHz, 33.3 output time seconds
VDDP =VDDR =3.3V ±5%, VDDC 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
Rev.
4/20/98 Page
SC657
Clock Generator w/Power Management Mobile Application
SWITCHING CHARACTERISTICS
Characteristic Output Duty Cycle Offset Buffer Skew Buffer Skew Period Adjacent Cycles Jitter Spectrum Bandwidth from Center Symbol tOFF tSKEW tSKEW +250 Units Conditions Measured 1.5V Load Measured 1.5V Load Measured 1.5V Load Measured 1.5V
VDDP =VDDR =3.3V ±5%, VDDC 2.5V ±5%,,
TB41 BUFFER CHARACTERISTICS CPU(0:1)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout Vout Vout Load Load
VDDP =VDDR =3.3V ±5%, VDDC 2.5V ±5%,,
TB4L1 BUFFER CHARACTERISTICS
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout 3.135 Vout 1.95 Vout Load Load
VDDP =VDDR =3.3V ±5%, VDDC 2.5V ±5%,,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571 Rev. 4/20/98 Page
SC657
Clock Generator w/Power Management Mobile Application
TB4L1 BUFFER CHARACTERISTICS PCI_F, PCI(1:5)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise Time Between Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax Units Conditions Vout Vout 3.135 Vout 1.95 Vout Load Load
VDDP =VDDR =3.3V ±5%, VDDC 2.5V ±5%,,
CRYSTAL REFERENCE OSCILLATOR PARAMETERS
Characteristic Frequency Tolerence Symbol Mode Capacitance Bias Voltage Startup time Load Capacitance Effective Series resonant resistance Power Dissipation Shunt Capacitance Load VBIAS 0.3Vdd 12.00 14.31818 Vdd/2 0.7Vdd 16.00 +/-100 Ohms note Units Calibration note Stability +60C) note Aging (first year 25C) note Parallell Resonant Capacitance Xout pins Conditions
0.10
note internal crystal loading gapacitors each ground)
maximum accuracy,the total circuit loading capacitance should equal This loading capacitance effective capacitance across crystal pins includes device capacitance (CP) parallel with circuit traces, clock generator onboard discrete load capacitors. Budgeting Calculations Typical trace capacitance, half inch) Load crystal therefore Clock generator internal capacitance Load crystal therefore 18.0 total parasitic capacitance would therefore 20.0 pF(matching Note recommended manditory that crystal meets these specifications.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
Rev.
4/20/98 Page
SC657
Clock Generator w/Power Management Mobile Application
PACKAGE DRAWING DIMENSIONS
SSOP OUTLINE DIMENSIONS
SYMBOL 0.301` 0.022 0.205 0.209 0.0256 0.307 0.030 0.311 0.037 7.65 0.55 0.212 5.20 5.30 0.65 7.80 0.75 7.90 0.95 5.38
INCHES 0.068 0.002 0.066 0.010 0.005 0.397 0.073 0.005 0.068 0.012 0.006 0.402 0.078 0.008 0.070 0.015 0.009 0.407 1.73 0.05 1.68 0.25 0.13 10.07
MILLIMETERS 1.86 0.13 1.73 0.30 0.15 10.20 1.99 0.21 1.78 0.38 0.22 10.33
ORDERING INFORMATION
Part Number IMISC657GYB Note: Package Type SSOP Production Flow Commercial,
ordering part number formed combination device number, device revision, package style, screening shown below. SC657GYB Date Code,
Marking: Example:
IMISC657GYB Flow Commercial, Package SSOP Revision Device Number
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035 TEL: 408-263-6300 ext. 408-263-6571
Rev.
4/20/98 Page
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