HPLL-8001 Operating Current Consumption typ.) High Input Sensitiv

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HPLL-8001 Operating Current Consumption typ.) High Input Sensitiv

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Frequency Synthesizer Technical Data
HPLL-8001
Operating Current Consumption typ.) High Input Sensitivity, High Input Frequencies MHz) Synchronous Programming Counters (n-, n/a-, r-counters) Switchable Modulus Trigger Edge Large Dividing Ratios Small Channel Spacing, counter 127, counter 16,380, counter 65,535 Serial Control 3-wire Bus: Data, Clock (<10 MHz), Enable Switchable Polarity Programmable Phase Detector Current Programmable Outputs Digital Phase Detector Output Signals (e.g. External Charge Pump) DRFI, DVFI Outputs (e.g. Prescaler Standby) Lock Detect Output with Gated Anti-backlash Pulse (quasi digital lock detect)
Plastic SOP-14
Description
HPLL-8001 phase-locked loop (PLL) frequency synthesizer intended frequency generation loop with external dual modulus prescaler VCO. frequency divided dual modulus prescaler, which then internal counters. reference frequency internal counter define channel spacing. Both frequencies compared phase detector which drives charge pump. lock detect provided monitor lock state loop. blocks programmed serial 3-wire interface.
Configuration
REFI
HPLL 8001 YYWW
DATA
AVDD AVSS VCOI
Functional Block Diagram
DATA CLOCK ENABLE Serial Control Logic counter counter VCOI counter Analog Control Logic AVDD AVSS DRFI Phase Detector Modulus Control DVFI Charge Pump Lock Detect
REFI
Applications
Handsets Base Stations PCS/PCN DECT Wireless
HPLL-8001 Absolute Maximum Ratings[1]
Symbol TSTG Parameter Supply Voltage Power Dissipation Input Power Junction Temperature Storage Temperature Units Absolute Maximum Thermal Resistance[2]: 150°C/W
Notes: Permanent damage occur these limits exceeded. Tcase 25°C. Derate mW/°C Tcase 90°C.
Recommended operating range +85°C.
HPLL-8001 Summary Characterization Information
Standard test conditions apply unless otherwise noted. Current Consumption Symbol Parameters Test Conditions Current Consumption Standby Units Typ. 0.06
Note: MHz, mVrms, MHz, mVrms, 0.250 IREF
Input Frequency (pin Reference Input Frequency (pin
Symbol FREFI FVCOI Parameters Test Conditions Reference Frequency Range Oscillator Frequency Range[2] Dual Mode VREFI mVrms VREFI mVrms VVCOI mVrms VVCOI mVrms VVCOI mVrms VVCOI mVrms VVCOI mVrms VVCOI mVrms Units Typ.
Single Mode
Single Mode
Note: Minimum Slew Rate V/ms, Input Capacitance Input Current Input Current high
Inputs (pin Data (pin (pin
Symbol FCLK TCLW TCLES TECLS TENW Parameters Test Conditions Voltage Input Voltage Input High Clock Frequency Rise Fall Time Pulse Width (high) Data Setup Time CLK-Enable Setup Time Enable-CLK Setup Time Pulse Width (high) Propagation Delay Time (Enable Port
Note: These values valid under following conditions:
Units
0.7VDD
0.3VDD
DATA
TCLES
TECLS
Output Modulus Control (pin
Symbol Parameters Test Conditions Voltage Output High Voltage Output Rise Fall Time TPHL Propagation Delay from high high (VCOI MOD) Units
TPLH TPLH
pos-edge
TPLH
TPLH
neg-edge
Output Phase Detector (pin
Symbol (VDD Parameters Test Conditions Standby (VDD Standby Units Typ. 0.15 0.21 0.31 0.44 0.63 0.89 1.26 1.69 0.14 0.20 0.29 0.40 0.58 0.79 1.06 1.26
REFI VCOI DRFI DVFI pos. neg.
+lprog tri-st. -lprog +lprog tri-st. -lprog high resist. (pos.) (neg.) pos. edge neg. edge
PHIR
(pos.) (neg.)
PHIV
Input-Output Programmable Input-Output (pin
Symbol VREF Parameters Test Conditions Voltage Output High Voltage Output Fall Time Rise Time MF01, MF02, MF01, MF02, MF01, MF02, MF01, MF02, Reference Voltage, Iref Units
Output Lock Detect (pin
Symbol Parameters Test Conditions Voltage Output Fall Time Units
INPUT
TPLH
TPLH
OUTPUT
HPLL-8001 Description Table
Mnemonic
REFI
Description
Reference Frequency
Typical Signal
High sensitivity preamplifier input r-counter. input AC-coupled small input signals DC-coupled large input signals. Enable line serial interface with internal pull-up resistor. When EN=H, input signal DATA internally disabled. When EN=L, received data transferred latches positive edge signal. Serial DATA input with internal pull-up resistor. last bits before EN-signal define destination address. Clock line with internal pull-up resistor. serial DATA read into internal shift register positive edge (see pulse diagram serial data control).
Ground digital logic 3-wire interface: Enable
DATA
3-wire interface: Data 3-wire interface: Clock
Positive supply voltage digital logic Modulus Control external dual modulus prescaler. modulus output beginning cycle. When a-counter reached value, switches high. When ncounter reached value, switches cycle starts again. When prescaler counter factor MOD=H, MOD=L), overall scaling factor NP+A. value a-counter must smaller than that n-counter. trigger edge modulus signal input signal selected (see programming tables according needs prescaler. single modulus operation standby operation, output low. High sensitivity preamplifier input n-counter. input AC-coupled small input signals DC-coupled large input signals. Pins AVDD also pins AVSS must have same power supply voltage. Tristate charge pump output. level charge pump output current programmed using digital interface. frequency FV<FR lagging: source active frequency FV>FR leading: source active frequency FV=FR locked: tristate standby mode: tristate polarity output signals phase detector programmed.
VCOI
frequency
AVSS
Ground analog logic Phase detector
AVDD
Positive supply voltage analog logic
HPLL-8001 Description Table, continued
Mnemonic
Description
Programmable output Programmable
Typical Signal
Multifunction Output signals PROBIT (FRN, inverted signals VN). output signals FVN, input signal IREF signals digital output signals phase frequency detector with external active current sources. signals scaled down signals reference frequency VCO-frequencies. programmed PROBIT assigned output internal charge pump mode. standby mode does affect this function. internal charge pump mode input signal IREF determines value PD-output current. Unipolar output phase detector form pulsewidth modulated signal. LD-pulse width corresponds phase difference. locked state LD-signal H-level. standby mode output resistive.
Lock detect
Programmable Reference Divider Counter Register)
Note: counter value. first which transferred HPLL-8001.
Programmable Dividers Counter Registers)
Dual Mode
Single Mode
Note: counter value. counter value. first which transferred HPLL-8001.
Status Registers
first which transferred HPLL-8001. Counter loading asynchronous counter load synchronous counter load
Polarity negative positive positive means increasing frequency with increasing voltage
Modes Test Modes External Charge Pump, Mode External Charge Pump, Mode Internal Charge Pump mode
PROBIT
IREF
Standby Standby Modes Standby mode functions powered down Standby mode Counters, charge pump, outputs off. Only preamplifiers stay active Normal operation: functions active
Anti Backlash Pulse Width Typical Unit
B10: Single/Dual Mode Preamplifier Select Modes
VCOI input: single mode VCOI input: single mode VCOI input: dual mode, VCOI trigger edge VCOI input: dual mode, VCOI trigger edge
B11: Output PROBIT
B12, B13, B14: Standby Standby Charge pump current Typ. Units 0.15 0.21 0.31 0.44 0.63 0.89 1.26 1.69 0.14 0.20 0.29 0.40 0.58 0.79 1.06 1.26
Reduced Status Register
first which transferred HPLL-8001.
Functional Description
Frequency Divider division ratio calculated follows: FVCO FREF where, FVCO: Output frequency external FREF: Reference oscillator frequency divide ratio counter 16380 divide ratio counter divide ratio counter 65535 divide ratio external dual modulus prescaler Phase Detector Charge Pump phase detector digital, edge-sensitive comparator with DOWN outputs. Both outputs monitored outputs PO2. phase detector drives charge pump, which switch with tristate state. output current programmed steps between 0.15 1.69 (VDD with reference current VCOI REFI, charge pump delivers positive current external loop filter. VCOI REFI, charge pump sinks negative current from external loop filter. charge pump output inverted software. Anti-backlash pulses generated extend very short phase difference between VCOI REFI.
Programming HPLL-8001 programmed through 3-wire interface. Four different words sent over this interface program internal registers. four words consists 2-bit address variable data portion. When data transferred. loaded into internal registers rising edge last bits which transferred, form address bits. When input signals, DATA, internally disabled. Status registers contains status information. reduced Status register reduced version status register. counter register counter register contain applicable counter values. programming device must start with loading status register. counters loaded synchronously asynchronously. synchronous loading selected, counters loaded when they reach value zero. result, phase difference between divided VCOI REFI signal remains same. synchronous loading following order programming must followed: programming synchronous loading using status register
programming counter programming counters rising edge enables synchronous loading counters their zero value. Standby HPLL-8001 standby modes. standby mode whole device powered down with exception serial interface. standby mode serial interface input amplifiers active. other parts powered down.
Part Number Ordering Information
Part Number HPLL-8001-BLK HPLL-8001-TR1 Devices 1000 Container Tube Reel
Package Dimensions
JEDEC Standard SOP-14
SYMBOL DIMENSIONS MIN. MAX. 1.35 (0.053) 2.01 (0.079) 0.080 (0.003) 0.300 (0.012) 0.330 (0.013) 0.510 (0.020) 8.56 (0.337) 8.89 (0.350) 3.81 (0.150) 4.09 (0.161) 1.27 (0.500) 5.79 (0.151) 6.40 (0.252) 0.300 (0.012) 1.27 (0.050)
Device Orientation
REEL
HPLL 8001 YYWW
CARRIER TAPE USER FEED DIRECTION COVER TAPE
Meets JEDEC outline dimensions. Dimensions millimeters (inches). Tolerances: ±.01, .XXX ±.002
Tape Dimensions Product Orientation
0.30 0.05 +0.1/-0.0 DIA. 1.75
0.30 MAX.
HPLL 8001 YYWW
16.0
RADIUS
DIMENSIONS SHOWN MILLIMETERS
www.hp.com/go/rf technical assistance location your nearest Hewlett-Packard sales office, distributor representative call: Americas/Canada: 1-800-235-0312 408-654-8675 East/Australasia: Call your local sales office. Japan: 3335-8152 Europe: Call your local sales office. Data subject change. Copyright 1998 Hewlett-Packard Printed U.S.A. 5966-1495E (1/98)

HPLL-8001 Operating Current Consumption typ.) High Input Sensitiv

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