Clock Distribution Buffer Banks Mobile SDRAM PRODUCT DESCRIPTION

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Clock Distribution Buffer Banks Mobile SDRAM PRODUCT DESCRIPTION

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CB664
Clock Distribution Buffer Banks Mobile SDRAM
PRODUCT DESCRIPTION
device high fanout system clock buffer. primary application distribute clocks needed support wide range applications such SDRAM clocks. This device provides Skew distribution clock heavily loaded. important application this component where long traces used transport clocks from their generating devices their loads. creation degradation waveform rise fall times greatly reduced running single reference clock trace this device then using regenerate clock that drives shorter traces. When using these devices therefore minimized board real estate saved.
output buffer high clock fanout applications Output individually disabled with VDD=3.3 volts Ouput frequency range 250ps skew between output clocks. 16-pin SSOP TSSOP package
BLOCK DIAGRAM
Control SDATA SCLK SDR[0,1]
SDR0 SDR1 CLKIN SDR2 SDATA SDR6 SDR5 SDR4 SDR3 SCLK
REFIN
SDR2
SDR[3,4]
SDR[5,6]
DESCRIPTION
2,3,6,11,12,15,16 10,14 Name CLKIN SDR(0:6) SDATA SCLK TYPE BUF1 Description This connected input reference clock. This clock must range 10.0 100.0 Mhz. skew output clock serial data 2-wire control interface. internal pull-up resistor. Serial clock 2-wire control interface. internal pull-up resistor. COMMON Ground. Power output clock buffers core logic.
MAXIMUM RATINGS
Voltage Relative VSS: Voltage Relative VDD: Storage Temperature: Operating Temperature: Maximum Power Supply: -0.3V 0.3V This device contains circuitry protect inputs against damage high static voltages electric field; however, precautions should taken avoid application voltage higher than maximum rated voltages this circuit. proper operation, Vout should constrained range: VSS<(Vin Vout)<VDD
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.5
5/6/1999 Page
CB664
Clock Distribution Buffer Banks Mobile SDRAM
2-WIRE CONTROL INTERFACE
2-wire control interface implements write only slave interface. device cannot read back. Sub-addressing supported, thus preceding bytes must sent order change control bytes. 2-wire control interface allows each clock output individually enabled disabled. During normal data transfer, SDATA signal only changes when SDCLK signal low, stable when SDCLK high. There exceptions this. high transition SDATA while SDCLK high used indicate start data transfer cycle. high transition SDATA while SDCLK high indicates data transfer cycle. Data always sent complete 8-bit bytes, after which acknowledge generated. first byte transfer cycle 7-bit address with Read/Write LSB. Data transferred first. device will respond writes bytes (max) data address generating acknowledge (low) signal SDATA wire following reception each byte. device will respond other control interface conditions. Previously control registers retained.
SERIAL CONTROL REGISTERS
NOTE: Pin# column lists affected number where applicable. @Pup column gives state true power Bytes values shown only true power when PWR_DWN# activated. Following acknowledge Address Byte (D2), additional bytes must sent: "Command Code byte, "Byte Count" byte. Although data (bits) these bytes considered "don't care", they must sent will acknowledged. After Command Code Count bytes have been acknowledged, below desrcibed sequence (Byte Byte Byte2, will valid acknowledged. Byte enable, Stopped)
@Pup Pin# Description SDR2 (enable stopped Reserved Reserved Reserved SDR1 (enable stopped SDR0 (enable stopped Reserved Reserved
Byte enable, Stopped)
@Pup Pin# Description SDR6 (enable stopped SDR5 (enable stopped Reserved Reserved SDR4 (enable stopped SDR3 (enable stopped Reserved Reserved
Application note AN664-01 further reducing power consumption with I2C.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.5
5/6/1999 Page
CB664
Clock Distribution Buffer Banks Mobile SDRAM
ELECTRICAL CHARACTERISTICS
Characteristic Input Voltage Input High Voltage Input Current Input High Current Tri-State leakage Current Dynamic Supply Current (all outputs loaded with 30pF) Static Supply Current Short Circuit Current Input Rise Time Symbol Idd66 Idd100 Isdd Units Input frequency Input frequency outputs disabled input clock output time seconds volts Conditions
VDD1 thru VDD6 =3.3V ±5%,
SWITCHING CHARACTERISTICS
Characteristic Output Duty Cycle Buffer out/out Skew Buffer Outputs Buffer input output Skew Jitter Cycle Cycle* Jitter Absolute (Peak Peak)* Symbol tSKEW tSKEW TJCC TJabs Units loading loading Conditions Measured 1.5V (50/50 Load Measured 1.5V
VDD1 thru VDD6 3.3V ±5%,
*this jitter additive input clock's jitter.
BUFFER CHARACTERISTICS (ALL CLOCK OUTPUTS)
Characteristic Pull-Up Current Pull-Up Current Pull-Down Current Pull-Down Current Rise/Fall Time Between Rise/Fall Time Between Symbol IOHmin IOHmax IOLmin IOLmax TRFmin TRFmax 1.33 1.33 Units Conditions Vout Vout Vout Vout Load Load
VDD1 thru VDD6 =3.3V ±5%,
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.5
5/6/1999 Page
CB664
Clock Distribution Buffer Banks Mobile SDRAM
LAYOUT SUGGESTION
Plane Plane Void (cut) power plane
This only layout recommendation best performance lower EMI. designer choose different approach (all should always used placed close their pins physically possible. Ferrite Bead resistor needed reduce conducted from device into systems power circuitry.
PACKAGE DRAWING DIMENSIONS SSOP OUTLINE DIMENSIONS
SYMBOL
INCHES 0.068 0.002 0.066 0.010 0.005 0.239 0.205 0.301 0.022 0.073 0.005 0.068 0.012 0.006 0.244 0.209 0.0256 0.307 0.030 0.311 0.037 7.65 0.55 0.078 0.008 0.070 0.015 0.009 0.249 0.212 1.73 0.05 1.68 0.25 0.13 6.07 5.20
MILLIMETERS 1.86 0.13 1.73 0.30 0.15 6.20 5.30 7.80 0.75 1.99 0.21 1.78 0.38 0.22 6.33 5.38 7.90 0.95
0.65
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.5
5/6/1999 Page
CB664
Clock Distribution Buffer Banks Mobile SDRAM
PACKAGE DRAWING DIMENSIONS (Cont.)
R0.1
TSSOP DIMENSIONS
INCHES
MILLIMETERS 0.0433 0.0059 0.0374 0.0275 0.0433 0.0108 0.0096 0.0068 0.0057 0.05 0.85 0.50 0.90 0.09 0.195 0.195 0.105 0.105 0.10 0.90 0.60 1.00 0.22 0.125 0.65 0.1988 0.2559 0.1752 4.95 4.35 0.20 5.05 4.45 1.10 0.15 0.95 0.75 1.10 0.275 0.245 0.175 0.145
SYMBOL
0.0019 0.0346 0.0196 0.0354 0.0035 0.0076 0.0076 0.0041 0.0041
0.0039 0.0354 0.0236 0.0393 0.0086 0.0049 0.026
1.20
1.50 SURFACES ROUGHNESS: 27n(RZ)
[10°
R0.15
0.07
R0.15
0.05 MAX.
0.05 MAX.
0.1948 0.2480 0.1712 0.0078
0.1968 0.2519 0.1732
0.25
DETAIL
DETAIL
ORDERING INFORMATION
Part Number IMICB664EYB IMICB664ETB Note: Package Type SSOP TSSOP Production Flow Commercial, Commercial,
ordering part number formed combination device number, device revision, package style, screening.
Purchase components International Microcircuits, Inc. sublicensed Associated Companies conveys license under Phillips Patent Rights these components system, provided that system conforms Standard Specification defined Phillips.
INTERNATIONAL MICROCIRCUITS, INC. COCHES MILPITAS, 95035. TEL: 408-263-6300. 408-263-6571
Rev.1.5
5/6/1999 Page

Clock Distribution Buffer Banks Mobile SDRAM PRODUCT DESCRIPTION

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