2M-BIT [256Kx8/128x16] CMOS EPROM 128K organization(MX27C2048, JE
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MX27C2100/27C2048
2M-BIT [256Kx8/128x16] CMOS EPROM
128K organization(MX27C2048, JEDEC
out) 256K 128K organization(MX27C2100, compatible) +12.5V programming voltage Fast access time: 55/70/90/120/150 Totally static operation
Completely compatible Operating current: 40mA Standby current: 100uA Package type: plastic PLCC(MX27C2048) TSOP(I)(MX27C2048)
GENERAL DESCRIPTION
MX27C2100/2048 only, 2M-bit, Time Programmable Read Only Memory. organized 128K words bits word(MX27C2048), 256K 128K 16(MX27C2100), operates from single volt supply, static standby mode, features fast single address location programming. programming signals levels, requiring single pulse. programming outside from system, existing EPROM programmers used. MX27C2100/2048 supports intelligent fast programming algorithm which result programming times less than minute. This EPROM packaged industry standard dual-in-line packages, lead PLCC, lead TSOP(I) packages.
CONFIGURATIONS
PDIP(MX27C2048)
PLCC(MX27C2048)
MX27C2048
MX27C2048
40-TSOP(I)10x14mm (MX27C2048)
BLOCK DIAGRAM (MX27C2048)
CONTROL LOGIC OUTPUT BUFFERS Q0~Q15
MX27C2048
A0~A16 ADDRESS INPUTS
Y-DECODER
X-DECODER
Y-SELECT
CELL MAXTRIX
P/N: PM0158
REV. 4.3, AUG. 2000
MX27C2100/27C2048
CONFIGURATIONS
PDIP(MX27C2100)
BYTE/VPP Q15/A-1
BLOCK DIAGRAM (MX27C2100)
BYTE/VPP
CONTROL LOGIC
OUTPUT BUFFERS
Q0~Q14 Q15/A-1
A0~A16 ADDRESS INPUTS
Y-DECODER
MX27C2100
Y-SELECT
X-DECODER
CELL MAXTRIX
DESCRIPTION(MX27C2100)
SYMBOL A0~A16 Q0~Q14 BYTE/VPP NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Word/Byte Selection /Program Supply Voltage Q15/A-1 Q15(Word mode)/LSB addr. (Byte mode) Power Supply (+5V) Ground
DESCRIPTION(MX27C2048)
SYMBOL A0~A16 Q0~Q15 NAME Address Input Data Input/Output Chip Enable Input Output Enable Input Program Enable Input Program Supply Voltage Power Supply (+5V) Ground
TRUTH TABLE BYTE FUNCTION(MX27C2100)
BYTE MODE(BYTE GND)
Q15/A-1 input MODE selected selected Selected Q0-Q7 High High DOUT SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
WORD MODE(BYTE VCC)
NOTE
P/N: PM0158 REV. 4.3, AUG. 2001
Q15/A-1 High High DOUT
MODE selected selected Selected
Q0-Q14 High High DOUT
SUPPLY CURRENT Standby(ICC2) Operating(ICC1) Operating(ICC1)
MX27C2100/27C2048
FUNCTIONAL DESCRIPTION
PROGRAMMING MX27C2100/2048 When MX27C2100/2048 delivered, erased, chip bits "ONE", HIGH state. "ZEROs" loaded into MX27C2100/2048 through procedure programming. programming, data programmed applied with bits parallel data pins. must applied simultaneously before VPP, removed simultaneously after VPP. When programming MXIC EPROM, 0.1uF capacitor required across ground suppress spurious voltage transients which damage device. AUTO IDENTIFY MODE auto identify mode allows reading binary code from EPROM that will identify manufacturer device type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional 25°C ambient temperature range that required when programming MX27C2100/2048. activate this mode, programming equipment must force 12.0 address line device. identifier bytes then sequenced from device outputs toggling address line from VIH. other address lines must held during auto identify mode. Byte VIL) represents manufacturer code, byte VIH), device identifier code. MX27C2100/2048, these identifier bytes given Mode Select Table. identifiers manufacturer device codes will possess parity, with (Q15) defined parity bit. VIL(for MX27C2048), VIL, VIH(for MX27C2100) programming voltage.
FAST PROGRAMMING device fast programming mode when programming voltage 12.75V applied, with 6.25 VIL(or VIH) (Algorithm shown Figure programming achieved applying single level 100us pulse input after addresses data line stable. data verified, additional pulse applied maximum pulses. This process repeated while sequencing through each address device. When programming mode completed, data address verified 10%.
READ MODE MX27C2100/2048 control functions, both which must logically satisfied order obtain data outputs. Chip Enable (CE) power control should used device selection. Output Enable (OE) output control should used gate data output pins, independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available outputs after falling edge OE's, assuming that been addresses have been stable least tACC
PROGRAM INHIBIT MODE Programming multiple MX27C2100/2048's parallel with different data also easily accomplished using Program Inhibit Mode. Except like inputs parallel MX27C2100/2048 common. low-level program pulse applied MX27C2100/2048 input with 12.5 will program MX27C2100/2048. high-level input inhibits other MX27C2100/2048s from being programmed.
WORD-WIDE MODE PROGRAM VERIFY MODE Verification should performed programmed bits determine that they were correctly programmed. verification should performed with With BYTE/VPP 0.2V outputs Q0-7 present data Q0-7 outputs Q8-15 present data Q8-15, after appropriately enabled.
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
BYTE-WIDE MODE With BYTE/VPP 0.2V, outputs Q8-15 tristated. Q15/A-1 VIH, outputs Q0-7 present data bits Q8-15. Q15/A-1 VIL, outputs Q0-7 present data bits Q0-7. location capacitor should close where power supply connected array.
STANDBY MODE MX27C2100/2048 CMOS standby mode which reduces maximum current placed CMOS standby when MX27C2100/2048 also TTL-standby mode which reduces maximum current placed TTL-standby when VIH. When standby mode, outputs high-impedance state, independent input.
TWO-LINE OUTPUT CONTROL FUNCTION accommodate multiple memory connections, twoline control function provided allow for: memory power dissipation, Assurance that output contention will occur. recommended that decoded used primary device-selecting function, while made common connection devices array connected READ line from system control bus. This assures that deselected memory devices their low-power standby mode that output pins only active when data desired from particular memory device.
SYSTEM CONSIDERATIONS During switch between active standby conditions, transient current peaks produced rising falling edges Chip Enable. magnitude these transient current peaks dependent output capacitance loading device. minimum, ceramic capacitor (high frequency, inherent inductance) should used each device between minimize transient effects. addition, overcome voltage drop caused inductive effects printed circuit board traces EPROM arrays, bulk electrolytic capacitor should used between each eight devices.
P/N: PM0158 REV. 4.3, AUG. 2001
MX27C2100/27C2048
MODE SELECT TABLE (MX27C2048)
PINS MODE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) VCC±0.3V OUTPUTS DOUT High High High DOUT High 00C2H 0122H
NOTES: 12.0 Either
VIL(For auto select) Programming Characteristics voltage during programming.
MODE SELECT TABLE (MX27C2100)
BYTE/ MODE Read (Word) Read (Upper Byte) Read (Lower Byte) Output Disable Standby Program Program Verify Program Inhibit Manufacturer Code(3) Device Code(3) Q15/A-1 High High High VPP(5) Q8-14 Q8-14 High High High High Q8-14 Q8-14 High Q0-7 Q0-7 Q8-15 Q0-7 High High Q0-7 Q0-7 High
NOTES: 12.0V 0.5V Either VIL. VIL(For auto select)
Programming Characteristics voltages. BYTE/VPP intended operation under Voltage conditions only.
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
FIGURE FAST PROGRAMMING FLOW CHART
START
ADDRESS FIRST LOCATION
6.25V 12.75V
PROGRAM 50us PULSE
INTERACTIVE SECTION
INCREMENT
FAIL
VERIFY BYTE
PASS INCREMENT ADDRESS LAST ADDRESS FAIL
5.25V
VERIFY SECTION
VERIFY BYTES
FAIL
DEVICE FAILED
PASS DEVICE PASSED
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
SWITCHING TEST CIRCUITS
DEVICE UNDER TEST
1.8K
6.2K
DIODES IN3064 EQUIVALENT
including capacitance (30pF MX27C2100/2048-70 MX27C2048-55)
SWITCHING TEST WAVEFORMS
2.0V
driving levels
2.0V TEST POINTS 0.8V OUTPUT
0.8V INPUT
TESTING: driving levels 3.0V/0V. Input pulse rise fall times 10ns.
driving levels
1.5V
TEST POINTS OUTPUT
1.5V
INPUT
TESTING: driving levels 3.0V/0V commercial grade. Input pulse rise fall times 10ns. MX27C2100/2048-70 MX27C2048-55.
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
ABSOLUTE MAXIMUM RATINGS
RATING Ambient Operating Temperature Storage Temperature Applied Input Voltage Applied Output Voltage Ground Potential VALUE 70oC -65oC 125oC -0.5V 7.0V -0.5V 0.5V -0.5V 7.0V -0.5V 13.5V NOTICE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended period affect reliability. NOTICE: Specifications contained within following tables subject change.
DC/AC Operating Conditions Read Operation
MX27C2048 Operating Temperature Power Supply Commercial 70°C MX27C2100/2048 70°C 70°C
CHARACTERISTICS
SYMBOL ICC3 ICC2 ICC1 PARAMETER Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Output Leakage Current Power-Down Current Standby Current Active Current Supply Current Read -0.3 MIN. MAX. UNIT 5.5V VOUT 5.5V 0.3V VIL, f=5MHz, Iout VIL, 5.5V CONDITIONS -0.4mA 2.1mA
CAPACITANCE 25oC, (Sampled only)
SYMBOL COUT CVPP PARAMETER Input Capacitance Output Capacitance Capacitance TYP. MAX. UNIT CONDITIONS VOUT
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
CHARACTERISTICS
2100/2048-55 SYMBOL tACC PARAMETER Address Output Delay Chip Enable Output Delay Output Enable Output Delay High Output Float, High Output Float Output Hold from Address, which ever occurred first MIN. MAX. 2100/2048-70 MIN. MAX. 2100/2048-90 MIN. MAX. UNIT CONDITIONS
CHARACTERISTICS
2100/2048-12 SYMBOL PARAMETER tACC Address Output Delay Chip Enable Output Delay Output Enable Output Delay High Output Float, High Output Float Output Hold from Address, which ever occurred first MIN. MAX. 2100/2048-15 MIN. MAX. UNIT CONDITIONS
CHARACTERISTICS
27C2100-70 SYMBOL PARAMETER tBHA tOHB tBHZ tBLZ BYTE Access Time BYTE Output Hold Time BYTE Output Delay Time BYTE Output Time MIN. MAX. 27C2100-90 MIN. MAX. 27C2100-12 MIN. MAX. 27C2100-15 MIN. MAX. UNIT
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
PROGRAMMING CHARACTERISTICS 25oC
SYMBOL ICC3 IPP2 VCC1 VPP1 PARAMETER Output High Voltage Output Voltage Input High Voltage Input Voltage Input Leakage Current Auto Select Voltage Supply Current (Program Verify) Supply Current(Program) Fast Programming Supply Voltage Fast Programming Voltage 6.00 12.5 -0.3 11.5 MIN. 12.5 6.50 13.0 MAX. UNIT VIL, 5.5V CONDITIONS -0.40mA 2.1mA
PROGRAMMING CHARACTERISTICS 25oC
SYMBOL tOES tDFP tVPS tVCS tCES PARAMETER Address Setup Time Setup Time Data Setup Time Address Hold Time Data Hold Time Enable Output Float Delay Setup Time Program Pulse Width Setup Time Setup Time Data valid from MIN. MAX. UNIT CONDITIONS
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
WAVEFORMS(MX27C2048)
READ CYCLE (WORD MODE)
ADDRESS INPUTS
tACC
DATA ADDRESS
DATA
VALID DATA
FAST PROGRAMMING ALGORITHM WAVEFORM
PROGRAM
PROGRAM VERIFY
Addresses
Hi-z DATA STABLE DATA VALID
DATA
VPP1
tDFP
tVPS VCC1
tVCS
tCES
tOES
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
WAVEFORMS(MX27C2100)
READ CYCLE (BYTE MODE)
HIGH-Z
HIGH-Z
tACC
BYTE/VPP
Q0-Q7
VALID DATA
tBHA tOHB
VALID DATA
Q15-Q8
tBHZ tBLZ
VALID DATA
FAST PROGRAMMING ALGORITHM WAVEFORM
PROGRAM
VERIFY
Addresses
VALID ADDRESS
DATA
VPP1
DATA
DATA VALID
tDFP
BYTE/VPP
tVPS VCC1
tVCS
tOES
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
ORDERING INFORMATION
PLASTIC PACKAGE
PART ACCESS TIME OPERATING CURRENT (ns) MX27C2100PC-70 MX27C2100PC-90 MX27C2100PC-12 MX27C2100PC-15 MX27C2048PC-55 MX27C2048PC-70 MX27C2048PC-90 MX27C2048PC-12 MX27C2048PC-15 MX27C2048QC-55 MX27C2048QC-70 MX27C2048QC-90 MX27C2048QC-12 MX27C2048QC-15 MX27C2048TC-55 MX27C2048TC-70 MX27C2048TC-90 MX27C2048TC-12 MX27C2048TC-15 STANDBY CURRENT MAX.(mA) PACKAGE MAX.(uA) DIP(ROM out) DIP(ROM out) DIP(ROM out) DIP(ROM out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) DIP(JEDEC out) PLCC PLCC PLCC PLCC PLCC TSOP(I) TSOP(I) TSOP(I) TSOP(I) TSOP(I)
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
PACKAGE INFORMATION
40-PIN PLASTIC DIP(600 mil)
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
44-PIN PLASTIC LEADED CHIP CARRIER(PLCC)
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
40-PIN PLASTIC TSOP
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
REVISION HISTORY
Revision Description SWITCHING TEST WAVEFORMS: 90/120/150ns, driving level revised from 2.4V/0.4V 3.0V/0V. 1)Eliminate Interactive Programming Mode. 2)40-CDIP package quartz len, change square shape. 100uA-> 10uA Cancel Ceramic package type Cancel "Ultraviolet Erasable" wording General Description modify Package Information Page Date 10/23/1996 6/13/1997 8/8/1997 P1,2,3,13,14 MAR/01/2000 AUG/22/2001 P14~16
P/N: PM0158
REV. 4.3, AUG. 2001
MX27C2100/27C2048
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