QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver with Integrate

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QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver with Integrate

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QS5935
QUALITY SEMICONDUCTOR, INC.
Skew CMOS Clock Driver with Integrated Loop Filter
DESCRIPTION
QS5935
Five noise CMOS level outputs 500ps output skew, Q0-Q4 Outputs 3-state reset while OE/RST disable feature frequency testing Internal loop filter network Balanced drive outputs ±36mA 80MHz maximum frequency Industrial temperature range Available space saving QSOP package
QS5935 Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock input. Five outputs available: Q0-Q4. Careful layout design ensure <500ps skew between Q0-Q4. QS5935 includes internal filter which provides excellent jitter characteristics eliminates need external components. also disabled PLL_EN signal allow frequency testing. QS5935 designed cost sensitive high-performance computing systems, workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QSOP package, QS5935 clock driver represents best value small form factor, high-performance clock management products.
Figure Functional Block Diagram
PLL_EN FEEDBACK CLK_IN DIVIDE
OE/RST
MDSC-00043-01 AUGUST 1998
QUALITY SEMICONDUCTOR, INC.
QS5935 Figure Configuration (All Pins View)
QSOP
OE/RST FEEDBACK AVCC AGND CLK_IN PLL_EN
Table Description
Name CLK_IN FEEDBACK Q0-Q4 OE/RST PLL_EN AVCC AGND Functional Description Reference clock input
External feedback provides flexibility different output frequency relationships. Clock outputs Output enable/asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled.
enable. Enables disables PLL. Allows CLK_IN input single-stepped system debug. Power supply output buffers. Power supply phase lock loop other internal circuitries. Ground supply output buffers. Ground supply phase lock loop other internal circuitries.
QUALITY SEMICONDUCTOR, INC.
MDSC-00043-01 AUGUST 1998
QS5935 Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 7.0V Input Voltage -0.5V 0.5V Maximum Power Dissipation 85°C 0.5W TSTG Storage Temperature -65° 150°C
Note: Stresses greater than those listed under absolute maximum ratings cause permanent damage devices that result functional reliability type failures.
Table Capacitance
25°C, 1MHz, Pins COUT QSOP Unit
Note: Capacitance characterized tested.
Table Electrical Characteristics
Industrial -40°C 85°C, 5.0V ±10% Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Test Conditions
Guaranteed Logic HIGH Level Guaranteed Logic Level -36mA -100µA Min., 36mA Min., 100µA
Unit 0.45
Output Voltage
-0.75 -0.20
Input Hysteresis Output Leakage Current VOUT VOUT GND, Max., Outputs disabled Input Leakage Current Max.,VIN
Table Power Supply Characteristics
Symbol ICCQ ICCD
Note: Guaranteed characterization tested.
Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current(1)
Test Conditions Max., OE/RST Low, CLK_IN Low, outputs unloaded Max., 3.4V Max.,
Unit
MDSC-00043-01 AUGUST 1998
QUALITY SEMICONDUCTOR, INC.
QS5935 Table Switching Characteristics
Industrial -40°C 85°C, 5.0V ±10% Symbol TSKR TSKF TLOCK TPZH TPZL TPHZ TPLZ TPWC Description(1) Output Skew Between Rising Edges, Q0-Q4
(2,3)
TCYC/2 -0.15 -500
TCYC/2
Unit
Output Skew Between Falling Edges, Q0-Q4(2,3) Pulse Wdith, Cycle Cycle Jitter
(2,5)
0.15
CLK_IN Feedback Delay(2,6) CLK_IN Phase Lock Output Enable Time, OE/RST HIGH
Output Disable Time, OE/RST HIGH LOW(2,4) Output Rise/Fall Times,0.2VCC~0.8VCC(2) Maximum Input Rise Fall Times, 0.8V 2.0V Input Clock Frequency Input Clock Pulse, HIGH LOW(7) Duty Cycle, CLK_IN
Notes: Figure test load termination. Test circuit used output enable/disable parameters. Test circuit used other timing parameters. This parameter guaranteed characterization tested. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade). Measured open loop mode PLL_EN Jitter characterized using oscilloscope, output 20MHz. Measurement taken cycle after jitter. measured device inputs 1.5V, output 80MHz. Input timing requirements guaranteed design tested. Where pulse width implied less than tPWC limit, tPWC limit applies.
QUALITY SEMICONDUCTOR, INC.
MDSC-00043-01 AUGUST 1998
QS5935 Figure Test Loads Waveforms
Test circuit used output enable/disable parameters. Test circuit used other timing parameters.
7.0V OUTPUT 30pF OUTPUT
Test Circuit
1.0ns 3.0V 2.0V 1.5V 0.8V 1.0ns 0.8VCC 0.5VCC 0.2VCC
Test Circuit
Input Test Waveform
ENABLE
CMOS Output Waveform
DISABLE
CONTROL INPUT OUTPUT NORMALLY tPZL SWITCH CLOSED tPZH 0.5VCC tPHZ tPLZ
3.5V 0.3V 0.3V
1.5V
Figure Timing Diagram
CLK_IN FEEDBACK tSKF Q0-Q4
OUTPUT NORMALLY HIGH
SWITCH OPEN
0.5VCC
Enable Disable Times
Notes: Figure applies output connected FEEDBACK. parameters measured 0.5VCC except TPD, which measures 1.5V.
MDSC-00043-01 AUGUST 1998
QUALITY SEMICONDUCTOR, INC.

QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver with Integrate

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