QUALITY SEMICONDUCTOR, INC. Skew Clock Driver With Integrated Loo
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QS5931T ADVANCE INFORMATION
QUALITY SEMICONDUCTOR, INC.
Skew Clock Driver With Integrated Loop Filter
DESCRIPTION
QS5931T ADVANCE INFORMATION
noise level outputs outputs, output <250ps output skew, Q0-Q4 Outputs 3-state reset while OE/RST disable feature frequency testing Internal loop filter network Internal VCO/2 option Balanced drive outputs 24mA 80MHz maximum frequency Industrial temperature range Available space saving QSOP package
SYNC OE/RST
FEEDBACK
QS5931T Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock input. outputs available: Q0Q4, Q/2. Careful layout design ensure <250ps skew between Q0-Q4, outputs. QS5931T includes internal filter which provides excellent jitter characteristics eliminates need external components. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. QS5931T designed cost sensitive highperformance computing systems, workstations, multiboard computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QSOP package, QS5931T clock driver represents best value small form factor, highperformance clock management products.
more information clock driver products, Application Note AN-22A.
Figure Functional Block Diagram
PLL_EN
PHASE DETECTOR LOOP FILTER
FREQ_SEL
MDSC-00029-00 DECEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5931T ADVANCE INFORMATION Figure Configuration (All Pins View)
QSOP
OE/RST FEEDBACK AVCC AGND SYNC FREQ_SEL
PLL_EN
Table Description
Name SYNC FREQ_SEL Functional Description Reference clock input
FEEDBACK
Q0-Q4
frequency select. choosing optimal operating frequency depending input frequency. HIGH higher frequencies, lower frequencies. feedback input which connected either output. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched phase, frequency half frequency. Output enable/asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled. enable. Enables disables PLL. Allows SYNC input singlestepped system debug. Power supply output buffers. Power supply phase lock loop other internal circuitries. Ground supply output buffers. Ground supply phase lock loop other internal circuitries.
OE/RST PLL_EN AVCC AGND
QUALITY SEMICONDUCTOR, INC.
MDSC-00029-00 DECEMBER 1997
QS5931T ADVANCE INFORMATION Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Input Voltage -0.5V +0.5V Maximum Power Dissipation 85°C watts TSTG Storage Temperature -65° +150°C
Note: Stresses greater than those listed under absolute maximum ratings cause permanent damage devices that result functional reliability type failures.
Table Output Frequency Specifications
Industrial: -40°C +85°C, 5.0V Symbol FMAX_Q FMAX_Q/2 FMIN_Q FMIN_Q/2 Description Frequency, Q0-Q4 Frequency, Frequency, Q0-Q4 Frequency, Units
Table Frequency Selection Table
Output Used FREQ_SEL Feedback HIGH HIGH
Q0-Q4
Allowable SYNC(1) Range (MHz) FMAX_Q/2 FMAX_Q FMAX_Q/2/2 FMAX_Q/2
Output Frequency Relationships Q0-Q4 SYNC SYNC/2 SYNC SYNC/2 SYNC SYNC SYNC SYNC
FMIN_Q/2
FMIN_
FMIN_Q/2/2 FMIN_Q/2
Q0-Q4
Note: Operation specified SYNC frequency range guarantees that will operate optimal range 20MHz FMAX_Q Operation with Sync inputs outside specified frequency ranges result invalid out-of-lock outputs. FREQ_SEL only affects frequency does affect output frequencies.
Table Capacitance
25°C, 1MHz, Pins COUT QSOP Unit
Note: Capacitance characterized tested.
MDSC-00029-00 DECEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5931T ADVANCE INFORMATION Table Electrical Characteristics Over Operating Range
Industrial: -40°C +85°C, 5.0V Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Test Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level Min., -24mA Min., -100µA Output Voltage Min., 24mA Min., 100µA Input Hysteresis Output Leakage Current Input Leakage Current VOUT VOUT GND, Max., Outputs disabled Max., 0.45 Unit
Table Power Supply Characteristics
Industrial: -40°C +85°C, 5.0V Symbol ICCQ ICCD
Note:
Parameter Quiescent Power Supply Current Power Supply Current Input HIGH Dynamic Power Supply Current(1)
Test Conditions
Max., OE/RST Low, SYNC Low, outputs unloaded Max., 3.4V Max.,
Unit
Guaranteed characterization tested.
QUALITY SEMICONDUCTOR, INC.
MDSC-00029-00 DECEMBER 1997
QS5931T ADVANCE INFORMATION Table Switching Characteristics Over Operating Range
Industrial: -40°C +85°C, 5.0V Symbol tSKR tSKF tLOCK tPZH tPZL tPHZ tPLZ Description(1) Output Skew Between Rising Edges, Q0-Q4
(2,3)
Unit
Output Skew Between Falling Edges, Q0-Q4, Q/2(2,3) Pulse Width, Q0-Q4, outputs, 80MHz(2) Cycle Cycle Jitter
(2,5)
TCY/2 -0.4 TCY/2 +0.4 -100
0.25
SYNC Input Feedback Delay(2,6) SYNC Phase Lock Output Enable Time, OE/RST HIGH
Output Disable Time, OE/RST HIGH LOW(2,4) Output Rise/Fall Times, 0.8V-2.0V(2)
Notes: Figure test load termination. Test circuit used output enable/disable parameters. Test circuit used other timing parameters. This parameter guaranteed characterization tested. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade). Measured open loop mode PLL_EN Jitter characterized using oscilloscope, output 20MHz. Measurement taken cycle after jitter. FREQUENCY SELECTION TABLE information proper FREQ_SEL level specified input frequencies. measured device inputs 1.5V, output 80MHz.
Table Input Timing Requirements
Industrial: -40°C +85°C, 5.0V Symbol tPWC Description FMAX_Q Unit
Maximum Input Rise Fall Times, 0.8V 2.0V Input Clock Frequency, SYNC(1) Input Clock Pulse, HIGH LOW(2) Duty Cycle, SYNC
Notes: Table Table more detail allowable SYNC input frequencies different speed grades with different FEEDBACK FREQ_SEL combinations. Input timing requirements guaranteed design tested. Where pulse width implied less than tPWC limit, tPWC limit applies.
MDSC-00029-00 DECEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5931T ADVANCE INFORMATION Figure Test Loads Waveforms
Test circuit used output enable/disable parameters. Test circuit used other timing parameters.
7.0V OUTPUT 30pF OUTPUT 20pF
Test Circuit
Test Circuit
1.0ns 3.0V 2.0V 1.5V 0.8V
1.0ns
2.0V 1.5V 0.8V
Input Test Waveform
ENABLE
Output Waveform
DISABLE
CONTROL INPUT OUTPUT NORMALLY tPZL SWITCH CLOSED tPZH SWITCH OPEN 1.5V 1.5V
1.5V 3.5V 0.3V 0.3V
tPLZ
OUTPUT NORMALLY HIGH
tPHZ
Enable Disable Times
Figure Timing Diagram
SYNC FEEDBACK tSKF Q0-Q4 tSKALL tSKR
Notes: Figure applies output connected FEEDBACK. parameters measured 1.5V.
QUALITY SEMICONDUCTOR, INC.
MDSC-00029-00 DECEMBER 1997
QS5931T ADVANCE INFORMATION OPERATION
Phase Locked Loop (PLL) circuit included QS5931T provides replication incoming SYNC clock signals. manipulation that signal, such frequency multiplying inversion performed digital logic following (see block diagram). advantage circuit provide effective zero propagation delay between output input signals. fact, adding delay circuits feedback path, `propagation delay' even negative! Figure shows simplified schematic QS5931T circuit:
Figure Simplified Diagram QS5931T Feedback
INPUT PHASE DETECTOR
VCO/2
phase difference between output input frequencies feeds which drives outputs. Whichever output back, will stabilize same frequency input. Hence, this true negative feedback closed loop system. most applications, output will optimally have zero phase shift with respect input. fact, internal loop filter QS5931T typically provides within 150ps phase shift between input output.
user wishes vary phase difference (typically compensate backplane delays), this most easily accomplished adding delay circuits feedback path. respective output used feedback will advanced amount delay feedback path. other outputs will retain their proper relationships that output.
MDSC-00029-00 DECEMBER 1997
QUALITY SEMICONDUCTOR, INC.
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