QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver With Integrate

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QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver With Integrate

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QS5930
QUALITY SEMICONDUCTOR, INC.
Skew CMOS Clock Driver With Integrated Loop Filter
DESCRIPTION
QS5930
output, outputs Useful Pentium, PowerPC, systems Internal loop filter network noise level outputs 250ps rising edge output skew Balanced Drive Outputs 24mA bypass feature frequency testing Internal VCO/2 option wider frequency range Outputs tri-state reset while Space saving 20-pin QSOP(Q) 2000V Latch-up -300mA
Figure Functional Block Diagram
FEEDBACK SYNC
PHASE DETECTOR LOOP FILTER
QS5930 Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock input. outputs available: Q4Q0, Q/2. Careful layout design insures less than 250ps skew between outputs. QS5930 includes internal loop filter eliminate need external components, level output signals lower noise. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. QS5930 designed cost sensitive high-performance computing systems such PentiumTM, PowerPCTM, other high performance applications. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. QSOP package, QS5930 clock driver represents best value small form factor, high-performance clock management products. more information clock driver products, Application Note AN-22A.
PLL_EN
FREQ_SEL
Pentium trademark Intel Corporation PowerPC trademark Corporation
MDSL-00093-03 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5930 Figure Configuration (All Pins View)
QSOP
FEEDBACK AVCC AVCC SYNC FREQ_SEL
PLL_EN
Table Descriptions
Name SYNC FREQ_SEL Functional Description Reference clock input
FEEDBACK
Q4-Q0
frequency select. choosing optimal operating frequency depending input frequency. HIGH higher frequencies, lower frequencies. feedback input which connected either output. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched phase, frequency half frequency. Output enable. When HIGH, outputs active (normal operation). When LOW, outputs held tri-stated condition output registers reset. enable. enabled when HIGH (normal operation), disabled when (allows SYNC input single-stepped system debug).
PLL_EN
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Maximum Power Dissipation watts TSTG Storage Temperature -65° +150°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional reliability type failures.
QUALITY SEMICONDUCTOR, INC.
MDSL-00093-03 NOVEMBER 1997
QS5930 Table Output Frequency Specifications
Industrial: -40°C +85°C, 5.0V Symbol FQ/2 Description Maximum frequency, Q4-Q0 Maximum frequency, output 66.6 33.3 Units
Table Frequency Selection Table
Output Used Feedback Q4-Q0 Q4-Q0 Allowable SYNC(1) Range (MHz) Output Frequency Relationships Outputs SYNC SYNC SYNC SYNC SYNC SYNC SYNC
FREQ_SEL
Note: Operation specified SYNC frequency range guarantees that will operate optimal range 20MHz 150MHz. Operation with SYNC input outside specified frequency ranges result invalid out-of-lock outputs. FREQ_SEL only affects frequency does affect output frequencies.
SYNC
Table Capacitance
25°C, 1MHz, VOUT Pins
COUT
QSOP
Unit
Note: Capacitance characterized tested.
Figure Test Load
Test Circuit used output enable/disable parameters. Test Circuit used other timing parameters.
7.0V OUTPUT 30pF OUTPUT 20pF
Test Circuit
MDSL-00093-03 NOVEMBER 1997 QUALITY SEMICONDUCTOR, INC.
Test Circuit
QS5930 Table Electrical Characteristics Over Operating Range
Industrial: -40°C +85°C, 5.0V Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Test Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level Min., -24mA Min., -100µA Output Voltage Min., 24mA Min., 100µA Output Leakage Current Input Leakage Current VOUT VOUT GND, Max. Max., 0.55 Unit
Table Power Supply Characteristics
Symbol ICCD Parameter Input Power Supply Current Input HIGH(2) Dynamic Power Supply Current Output(3) Test Conditions(1) Max., 3.4V Max.
Typ.
Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. This specification does apply PLL_EN input. Guaranteed tested. parameters, test conditions also assume output loading.
Description(1)
Table Input Timing Requirements
Industrial: -40°C +85°C, 5.0V Symbol tPWC QS5930 Unit
Maximum Input Rise Fall Times, 0.8V 2.0V Input Clock Frequency, SYNC(3) Input Clock Pulse, HIGH Duty Cycle, SYNC
QUALITY SEMICONDUCTOR, INC.
MDSL-00093-03 NOVEMBER 1997
QS5930 Table Switching Characteristics Over Operating Range
Industrial: -40°C +85°C, 5.0V Symbol tSKR tSKF tLOCK tPZH tPZL tPHZ tPLZ Description(1) Output Skew Between Rising Edges, Q4-Q0 Q/2(2,4) Output Skew Between Falling Edges, Q4-Q0 Pulse Width(2) Cycle Cycle Jitter, 33MHz(6) SYNC Input Feedback Delay, 10MHz SYNC Input Feedback Delay, 33MHz, 1.5V(2) SYNC Phase Lock(2) Output Enable Time, HIGH
(2,4)
QS5930
Unit
TCY/2 -0.5 TCY/2 +0.5 -100 -100
Output Disable Time, HIGH LOW(2,5) Output Rise Fall Times, 0.8V 2.0V(2)
Notes: Test Circuit Waveforms. Minimums guaranteed tested. This parameter guaranteed design tested. specification based output feedback. FREQUENCY SELECTION TABLE more detail allowable SYNC input frequencies different feedback combinations. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade). Measured open loop mode PLL_EN Jitter characterized using digital oscilloscope. Jitter characterized tested. FREQUENCY SELECTION TABLE information proper FREQ_SEL level specified SYNC input frequencies.
MDSL-00093-03 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.

QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver With Integrate

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