QUALITY SEMICONDUCTOR, INC. Programmable Frequency Generator

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QUALITY SEMICONDUCTOR, INC. Programmable Frequency Generator

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QS5925 PRELIMINARY
QUALITY SEMICONDUCTOR, INC.
Programmable Frequency Generator
QS5925 PRELIMINARY
DESCRIPTION
QS5925 high-performance, skew, jitter phase-locked loop (PLL) clock driver. provides precise phase frequency alignment clock outputs externally applied clock input internal crystal oscillator. QS5925 been specially designed interface with Gigabit Ethernet Fast Ethernet applications providing 125MHz clock from 25MHz input. also programmed provide output frequencies ranging from 3.125MHz 160MHz with input frequencies ranging from 3.125MHz 100MHz. QS5925 includes internal filter that provides excellent jitter characteristics eliminates need external components. When using optional crystal input, must connected pin. on-chip crystal oscillator requires "Fundamental Mode" crystal with less than includes internal crystal capacitors (crystal load capacitance nominally 20pF) eliminating need external capacitors.
programmable frequency outputs Optional crystal input, internal capacitors Balanced Drive Outputs ±12mA disable mode frequency testing Tri-state output enable (OE) PHY/MAC networking applications Extended 85°C operation Input frequencies 100MHz Output frequencies 160MHz tolerant inputs output skew/jitter External feedback, internal loop filter 3.0V 3.6V supply voltage Available 16-pin QSOP package
Figure Functional Block Diagram
SELECT MODE CLKIN PHASE DETECTOR LOOP FILTER OPTIONAL CRYSTAL XTAL FREQUENCY DIVIDER
MDSC-00030-02 JANUARY 1999
QUALITY SEMICONDUCTOR, INC.
QS5925 PRELIMINARY Figure Configuration (All Pins View)
QSOP
GNDQ VDDQ CLKIN
VDDN GNDN GNDN
Table Description
Name CLKIN S0:1 Q0:2 Functional Description Input clock Crystal input Crystal output
feedback input which connected output pin. locks onto edge signal. Mode/Frequency select inputs (three-level) Clock outputs Programmable divide-by-N clock output Tri-state output enable. When asserted HIGH, clock outputs high impedance. Power supply output buffers Ground supply output buffers Power supply Ground supply
VDDN GNDN VDDQ
Note: best accuracy, parallel resonant crystal.
QUALITY SEMICONDUCTOR, INC.
MDSC-00030-02 JANUARY 1999
QS5925 PRELIMINARY Table Divide Selection Table
Divide-by-N Value FACTORY TEST
Mode TEST(3)
Notes: Factory test mode: operation specified. Ethernet mode (use 25MHz input frequency feedback). Test mode frequency testing. this mode, bypasses (VCO powered down). Frequency must 1MHz dynamic circuits frequency dividers.
Table Functionally Table
Output Used Feedback Q0-Q2 Allowable Range (MHz)(1) Minimum Maximum 25/N 160/N
CLK/N
Output Frequency Relationships Q0-Q2
Note: Operation specified frequency range guarantees that will operate optimal range 25MHz 160MHz. Operation with outside specified frequency ranges result invalid out-of-lock outputs.
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 7.0V Output Voltage VOUT -0.5V 0.5V Input Voltage -0.5V 7.0V Input Diode Current with -20mA Maximum Power Dissipation 85°C, 0.55W TSTG Storage Temperature -65°C 150°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional reliability type failures.
Table Operating Conditions
Symbol Parameter Power Supply Voltage Operating Temperature Load Capacitance Input Capacitance 1MHz, 25°C
Unit
MDSC-00030-02 JANUARY 1999
QUALITY SEMICONDUCTOR, INC.
QS5925 PRELIMINARY Table Electrical Characteristics Over Operating Range
Symbol VIHH(1) VILL(1) VIMM(1) IIHH IILL IIMM IDDQ Parameter Input High Voltage Conditions CLKIN Input Voltage CLKIN Input Voltage VDD/2 Input High Current VDD; CLKIN VDD; Input Current CLKIN -150 Input Current VDD/2; Quiescent Supply Current Max; GND; outputs unloaded Supply Current Input Max; 3.0V Dynamic Supply Current 3.6; MID; GND; GND; 60MHz; outputs unloaded Output High Voltage 3.0V, -12mA 3.0V, -100uA Output Voltage 3.0V, 12mA 3.0V. 100uA Unit
Note: These inputs normally wired VCC, unconnected. inputs switched real time, function timing outputs glitch, require additional lock time before datasheet limits achieved.
Table Electrical Characteristics Over Operating Range
Symbol Dt_INPUT TR_INPUT TF_INPUT FOSC FOUT Parameter Rise Time(1) Fall Time(1) Duty Cycle(1) CLKIN Propagation Delay(1) Skew (output output)(1) Cycle Cycle Jitter(1) CLKIN Duty Cycle(1) CLKIN Rise Time(1) CLKIN Fall Time(1) Oscillator Frequency Output Frequency Input Frequency
pany
0.15 0.55 0.20
VDD/2 0.07
Q0-Q2 used feedback used feedback
Conditions 0.8V 2.0V 2.0V 0.8V VDD/2 VDD/2
-1.6
0.70 0.70 -0.95
-0.50
Unit
VDD/2; Q0-Q2 VDD/2; Q0:2 125MHz output (Q0:2) 1.5V 0.8V 2.0V 0.8V 2.0V
25/N
160/N
Note: Guaranteed design, subject 100% production testing.
QUALITY SEMICONDUCTOR, INC.
MDSC-00030-02 JANUARY 1999
QS5925 PRELIMINARY Figure Test Loads Waveforms
3.0V 2.0V VCC/2
Input Test Waveform
OUTPUT 15pF
2.0V VCC/2
Test Load
Output Waveform
QS5925
QS5925 general-purpose phase-locked loop (PLL) that used zero delay buffer clock multiplier. generates three outputs same frequency input, divided output, where determined frequency select pins. QS5925 accept types input signal. first reference clock generated another device board which needs reproduced with minimal delay between incoming clock output. second external crystal. When used first mode, crystal input (X1) should tied ground crystal output (X2) should left unconnected. Figure depicts applications:
connecting phase detector QS5925 will adjust output frequency incoming clock such fashion that inputs CLKIN) will have nearly zero phase frequency difference. addition, copy clock divided from increments one. divide will depend selection (Table pins three level inputs that allow total seven different modes division. They connected HIGH, left unconnected provide level internal resistor network will bias signal level 0.5VDD). Another QS5925 connect (see Figure
Figure
CLKIN QS5925
Figure
CLKIN QS5925
MDSC-00030-02 JANUARY 1999
QUALITY SEMICONDUCTOR, INC.
QS5925 PRELIMINARY
Connected this fashion, QS5925 only becomes zero delay buffer, also clock multiplier. With proper selection Q0-Q2 outputs will generate times input clock frequency. When used this mode, must make sure that output frequency specification violated. Please refer "output frequency when used feedback" (for additional information, please consult factory). There some applications where higher fan-out required. These kinds applications could addressed using QS5925 conjunction with clock buffer such QS53805. Figure shows higher fan-out with different clock rates generated.
Figure
CLKIN QS5925 QS53805 COPIES
COPIES
connecting, QS53805 outputs input QS5925, propagation delay from CLKIN output QS53805 will nearly zero. second drive input QS5925 external crystal. When connecting external crystal pins must
shorted CLKIN (pin shown Figure best accuracy, parallel resonant crystal with crystal load capacitance rating 20pF should used. reduce parasitic between external crystal QS5925, recommended connect crystal close possible pins.
Figure
CLKIN QS5925 XTAL
QUALITY SEMICONDUCTOR, INC.
MDSC-00030-02 JANUARY 1999
QS5925 PRELIMINARY
questions often asked what accuracy clock generators? applications where clock synthesizers used, terms frequency accuracy frequency error used interchangeably. Here, frequency accuracy error) based factors. input frequency other multiplication factor. Clock multipliers synthesizers) governed equation: reference divide ("N") "1", equation strong function feedback divide ("M"). addition, since feedback integer, output frequency error accuracy) merely function accurate input instance, QS5925 could accept forms input, from crystal oscillator (see figure other from crystal (see figure using 20MHz clock with multiplication factor (with accuracy parts million), easily have copies 100MHz clock with ±30PPM accuracy. Frequency accuracy defined following equation:
Output Frequency (M)* Input Frequency where feedback divide reference divide. ratio integer, then output frequency will exact multiple input. other hand, ratio were whole number, output clock would exact multiple input. case QS5925, since
Accuracy (Measured Freq. Nominal Freq.) Nominal Frequency where measured frequency average frequency over certain number cycles (typically 10,000) nominal frequency desired frequency.
MDSC-00030-02 JANUARY 1999
QUALITY SEMICONDUCTOR, INC.
QS5925 PRELIMINARY Ordering Information
Clock Management Product Prefix (QS5) Part Number Package (150-mil QSOP)
Figure Packaging Information 150-mil QSOP Package Code Quarter-Size Outline Package Plastic Small Outline Gull-Wing
SEATING PLANE
Notes: Refer applicable symbol list. dimensions inches. number lead positions. Dimensions measured maximum material condition include mold flash. Allowable mold flash 0.006in. side. Lead coplanarity 0.004in. maximum.
JEDEC# DWG# Symbol
0.060 0.004 0.009 0.007 0.189 0.150
MO-137AB PSS-16A 0.064 0.006 0.010 0.008 0.193 0.154
0.068 0.008 0.012 0.010 0.197 0.157 0.244 0.016 0.035
0.025 0.230 0.236 0.010 0.016 0.006 0.013 0.025 0.009 0.010
QUALITY SEMICONDUCTOR, INC.
MDSC-00030-02 JANUARY 1999

QUALITY SEMICONDUCTOR, INC. Programmable Frequency Generator

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