QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver With Integrate

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QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver With Integrate

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QS5917T-T
QUALITY SEMICONDUCTOR, INC.
Skew CMOS Clock Driver With Integrated Loop Filter
DESCRIPTION
QS5917T-T
output, output, output Outputs tri-state while Internal loop filter network noise level outputs 500ps output skew, Q0-Q4 disable feature frequency testing Balanced Drive Outputs 24mA 132MHz maximum frequency (2xQ output) compatible with Motorola MC88915 2000V Latch-up -300mA Space saving 28-pin QSOP PLCC packages
Figure Functional Block Diagram
REF_SEL SYNC0 SYNC1
PHASE DETECTOR
QS5917T-T Clock Driver uses internal phase locked loop (PLL) lock skew outputs reference clock inputs. Eight outputs available: Q0-Q4, 2xQ, Q/2, Careful layout design insures 500ps skew between Q4-Q0, outputs. QS5917T-T includes internal filter which provides excellent jitter characteristics eliminates need external components. addition, level outputs reduce clock signal noise. Various combinations feedback divide-by-2 path allow applications customized linear operation over wide range input SYNC frequencies. also disabled PLL_EN signal allow frequency testing. LOCK output asserts indicate when phase lock been achieved. QS5917T-T designed high-performance workstations, multi-board computers, networking hardware, mainframe systems. Several used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks.
more information clock driver products, Application Note AN-22A.
LOCK FEEDBACK
PLL_EN
FREQ_SEL
LOOP FILTER
MDSL-00060-06 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5917T-T Figure Configuration (All Pins View)
QSOP PLCC
FEEDBACK REF_SEL SYNC0 AVCC AGND SYNC1 FREQ_SEL
FREQ_SEL
Table Descriptions
Name SYNC0 SYNC1
REF_SEL
Functional Description Reference clock input Reference clock input Reference clock select. When selects SYNC1. When selects SYNC0. frequency select. choosing optimal operating frequency depending input frequency. feedback input which connected user selected output pin. External feedback provides flexibility different output frequency relationships. Frequency Selection Table more information. Clock outputs Clock output. Matched frequency, inverted with respect Clock output. Matched phase, frequency double frequency. Clock output. Matched phase, frequency half frequency.
FREQ_SEL FEEDBACK
Q0-Q4 LOCK PLL_EN
lock indication signal. indicates positive lock. indicates that locked outputs synchronized inputs. Asynchronous reset. Resets output registers. When outputs held tri-stated condition. When outputs enabled (normal operation). enable. When enabled (normal operation). When disabled (for testing purposes). Connection
QUALITY SEMICONDUCTOR, INC.
MDSL-00060-06 NOVEMBER 1997
PLL_EN
LOCK PLL_EN
INDEX FEEDBACK REF_SEL SYNC0 AVCC AGND SYNC1
2x26 LOCK
QS5917T-T Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Maximum Power Dissipation watts TSTG Storage Temperature -65° +150°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional reliability type failures.
Table Output Frequency Specifications
Industrial: -40°C +85°C, 5.0V Symbol F2xQ FQ/2 Description Maximum frequency, output Maximum frequency, Q0-Q4, outputs Maximum frequency, output 17.5 -100 -132 Units
Table Frequency Selection Table
Output Allowable SYNC(1) Used Range (MHz) FREQ_SEL Feedback Q4-Q0 F2xQ F2xQ F2xQ F2xQ(2) F2xQ F2xQ F2xQ F2xQ
SYNC
Output Frequency Relationships Outputs -(SYNC -SYNC SYNC -(SYNC -(SYNC -SYNC SYNC -(SYNC SYNC SYNC -SYNC SYNC SYNC SYNC -SYNC SYNC
SYNC SYNC -SYNC SYNC SYNC SYNC -SYNC SYNC
Q4-Q0
SYNC -SYNC SYNC SYNC SYNC -SYNC SYNC
Notes: Operation specified SYNC frequency range guarantees that will operate optimal range 20MHz F2XQMAX. Operation with Sync inputs outside specified frequency ranges result invalid out-of-lock outputs. FREQ_SEL only affects frequency does affect output frequencies. -132 speed grade, maximum input frequency restricted 100MHz.
Table Capacitance
25°C, 1MHz, VOUT Pins COUT QSOP PLCC Unit
Note: Capacitance characterized tested.
MDSL-00060-06 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5917T-T Table Electrical Characteristics Over Operating Range
Industrial: -40°C +85°C, 5.0V Symbol Parameter Input HIGH Voltage Input Voltage Output HIGH Voltage Test Conditions Guaranteed Logic HIGH Level Guaranteed Logic Level Min., -24mA(1) Min., -100µA Output Voltage Min., 24mA(1) Min., 100µA Output Leakage Current Input Leakage Current VOUT VOUT GND, Max. Max., 0.55 Unit
Notes: 12mA -12mA, respectively, LOCK output.
Table Power Supply Characteristics
Symbol ICCD Parameter Input Power Supply Current Input HIGH(2) Dynamic Power Supply Current(3)
Test Conditions(1)
Max., 3.4V Max.
Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. This specification does apply PLL_EN input. Guaranteed tested. parameters, test conditions also assume output loading.
Figure Test Load
Test Circuit used output enable/disable parameters. Test Circuit used other timing parameters.
OUTPUT 20pF OUTPUT 30pF
7.0V
TEST CIRCUIT
TEST CIRCUIT
MDSL-00060-06 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5917T-T Table Switching Characteristics Over Operating Range
Industrial: -40°C +85°C, 5.0V Symbol tSKR tSKF tSKALL tLOCK tPZH tPZL tPHZ tPLZ Description(1) Output Skew Between Rising Edges, Q0-Q4 Q/2(2,3) Output Skew Between Falling Edges, Q0-Q4 Output Skew, Outputs(2,3) Pulse Width, Outputs(2) Pulse Width, Q0-Q4, Outputs Cycle Cycle Jitter, 33MHz(2,5) SYNC Input Feedback Delay, 10MHz SYNC Input Feedback Delay, 33MHz, 1.5V SYNC Phase Lock Output Enable Time, HIGH(4) Output Disable Time, HIGH LOW(2,4) Output Rise Fall Times, 0.8V 2.0V(2)
(2,3)
QS5917T-T TCY/2-0.5 TCY/2-0.5 -100 -100 TCY/2+0.5 TCY/2+0.5 0.25
Unit
Notes: Test Circuit Waveforms. Minimums guaranteed tested. This parameter guaranteed design tested. Skew specifications apply under identical environments (loading, temperature, VCC, device speed grade). Measured open loop mode PLL_EN Jitter characterized using oscilloscope. Measurement taken cycle after jitter. Jitter characterized tested. FREQUENCY SELECTION TABLE information proper FREQ_SEL level specified input frequencies.
Description(1)
Table Input Timing Requirements
Industrial: -40°C +85°C, 5.0V Symbol tPWC QS5917T-T F2XQ Unit
Maximum Input Rise Fall Times, 0.8V 2.0V Input Clock Frequency, SYNC0, SYNC1(2) Input Clock Pulse, HIGH Duty Cycle, SYNC0, SYNC1
Notes: Test Circuit Waveforms. Minimums guaranteed tested. specification based output feedback. FREQUENCY SELECTION TABLE more detail allowable SYNC input frequencies different feedback combinations.
MDSL-00060-06 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5917T-T Operation
Phase Locked Loop (PLL) circuit included QS5917T-T provides replication incoming SYNC clock signals. manipulation that signal, such frequency mulitplying inversion performed digital logic following (see block diagram). advantage circuit provide effective zero propagation delay between output input signals. fact, adding delay circuits feeback path, `propagation delay' even negative! Figure shows simplified schematic QS5917T-T circuit:
Figure Simplified diagram QS5917T-T feedback
INPUT PHASE DETECTOR
phase difference between output input frequencies feeds which drives outputs. Whichever output back, will stabilize same frequency input. Hence, this true negative feedback closed loop system. most applications, output will optimally have zero phase shift with respect input. fact, internal loop filter QS5917T-T typically provides within 150ps phase shift between input output.
user wishes vary phase difference (typically compensate backplane delays), this most easily accomplished adding delay circuits feedback path. repective output used feedback will advanced amount delay feedback path. other outputs will retain their proper relationships that output.
QUALITY SEMICONDUCTOR, INC.
MDSL-00060-06 NOVEMBER 1997

QUALITY SEMICONDUCTOR, INC. Skew CMOS Clock Driver With Integrate

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