QUALITY SEMICONDUCTOR, INC. Guaranteed Skew CMOS Output Clock Dri
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QS5820T
QUALITY SEMICONDUCTOR, INC.
Guaranteed Skew CMOS Output Clock Driver/Buffer
DESCRIPTION
QS5820T
output, skew clock signal buffer High drive FCT-type outputs Reduced swing outputs noise Input hysteresis better noise margin Monitor output Guaranteed skew 0.35ns output skew 0.7ns pulse skew 1.0ns part-to-part skew Available 40-pin QVSOP (Q2)
QS5820T clock driver/buffer circuits used clock distribution schemes where skew, high speed, small footprint primary concerns. QS5820T offers four banks five non-inverting outputs. Designed QSI's proprietary QCMOS process, this device provides propagation delay buffering with on-chip skew 0.35ns same-transition, samebank signals. QS5820T provides major skew advantages over octal type devices where total part-topart skew (tSK(t)) >1ns unacceptable. Furthermore, board area consumed QVSOP package almost one-third that typical SOIC package offered octal devices. This clock buffer product designed high performance workstation, multi-board computing telecommunications systems. QS5820T available 40-pin QVSOP package which offers world's smallest logic footprint.
Figure Functional Block Diagram Pinout
OA1-OA5
OB1-OB5 MONB
OC1-OC5
OD1-OD5 MOND
MONB MOND
MDSC-00011-00 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5820T Table Descriptions
Name OEA, OEB, OEC, INA, INB, INC, OAn, OBn, OCn, MONB, MOND Description Output Enable Inputs Clock Inputs Clock Outputs Non-disable Monitor Outputs
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Switch Voltage -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Input Diode Current with -20mA Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation watts TSTG Storage Temperature -65° +150°C
Note: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage devices that result functional reliability type failures.
Table Capacitance
25°C, 1MHz, VOUT
Pins
Pins
QVSOP
Unit
Note: Capacitance characterized tested.
Table Recommended Operating Conditions
Symbol VOUT Description Power Supply Voltage Input Voltage Voltage Applied Outputs Ambient Operating Temperature 4.75 5.25 Units
QUALITY SEMICONDUCTOR, INC.
MDSL-00011-00 NOVEMBER 1997
QS5820T Table Electrical Characteristics Over Operating Range
Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage Input Leakage Current Output Leakage Current Short Circuit Current(2,3)
Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Min., -24mA Min., 64mA Max., Max., Outputs High-Z Max., VOUT
Typ(1) -0.7
Unit -1.2 0.55
Notes: Typical values indicate 5.0V 25°C. more than output should used test this high power condition duration second. Guaranteed design tested.
Table Power Supply Characteristics
Symbol Parameter ICCD Quiescent Power Supply Current Supply Current Input HIGH Test Conditions(1)
Max.,VIN
Typ(3) Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. Guaranteed tested. Typical values reference only. Conditions 5.0V 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input duty cycle Number HIGH inputs Output frequency Number outputs
Dynamic Power Supply Current Output(2)
Max., 3.4V, 0MHz Max., Outputs enabled, duty cycle
MDSC-00011-00 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5820T Table Skew Characteristics Over Operating Range
Symbol tSK(O1) tSK(O2) tSK(p) Description
(1,2)
0.35 Unit
Skew between outputs same transition, same bank Skew between outputs same transition, different banks Duty cycle distortion (pulse skew) single output opposite transitions (tPHL-tPLH) Part-to-part skew same transition(3)
tSK(t)
Notes: Skew parameters guaranteed across temperature range, production tested. Skew parameters apply propagation delays only. Test Circuit Waveforms. tSK(t) only applies Quality Semiconductor devices same transition, same VCC, same temperature, same speed grade, same loading.
Table Switching Characteristics Over Operating Range
CLOAD 50pF, RLOAD 500.
Symbol
tPLH, tPHL tPZL, tPZH tPLZ, tPZH
Description
Unit
Propagation Delay(1, Output Rise Time, 0.8V 2.0V Output Fall Time, 2.0V 0.8V Output Enable Time Output Disable Time(3)
Notes: Test Circuit Waveforms. Minimums guaranteed tested. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delay limits imply skew. Guaranteed design tested.
QUALITY SEMICONDUCTOR, INC.
MDSL-00011-00 NOVEMBER 1997
QS5820T
MDSC-00011-00 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
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