QUALITY SEMICONDUCTOR, INC. Guaranteed Skew CMOS Clock Driver/Buf
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QS5805, QS52805, QS5806, QS52806 ADVANCE INFORMATION
QUALITY SEMICONDUCTOR, INC.
Guaranteed Skew CMOS Clock Driver/Buffer
QS5805, QS5806 QS52805, QS52806 ADVANCE INFORMATION
DESCRIPTION
QS5805 QS5806 clock driver/buffer circuits used clock buffering schemes where skew parameter. QS5805 offers banks five non-inverting outputs QS5806 provides inverting outputs. Designed QSI's proprietary QCMOS process, these devices provide propagation delay buffering with on-chip skew 0.3ns same-transition, same-bank signals. QS52805 QS52806 have on-chip series termination resistors lower noise clock signals. QS52805 QS52806 series resistor versions recommended driving unterminated lines with capacitive loading other noise sensitive clock distribution circuits. These clock buffer products designed high-performance workstations, embedded personal computing systems. Several devices used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. Rail-to-rail output swing improves noise margin allows easy interface with CMOS inputs.
CMOS outputs Monitor output Rail-to-rail output voltage swing on-chip resistors available noise Input hysteresis better noise margin Guaranteed skew 0.3ns same bank 0.6ns opposite transition 1.0ns different devices Industrial temperature range Available QSOP SOIC (SO)
Fore more information Application Note AN-21A more information low-skew clock buffers.
Figure Functional Block Diagram
QS5805, QS52805 QS5806, QS52806
OA5-OA1 OB5-OB1 OA5-OA1 OB5-OB1
Note: QS52805 QS52806 devices have series termination resistors each clock output including monitor.
MDSC-00017-00 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5805, QS52805, QS5806, QS52806 ADVANCE INFORMATION Figure Configurations (All Pins View)
QS5805, QS52805 QSOP, SOIC QS5806, QS52806 QSOP, SOIC
VCCA GNDA GNDQ
VCCB GNDB
VCCA GNDA GNDQ
VCCB GNDB
Table Description
Name OEA, INA, OAn, OBn, OAn, MON, Description Output Enable Inputs Clock Inputs Clock Outputs Monitor Output (non-disable)
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Output Voltage VOUT -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Input Diode Current with -20mA Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation 85°C, QSOP 0.82 watts SOIC 0.75 watts TSTG Storage Temperature -65° +150°C
Note: Stresses greater than those listed under absolute maximum ratings cause permanent damage devices that result functional reliability type failures.
Table Capacitance
25°C, 1MHz, QSOP Pins Pins SOIC Unit
Note: Capacitance characterized tested.
QUALITY SEMICONDUCTOR, INC.
MDSC-00017-00 NOVEMBER 1997
QS5805, QS52805, QS5806, QS52806 ADVANCE INFORMATION
Table Electrical Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V 10%, VCC-0.2V, 0.2V Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage(3) Output HIGH Voltage QS5805/5806 Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA Typ(1) -0.7 Unit -1.2 0.55 0.50
Min.,VIN VIL, -300µA -15mA -24mA Min.,VIN VIL, -12mA -24mA Min.,VIN VIL, 300µA 64mA Min.,VIN VIL, 12mA Max., VCC, 4.5V Max., VOUT VTLH VTHL Inputs Min., 12mA
IOFF ROUT
Output HIGH Voltage QS52805/52806 Output Voltage QS5805/5806 Output Voltage QS52805/52806 Input Leakage Current
Output Leakage Current Max., VOUT VCC, VOUT Power Leakage Short Circuit Current(2,3) Input Hysteresis Output Resistance QS52805/52806
Notes: Typical values indicate 5.0V 25°C. more than output should used test this high power condition duration second. Guaranteed design tested.
MDSC-00017-00 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5805, QS52805, QS5806, QS52806 ADVANCE INFORMATION Table Power Supply Characteristics
Symbol Parameter ICCD Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output(2) Total Power Supply Current Examples(2,4) Test Conditions(1) Max.,VIN Max., 3.4V Max., Outputs enabled, duty cycle Max., duty cycle, 10MHz outputs toggling Max., duty cycle, 2.5MHz outputs toggling 3.4V 3.4V Typ(3) 0.005 Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. Guaranteed characterization tested. Typical values reference only. Conditions 5.0V 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input duty cycle Number HIGH inputs Output frequency Number outputs
QUALITY SEMICONDUCTOR, INC.
MDSC-00017-00 NOVEMBER 1997
QS5805, QS52805, QS5806, QS52806 ADVANCE INFORMATION Table Skew Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V QS5805, QS5806, CLOAD 50pF, RLOAD 500. QS52805, QS52806, CLOAD 50pF resistor). 0.35
Symbol tSK(O1) tSK(O2) tSK(p)
Description(1) Skew between outputs same transition, same bank Skew between outputs banks same transition, Pulse Skew: Skew between opposite transitions same output (tPHL-tPLH) Part part skew(2)
Unit
tSK(t)
Notes: Skew parameters guaranteed across temperature range, production tested. Skew parameters measured 0.5VCC. Test Circuit Waveforms. tSK(t) only applies devices same transition, same part type, same temperature, power supply voltage, loading, package speed grade.
Table Switching Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V QS5805, QS5806, CLOAD 50pF, RLOAD 500. QS52805, QS52806, CLOAD 50pF resistor).
Symbol Description(1) tPLH tPHL
Unit
Propagation Delay(2) OAn, Output Enable Time Output Disable Time(3) Output Rise/Fall Time(3) 0.8V-2.0V 0.2VCC-0.8VCC
tPZL tPZH tPLZ tPZH tR,tF
Notes: Test Circuit Waveforms. Minimums guaranteed tested. Timing parameters measured 0.5VCC. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delay limits imply skew. Guaranteed characterization tested.
MDSC-00017-00 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5805, QS52805, QS5806, QS52806 ADVANCE INFORMATION Figure Test Circuits Waveforms
Parameter Tested
tPLZ, tPZL
Others Pulse Generator VOUT
Switch Position Closed Open
7.0V
50pF
Coax Oscilloscope
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
INPUT tPLH OUTPUT tPHL 2.0V 0.5VCC 0.8V 1.5V
INPUT tPHL 1.5V tPLH OUTPUT 0.5VCC
tSK(p) tPHL tPLH
Propagation Delay
INPUT 1.5V
tPLH1 tPHL1
INPUT
tPLHA
Pulse Skew tSK(p)
tPHLA
1.5V
0.5VCC
tSK(01) 0.5VCC
tSK(02)
OUTPUT
OUTPUT
tSK(01) tPLH2
OUTPUT
0.5VCC
tSK(02) 0.5VCC tPLHB tPHLB
OUTPUT
tPHL2
tSK(O1) |tPLH2 tPLH1| |tPHL2 tPHL1|
tSK(O2) |tPLHB tPLHA| |tPHLB tPHLA|
Output Skew (Same Bank) tSK(O1)
Ouput Skew (Different Banks) tSK(O2)
ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY SWITCH CLOSED tPZH OUTPUT NORMALLY HIGH SWITCH OPEN 1.5V 1.5V
DISABLE 1.5V tPLZ 3.5V tPLH1
INPUT
tPHL1
1.5V
PART OUTPUT
0.5VCC
tSK(t)
0.3V tPHZ 0.3V
tSK(t)
0.5VCC
PART OUTPUT
tPLH2
tPHL2
Enable Disable Times
tSK(t) tPLH2 tPLH1 tPHL2 tPHL1
Part-to-Part Skew tSK(t)
QUALITY SEMICONDUCTOR, INC.
MDSC-00017-00 NOVEMBER 1997
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