QUALITY SEMICONDUCTOR, INC. Guaranteed Skew 3.3V CMOS Clock Drive

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QUALITY SEMICONDUCTOR, INC. Guaranteed Skew 3.3V CMOS Clock Drive

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QS53807, QS532807
QUALITY SEMICONDUCTOR, INC.
Guaranteed Skew 3.3V CMOS Clock Driver/Buffer
DESCRIPTION
QS53807 QS532807
JEDEC compatible LVTTL level skew clock outputs Clock input tolerant Pinout function compatible with QS5807 QS532807 on-chip resistors noise Input hysteresis better noise margin Guaranteed skew 0.35ns same transition 0.6ns opposite transition 0.75ns different devices Industrial temperature range Available QSOP SOIC (SO)
QS53807 QS532807 clock driver/buffer circuits used clock buffering schemes where skew parameter. QS53806 offers non-inverting outputs. Designed QSI's proprietary QCMOS process, these devices provide propagation delay buffering with on-chip skew 0.35ns same-transition, same-bank signals. QS532807 on-chip series termination resistors lower noise clock signals. series resistor versions recommended driving unterminated lines with capacitive loading other noise sensitive clock distribution circuits. These clock buffer products designed high-performance workstations, embedded personal computing systems. Several devices used parallel scattered throughout system guaranteed skew, system-wide clock distribution networks. Application Note AN-21 more information lowskew clock buffers.
Figure Functional Block Diagram
MDSC-00025-04 January 1999 QUALITY SEMICONDUCTOR, INC.
QS53807, QS532807 Figure Configurations (All Pins View)
QSOP, SOIC
Table Description
Name Description Clock Input Clock Outputs
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V 4.6V Output Voltage VOUT -0.5V 0.5V Input Voltage -0.5V 7.0V Input Voltage (for pulse width 20ns) -3.0V Input Diode Current with -20mA Output Current Max. Sink Current/Pin 120mA Maximum Power Dissipation TA=85°C, QSOP 0.82 watts SOIC 0.75 watts TSTG Storage Temperature -65° 150°C
Note: Stresses greater than those listed under absolute maximum ratings cause permanent damage devices that result functional reliability type failures.
Table Capacitance
25°C, 1MHz, QSOP Pins SOIC Unit
Note: Capacitance characterized tested.
QUALITY SEMICONDUCTOR, INC.
MDSC-00025-04 January 1999
QS53807, QS532807 Table Electrical Characteristics Over Operating Range
Industrial: -40°C 85°C, 0.3V Symbol Parameter Input HIGH Voltage Input Voltage Clamp Diode Voltage Output HIGH Voltage Output Voltage QS53807 Output Voltage QS532807 IODH IODL ROUT Input Leakage Current Short Circuit Current(2,3) Output HIGH Current Output Current Input Hysteresis Output Resistance(4) QS532807 Test Conditions Guaranteed Logic HIGH Inputs Guaranteed Logic Inputs Min., -18mA(3) Min., -100µA Min., -8mA Min., 100µA Min., 16mA Min., 24mA Min., 100µA Min., Min., 5.5V Max., VOUT 3.3V, VIL, 1.5V -0.5 VCC-0.2 Typ(1) -0.7 -1.2 Unit
3.3V, VIL, 1.5V VTLH VTHL Inputs Min.
-195
-200
Notes: Typical values indicate 3.3V 25°C. more than output should used test this high power condition, duration second. Guaranteed design production tested. Output resistance represents total output impedence logic device includes added series termination resistance.
MDSC-00025-04 January 1999
QUALITY SEMICONDUCTOR, INC.
QS53807, QS532807 Table Power Supply Characteristics
Symbol Parameter ICCD Quiescent Power Supply Current Supply Current Input HIGH Dynamic Power Supply Current Output(2) Total Power Supply(2,4) Current Test Conditions(1) Max.,VIN Max., 3.0V Input toggling duty cycle Max., outputs enabled Max., Input duty cycle, 10MHz Max., Input duty cycle, 2.5MHz Typ(3) 0.01 Unit
Notes: conditions shown Min. Max., appropriate values specified under specifications. Guaranteed production tested. CL=0pF. Typical values reference only. Conditions 3.3V 25°C. (ICC)(DH)(NT) ICCD (fO)(NO) where: Input duty cycle Number HIGH inputs (one) Output Frequency Number outputs (ten)
Table Switching Characteristics Over Operating Range
Industrial: -40°C 85°C, 0.3V QS53807, CLOAD 50pF, RLOAD 500. QS532807, CLOAD 50pF resistor) Symbol Description(1) tSK(01) tSK(p) Skew between outputs same transition Pulse Skew: Skew between opposite transitions same output (tPHL-tPLH) Part-to-part skew(2) Propagation Delay(3) Output Rise Time, 0.8V 2.0V Output Fall Time, 2.0V 0.8V QS53807 QS532807 QS53807 QS532807 QS53807 QS532807
0.35 0.35
Unit
tSK(t) tPLH tPHL
0.75
Notes: Skew parameters guaranteed production tested. Test Circuit Waveforms. Minimums guaranteed tested. tSK(t) only applies devices same transition, part type, temperature, power supply voltage, loading, package speed grade. propagation delay range indicated Min. Max. specifications results from process environmental variables. These propagation delay limits imply skew.
QUALITY SEMICONDUCTOR, INC.
MDSC-00025-04 January 1999
QS53807, QS532807 Figure Test Circuits Waveforms
Pulse Generator VOUT
50pF
(53807 only)
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
Test Circuit
INPUT tPLH OUPUT tPHL 2.0V 1.5V 0.8V
OUPUT
1.5V
INPUT
tPLH
tPHL
1.5V
1.5V
tSK(p) tPHL tPLH
Propagation Delay
Pulse Skew tSK(p)
INPUT
tPLH1 tPHL1 tSK(01) tSK(01) tPLH2 tPHL2
1.5V 1.5V 1.5V
INPUT tPLH1 PART OUTPUT tSK(t) tPHL1 1.5V 1.5V tSK(t) PART OUTPUT 1.5V tPLH2 tPHL2
OUPUT
OUPUT
tSK(O1) |tPLH2 tPLH1| |tPHL2 tPHL1|
tSK(t) |tPLH2 tPLH1| |tPHL2 tPHL1|
Output Skew tSK(01)
Part-to-Part Skew tSK(t)
MDSC-00025-04 January 1999
QUALITY SEMICONDUCTOR, INC.
QS53807, QS532807
Figure Ordering Information Example:
QS532807AClock Management Product Prefix (QS5) 3.3V devices Resistor Option (blank) Part Number Package (150 wide QSOP) (300 wide SOIC)
Speed (blank)
QUALITY SEMICONDUCTOR, INC.
MDSC-00025-04 January 1999

QUALITY SEMICONDUCTOR, INC. Guaranteed Skew 3.3V CMOS Clock Drive

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