QUALITY SEMICONDUCTOR, INC. High-Speed CMOS 8-Bit Buffer/Line Dri
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QS5244T
QUALITY SEMICONDUCTOR, INC.
High-Speed CMOS 8-Bit Buffer/Line Driver
DESCRIPTION
QS5244T
0.5ns on-chip skew (same transition) 1.2ns pulse skew (opposite transition) '244 compatible pinout function 1.5ns skew between devices Ground bounce controlled outputs CMOS power levels: <8mW static voltage swing 0V~3.5V 4.1ns propagation delay Undershoot clamp diodes inputs Available SOIC, QSOP
QS5244T 8-bit buffer/line driver with threestate outputs that ideal driving high-capacitance loads memory address data buses. QS5244T designed minimize skew between outputs. inputs have clamp diodes undershoot noise suppression. outputs have ground bounce suppression outputs will load active when removed from device. more information, Application Note AN-01.
Figure Functional Block Diagram
2G(19)
1G(1)
1Y1(18) 1Y2(16) 1Y3(14) 1Y4(12)
1A1(2) 1A2(4) 1A3(6) 1A4(8)
2A1(11) 2A2(13) 2A3(15) 2A4(17)
2Y1(9) 2Y2(7) 2Y3(5) 2Y4(3)
MDSL-00054-03 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5244T Figure Configurations (All Pins View)
SOIC, QSOP
Table Description
Name xA4-xA1 xY4-xY1 Description Data Inputs Data Outputs Three State Output Enable, Bank Output Enable, Bank
Table Function Table
1G/2G
Input
Output
Table Absolute Maximum Ratings
Supply Voltage Ground -0.5V +7.0V Output Voltage VOUT -0.5V +7.0V Input Voltage -0.5V +7.0V Input Voltage (for pulse width 20ns) -3.0V Input Diode Current with -20mA Output Diode Current with VOUT -50mA Output Current Max. sink current/pin 120mA Maximum Power Dissipation 85oC, QSOP 0.80 watts SOIC 0.75 watts TSTG Storage Temperature -65° +150°C
Table Capacitance
25°C, 1MHz, VOUT Pins 1,19 2-9, 11-18 SOIC QSOP Unit
Note: Capacitance characterized tested.
QUALITY SEMICONDUCTOR, INC.
MDSL-00054-03 NOVEMBER 1997
QS5244T Table Electrical Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V Symbol Parameter Input HIGH Voltage Input Voltage Input Hysteresis Input Current Input HIGH Off-State Output Current (Hi-Z) Short Circuit Current(2,3) Input Clamp Voltage(3) Output HIGH Voltage Output Voltage
Test Conditions Logic HIGH Inputs Logic Inputs VTLH VTHL Inputs Max., Max., VOUT VOUT Max., VOUT Min., -18mA Min. Min. -15mA 64mA
Typ(1) -0.7
-225 -1.2 0.55
Unit
Notes: Typical values indicate 5.0V 25°C. more than output should shorted duration second. These parameters guaranteed design tested.
Table Power Supply Characteristics
Symbol Parameter
Quiescent Power Supply Current
Test Conditions(1) Max., Freq 0.2V VCC-0.2V Max., 3.4V, Freq Max., Outputs open enabled toggling duty cycle Other inputs
Unit
Supply Current Input HIGH(2)
QCCD
Supply Current Output(3,4)
Notes: conditions shown, appropriate values specified under specifications. driven input (VIN 3.4V). flip-flops, QCCD measured switching data input pins that output changes every clock cycle. This measurement device power consumption only does include power drive load capacitance tester capacitance. This parameter guaranteed design tested. computed using above parameters explained Technical Overview section.
MDSL-00054-03 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
QS5244T Table Switching Characteristics Over Operating Range
Industrial: -40°C 85°C, 5.0V CLOAD 50pF, RLOAD unless otherwise noted.
QS5244T Symbol tPHL tPLH tPZH tPZL tPHZ tPLZ tSK(O2) tSK(p) tSK(t) Description
Unit
Propagation Delay Output Enable Time Output Disable Time(2) Skew between outputs (same transition)(2) Skew between opposite transition same output(2) Skew between outputs different devices(2,3) Output rise/fall time(2)
Notes: Test Circuit Waveforms. Minimums guaranteed tested. This parameter guaranteed design tested. tSK(t) applies same VCC, temperature, package.
QUALITY SEMICONDUCTOR, INC.
MDSL-00054-03 NOVEMBER 1997
QS5244T Figure Test Circuits Waveforms
Parameter Tested
tPLZ, tPZL
Others Pulse Generator VOUT
Switch Position Closed Open
7.0V
50pF
Coax Oscilloscope
Pulse generator pulses: 1.0MHz; 2.5ns; 2.5ns
INPUT tPLH OUTPUT tPHL 2.0V 1.5V 0.8V
OUTPUT INPUT tPHL 1.5V tPLH 1.5V
1.5V
tSK(P) tPHL tPLH
Propagation Delay
Pulse Skew tSK(p)
tPHL1
ENABLE CONTROL INPUT
DISABLE
1.5V
INPUT
1.5V
OUTPUT NORMALLY
OUTPUT NORMALLY HIGH
SWITCH CLOSED
tPZL 1.5V tPZH 1.5V
tPLZ 3.5V
tPLH1
OUTPUT
tSK(02)
1.5V
tSK(02) 1.5V tPLH2 tPHL2
0.3V tPHZ 0.3V
SWITCH OPEN
OUTPUT
tSK(02) |tPLHB tPLHA| |tPHLB tPHLA|
Enable Disable Times
Ouput Skew tSK(O2)
INPUT
tPLH1 tPHL1
1.5V
PART OUTPUT
1.5V
tSK(t) tSK(t) 1.5V tPLH2 tPHL2
PART OUTPUT
tSK(T) tPLH2 tPLH1
tPHL2 tPHL1
Part-to-Part Skew tSK(t)
MDSL-00054-03 NOVEMBER 1997
QUALITY SEMICONDUCTOR, INC.
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