Software Programmable Gain Amplifier AD526 CONFIGURATION APP

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Software Programmable Gain Amplifier AD526 CONFIGURATION APP

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FEATURES Digitally Programmable Binary Gains from Two-Chip Cascade Mode Achieves Binary Gain from Gain Error: 0.01% max, Gain Grade) 0.02% max, Gain Grade) ppm/ Drift Over Temperature Fast Settling Time Signal Change: 0.01% (Gain Gain Change: 0.01% (Gain Nonlinearity: 0.005% Grade) Excellent Accuracy: Offset Voltage: Grade) Offset Voltage Drift: Grade) Compatible Digital Inputs PRODUCT DESCRIPTION
Software Programmable Gain Amplifier AD526
CONFIGURATION
APPLICATION HIGHLIGHTS
AD526 single-ended, monolithic software programmable gain amplifier (SPGA) that provides gains complete, including amplifier, resistor network TTL-compatible latched inputs, requires external components. gain error nonlinearity make AD526 ideal precision instrumentation applications requiring programmable gain. small signal bandwidth gain addition, AD526 provides excellent precision. FETinput stage results bias current guaranteed maximum input offset voltage grade) gain error (0.01%, grade) accomplished using Analog Devices' laser trimming technology. provide flexibility system designer, AD526 operated either latched transparent mode. force/sense configuration preserves accuracy when output connected remote impedance loads. AD526 offered commercial (0°C +70°C) grade, three industrial grades, which specified from -40°C +85°C. grade specified from -55°C +125°C. military version available processed MILSTD 883B, grade supplied 16-pin plastic DIP, other grades offered 16-pin hermetic sidebrazed ceramic DIP.
Dynamic Range Extension Systems: single AD526 conjunction with 12-bit provide dynamic range systems. Gain Ranging Pre-Amps: AD526 offers complete digital gain control with precise gains binary steps from Additional gains possible cascading AD526s.
ORDERING GUIDE
Model AD526JN AD526AD AD526BD AD526CD AD526SD/883B 5962-9089401MEA* Temperature Range Commercial Industrial Industrial Industrial Military Package Description 16-Pin Plastic 16-Pin Cerdip 16-Pin Cerdip 16-Pin Cerdip 16-Pin Cerdip Package Option N-16 D-16 D-16 D-16 D-16
*Refer official DESC drawing tested specifications.
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Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD526-SPECIFICATIONS
unless otherwise noted)
AD526B/S AD526C
Model GAIN Gain Range (Digitally Programmable) Gain Error Gain Gain Gain Gain Gain Gain Error Drift Over Temperature Gain Error (TMIN TMAX) Gain Gain Gain Gain Gain Nonlinearity Gain Gain Gain Gain Gain Nonlinearity (TMIN TMAX) Gain Gain Gain Gain Gain VOLTAGE OFFSET, GAINS Input Offset Voltage Input Offset Voltage Drift Over Temperature Input Offset Voltage TMIN TMAX Input Offset Voltage Supply 10%) INPUT BIAS CURRENT Over Input Voltage Range ANALOG INPUT CHARACTERISTICS Voltage Range (Linear Operation) Capacitance RATED OUTPUT Voltage Current (VOUT Short-Circuit Current Output Resistance Load Capacitance (For Stable Operation) NOISE, GAINS Voltage Noise, Voltage Noise Density,
AD526J
AD526A
Units
0.05 0.05 0.10 0.15 0.15
0.02 0.03 0.03 0.07 0.07
0.01 0.02 0.02 0.04 0.04
0.01 0.01 0.01 0.02 0.02
0.06 0.06 0.12 0.17 0.17 0.005 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001
0.03 0.04 0.04 0.08 0.08 0.005 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001
0.02 0.03 0.03 0.05 0.05 0.005 0.001 0.001 0.001 0.001 0.01 0.001 0.001 0.001 0.001
0.015 0.015 0.015 0.03 0.03 0.0035 0.001 0.001 0.001 0.001 0.007 0.001 0.001 0.001 0.001
ppm/°C ppm/°C ppm/°C ppm/°C ppm/°C µV/°C
0.25
0.25
0.25
0.002
0.002
0.002
0.002
nVHz nVHz nVHz nVHz
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AD526
Model DYNAMIC RESPONSE Bandwidth (Small Signal) Signal Settling Time 0.01% (VOUT Full Power Bandwidth Slew Rate DIGITAL INPUTS (TMIN TMAX) Input Current Logic Logic TIMING1 TEMPERATURE RANGE Specified Performance Storage POWER SUPPLY Operating Range Positive Supply Current Negative Supply Current PACKAGE OPTIONS Plastic (N-16) Ceramic (D-16) AD526J AD526A AD526B/S AD526C Units
0.65 0.35 0.10 0.35
0.65 0.35 0.10 0.35
0.65 0.35 0.10 0.35
0.65 0.35 0.10 0.35
V/µs V/µs
AD526JN +125 16.5
+150 16.5
-40/-55
+85/+125 +150 16.5 +150 16.5
AD526AD
AD526BD AD526SD AD526SD/883B
AD526CD
NOTES Refer Figure definitions. Full Scale Range Referred Input. Specifications subject change without notice. Specifications shown boldface tested production units final electrical test. specifications guaranteed, although only those shown boldface tested production units.
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AD526-Typical Characteristics
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AD526
*For Settling Time Traces, 0.01% Vertical Division
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AD526
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AD526
THEORY OPERATION
AD526 complete software programmable gain amplifier (SPGA) implemented monolithically with drift-trimmed BiFET amplifier, laser wafer trimmed resistor network, JFET analog switches compatible gain code latches. particular gain selected applying appropriate gain code (see Table control logic. control logic turns JFET switch that connects correct gain network inverting input amplifier; unselected JFET gain switches (open). "on" resistance gain switches causes negligible gain error since only amplifier's input bias current, which less than actually flows through these switches. AD526 capable storing gain code, (latched mode), under direction control inputs Alternatively, AD526 respond directly gain code changes control inputs tied (transparent mode). gains fraction frequency compensation capacitance Figure automatically switched circuit. This increases amplifier's bandwidth improves signal settling time slew rate.
After gain codes changed, AD526's output voltage typically requires settle within 0.01% final value. Figures show performance AD526 positive gain code changes.
Figure Transparent Mode
LATCHED MODE OPERATION
latched mode operation shown Figure When either logic "1," gain code (A0, signals latched into registers held until both return "0." Unused inputs should tied ground inputs functionally electrically equivalent.
Figure Simplified Schematic AD526
TRANSPARENT MODE OPERATION
transparent mode operation, AD526 will respond directly level changes gain code inputs (A0, tied high both allowed float low.
Figure Latched Mode
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AD526
TIMING CONTROL Table Logic Input Truth Table DIGITAL FEEDTHROUGH
Gain Code
Control
Condition Gain Previous State
Condition Latched Transparent Transparent Transparent Transparent Transparent Transparent Latched Latched Latched Latched Latched Latched
With either both held high, AD526 gain state will remain constant regardless transitions inputs. However, high speed logic transitions will unavoidably feed through analog circuitry within AD526 causing spikes occur signal output. This feedthrough effect completely eliminated operating AD526 transparent mode latching gain code external bank latches (Figure 36). operate AD526 using serial inputs, configuration shown Figure used with 74LS174 replaced serial-in/parallel-out latch, such 54LS594.
GROUNDING BYPASSING
Proper signal grounding techniques must applied board layout that specified performance levels precision data acquisition components, such AD526, degraded. shown Figure logic signal grounds should separate. connecting signal source ground locally AD526 analog ground Pins gain accuracy AD526 maintained. This ground connection should corrupted currents associated with other elements within system. Utilizing force sense outputs AD526, shown Figure avoids signal drops along etch runs impedance loads.
NOTE: Don't Care.
specifications page combination with Figure give timing requirements loading gain codes.
Figure AD526 Timing
Figure Grounding Bypassing
Figure Using External Latch Minimize Digital Feedthrough
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AD526
Figure Cascaded Operation
Table Logic Table Figure OUTPUT CURRENT BOOSTER
VOUT/VIN
OFFSET NULLING
AD526 rated full output voltage swing into some applications, need exists drive more current into heavier loads. shown Figure high current booster connected "inside loop" SPGA provide required current boost without significantly degrading overall performance. Nonlinearities, offset gain inaccuracies buffer minimized loop gain AD526 output amplifier.
Input voltage offset nulling AD526 best accomplished gain since referred-to-input (RTI) offset amplified most this gain therefore most easily trimmed. resulting trimmed value voltage offset typically varies less than across gain ranges. Note that input current AD526 minimizes voltage offsets source resistance.
Figure Current Output Boosting
CASCADED OPERATION
Figure Offset Voltage Null Circuit
cascade AD526s used achieve binarily weighted gains from 256. gains from needed, additional components required. This accomplished using shown Figure When low, AD526 held unity gain stage independent other gain code values.
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AD526
OFFSET NULLING WITH CONVERTER FLOATING-POINT CONVERSION
Figure shows AD526 with offset nulling accomplished with 8-bit converter (AD7524) circuit instead potentiometer shown Figure calibration procedure same before except that instead adjusting potentiometer, converter corrects offset error. This calibration circuit number benefits addition eliminating trimpot. most significant benefit that calibration under control microprocessor therefore implemented part autocalibration scheme. Secondly, switches used hold 8-bit word after value been determined. Figure offset null sensitivity, gain adjustment, which guarantees accuracy 16-bit performance level.
High resolution converters used systems obtain high accuracy, improve system resolution increase dynamic range. There number high resolution converters available with throughput rates 66.6 that purchased single component solution; however order achieve higher throughput rates, alternative conversion techniques must employed. floating point converter improve both throughput rate dynamic range system. floating point converter (Figure 42), output data presented 16-bit word, lower bits from converter form mantissa upper bits from digital signal used gain form exponent. AD526 programmable gain amplifier conjunction with comparator circuit scales input signal range between half scale full scale maximum usable resolution. converter diagrammed Figure consists pair AD585 sample/hold amplifiers, flash converter, five-range programmable gain amplifier (the AD526) fast 12-bit converter (the AD7572). floating-point converter achieves high throughput rate overlapping acquisition time first sample/hold amplifier settling time AD526 with conversion time converter. first sample/hold amplifier holds signal flash autoranger, which determines which binary quantum input falls within, relative full scale. Once AD526 settled appropriate level, then second sample/hold amplifier into hold which holds amplified signal while AD7572 perform conversion routine. acquisition time AD585 conversion time AD7572 total kHz. This performance relies fast settling characteristics AD526 after flash autoranging (comparator) circuit quantizes input signal. 16-bit register holds 3-bit output from flash autoranger 12-bit output AD7572. converter Figure dynamic range dynamic range converter ratio full-scale input range value. With floating-point converter smallest value corresponds monolithic converter divided maximum gain PGA. floating point converter full-scale range maximum gain from AD526 12-bit converter; this produces: ([FSR/2N]/Gain) V/4096]/16) dynamic range based ratio full-scale input range LSB; dynamic range V/76
Figure Offset Nulling Using
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AD526
Figure Floating-Point Converter
HIGH ACCURACY CONVERTERS
Very high accuracy high resolution floating-point converters achieved incorporation offset gain calibration routines. There techniques commonly used calibration, hardware circuit shown Figure and/or software routine. this application microprocessor functioning autoranging circuit, requiring software overhead; therefore, hardware calibration technique applied which reduces software burden. software used gain AD526. operation signal converted, AD574 equal logical gain increased binary steps, maximum gain. This maximizes full-scale range conversion process insures wide dynamic range. calibration technique uses point correction, offset gain. hardware simplified programmable magnitude comparators, 74ALS528s, which "burned" particular code. order prevent under
over range hunting during calibration process, reference offset gain codes should different from endpoint codes. calibration cycle consists selecting whether gain offset calibrated then selecting appropriate multiplexer channel apply reference voltage signal channel. Once operation been initiated, counter, 74ALS869, drives converter linear fashion providing small correction voltage either gain offset trim point AD574. output converter then compared value preset 74ALS528 determine match. Once match detected, 74ALS528 produces going pulse which stops counter. code converter latched until next calibration cycle. Calibration cycles under control microprocessor this application should implemented only during periods converter inactivity.
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AD526
Figure High Accuracy Converter
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
16-Pin Plastic Package (N-16)
16-Pin Sided-Brazed Ceramic Package (D-16)
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PRINTED U.S.A.
C1103a-9-2/88

Software Programmable Gain Amplifier AD526 CONFIGURATION APP

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