DISTINCTIVE CHARACTERISTICS Microcontrollers E86family embedded p
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Single-Chip, Low-Power, PC/AT-Compatible Microcontrollers
DISTINCTIVE CHARACTERISTICS Microcontrollers
E86family embedded processors Standard PC/AT system logic
(PICs, DMACs, timer, RTC) DOS, ROM-DOS, Windows, industrystandard BIOS support Leverages benefits desktop computing environment embedded price points
Bidirectional parallel port with Enhanced
Offers improved time-to-market, software migration, field-proven development tools
Highly integrated single-chip with complete
Parallel Port (EPP) mode
16550-compatible UART Infrared port wireless communication
common peripherals Accelerates time-to-market with simplified hardware Low-power 0.35-micron process technology Single chip delivers smallest system form factor 33-MHz, 66-MHz, 100-MHz operating frequencies
Am486® core
Standard high-speed
Keyboard interface
Matrix keyboard support with rows columns SCP-emulation mode PC/AT keyboard support
Robust Microsoft® Windows® compatible 8-Kbyte write-back cache enhanced performance Fully static design with System Management Mode (SMM) power savings
Comprehensive power management unit
Microcontroller Only
microcontroller includes following additional features designed specifically mobile computing applications. microcontroller does include these features.
Dual Card (PCMCIA Version 2.1) controller
Seven modes operation allow fine-tuning power requirements maximum battery life Provides superset features
Glueless burst-mode
supports 16-bit data End-user (after-market) system expansion ExCA-compliant, 82365-register compatible Leverages off-the-shelf card socket services Supports transfers between cards system DRAM
graphics controller
ROM/Flash memory/SRAM interface Reduces system cost allowing mask Flash memory same time with three ROM/ Flash memory/SRAM chip selects
Glueless DRAM controller
Allows mixed DRAM types per-bank basis reduce system cost
VESA Local (VL) interface
Supports monochrome 4-bit color Super Twisted Nematic (STN) LCDs Unified Memory Architecture (UMA) eliminates separate video memory
Reduces time-to-market with wide variety offthe-shelf companion chips
Copyright 1998 Advanced Micro Devices, Inc. Rights Reserved. Advanced Micro Devices, Inc. ("AMD") reserves right discontinue products, make changes products, time without notice. information this publication believed accurate time publication, makes representations warranties with respect accuracy completeness contents this publication information contained herein, reserves right make changes time, without notice. disclaims responsibility consequences resulting from information included this publication. This publication neither states implies representations warranties kind, including limited implied warranty merchantability fitness particular purpose. AMD's products designed, intended, authorized warranted components systems intended surgical implant into body, other applications intended support sustain life, other application which failure AMD's product could create situation where personal injury, death, severe property environmental damage occur. assumes liability whatsoever claims associated with Publication# 21028 Rev: Amendment/0 sale (including engineering samples) products except provided AMD's Terms Conditions Issue Date: December 1998 Sale such product.
GENERAL DESCRIPTION
microcontrollers among latest series E86family microcontrollers, which integrate proven cores with comprehensive on-chip peripherals 0.35-micron process. microcontrollers combine 32-bit, low-voltage Am486 with complete PC/AT-compatible peripherals, along with power management features required battery operation. Leveraging benefits desktop computing environment, microcontrollers integrate common logic functionality associated with PC/AT computing system into single device, eliminating need multiple peripheral chips. Fully integrated PC/AT-compatible peripherals include 8259A-compatible programmable interrupt controllers (PICs), 8237A-compatible controllers, 8254-compatible timer, 16550 UART, IrDA controller, VL-bus controllers, real-time clock (RTC), Enhanced Parallel Port (EPP) mode parallel port. With low-voltage Am486® core ultra-small form factor, microcontroller highly optimized mobile computing applications. microcontroller targeted specifically embedded systems. feature comparison microcontrollers shown Table page microcontrollers industry-standard microprocessor instruction set. software written architecture family compatible with microcontrollers. microcontrollers based fully static design include advanced power management unit. Operating voltages V-3.3 with 5-V-tolerant pads. Orderable both 33-MHz, 66-MHz, 100-MHz peak processor speeds, product available ultra-small ball grid array (BGA) package.
ORDERING INFORMATION
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
ELANSC400 TEMPERATURE RANGE Commercial MHz: TCASE +95°C MHz: TCASE +85°C Industrial MHz, TCASE 40°C +95°C PACKAGE TYPE 292-pin (Ball Grid Array) SPEED OPTION -100 DEVICE NUMBER/DESCRIPTION microcontroller microcontroller Valid Combinations ELANSC400-33 ELANSC400-66 ELANSC400-100 ELANSC410-33 ELANSC410-66 ELANSC410-100 Valid Combinations
Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Microcontrollers Data Sheet
Table
Product Microcontrollers
Am486 8-Kbyte Write-Back Mbyte Mbyte ROM-mappable 16550-compatible Am486 8-Kbyte Write-Back Mbyte Mbyte ROM-mappable 16550-compatible 2.7-3.3
Feature Core Cache System management mode (SMM) Floating-point unit Data Interface mastering VESA Local mastering Power Management Mode timers Activity detection SMI/NMI generation Battery monitoring On-Chip Interface Width Size (total space) chip selects Burst-mode support Support SRAM address space On-Chip DRAM Controller Banks Width Size (total banks) support Support SRAM main memory Integrated PC/AT-Compatible Peripherals Programmable timer (8254-compatible) Real-time clock (146818A-compatible) Port Port registers Cascaded Controllers (8237A) Width Total number channels External channels Cascaded Interrupt Controllers (8259) External signals Bidirectional Parallel Port with Mode Serial Port (UART) Keyboard Interface Support external 8042 interface Matrix scanned with emulation General-Purpose Input/Output Signals Infrared (IrDA) Port Card Controller Sockets PCMCIA 2.1-compliant 82365-compatible Graphics Controller Programmable clock frequency Unified memory architecture (UMA) JTAG Support Count Package VCC: core On-chip peripheral logic tolerance (designated pins) Processor Clock Rate
2.7-3.3
Microcontrollers Data Sheet
BLOCK MICROCONTROLLER
Microcontroller Addr Data Am486® Memory Management Unit
System Address
Address Decoder Addr Dual Controllers 8237 Data Steering Data
Power GPIOs Management Unit Clock Clock Generation Real-Time Clock Boundary Scan Port Logic Timer 8254 Dual Interrupt Controllers 8259 Socket Ctrl GPIOs Parallel Port Card Socket Card Controller GPIOs Parallel Port UART 16550 Infrared Port GPIOs GPIOs Internal
Graphics Controller Graphics Local Controller Local Controller
32-kHz Crystal
System Arbiter GPIOs
DRAM Control Memory Controller Control DRAM Control Keyboard Rows GPIOs Keyboard Rows Columns Keyboard Control Keyboard Rows Control Control GPIOs
Keyboard Interface: Matrix/XT/SCP
Serial Port
Controller
Infrared
Microcontrollers Data Sheet
BLOCK MICROCONTROLLER
Microcontroller Addr Data Am486® Memory Management Unit
System Address
Address Decoder Addr Dual Controllers 8237 Data Steering Data
Power GPIOs Management Unit Clock Clock Generation Real-Time Clock Boundary Scan Port Logic Timer 8254 Dual Interrupt Controllers 8259 GPIOs Parallel Port Parallel Port Serial Port UART 16550 Infrared Port GPIOs Memory Controller Internal
32-kHz Crystal
Local Controller
Local Controller
System Arbiter GPIOs DRAM Control Control DRAM Control Keyboard Rows GPIOs Keyboard Interface: Matrix/XT/SCP GPIOs Keyboard Rows Columns Keyboard Control Keyboard Rows Control Control GPIOs
Controller GPIOs
Infrared
Microcontrollers Data Sheet
LOGIC MICROCONTROLLER
LCDD7 [VL_BE3] LCDD6 [VL_LDEV] LCDD5 [VL_D/C] LCDD4 [VL_LRDY] LCDD3 [VL_M/IO] LCDD2 [VL_W/R] CASL/H1-CASL/H0 RAS1-RAS0 MA11-MA5 {CFG3} {CFG2} {CFG1} {CFG0} D15-D0 SD15-SD0 [D31-D16] SA25-SA0 ROMCS1-ROMCS0 ROMRD ROMWR MEMR MEMW RSTDRV MCEL_A [[BNDSCN_TCK]] MCEH_A [[BNDSCN_TMS]] RST_A [[BNDSCN_TDI]] REG_A [[BNDSCN_TDO]]
Graphics Controller VESA Local
LCDD1 [VL_ADS] LCDD0 [VL_RST] [VL_BE2] [VL_BE1] [VL_BE0] [VL_LCLK] LVEE [VL_BRDY] LVDD [VL_BLAST] DTR, RTS, SOUT
DRAM Interface Feature Configuration Pins
DRAM, ROM, Card Data ROM, ISA, Card Address ROM/Flash Memory Control Card Command Command Reset
8-Pin Serial Port Infrared Interface Power Management Interface GPIOs GPIO/External Buffer Control
CTS, DCD, RIN, SIROUT SIRIN ACIN BL2-BL1 [CLK_IO] GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16]
GPIO/ISA Interface
GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 [PCMA_VCC] GPIO_CS14 [PCMA_VPP1] GPIO15 [PCMA_VPP2]
Microcontroller
CD_A RDY_A BVD1_A, BVD2_A WP_A WAIT_AB ICDIR GPIO31 [STRB] [MCEL_B] GPIO30 [AFDT] [MCEH_B] GPIO29 [SLCTIN] [RST_B] GPIO28 [INIT] [REG_B] GPIO27 [ERROR] [CD_B] GPIO26 [PE] [RDY_B] GPIO25 [ACK] [BVD1_B] GPIO24 [BUSY] [BVD2_B] GPIO23 [SLCT] [WP_B] GPIO22 [PPOEN] GPIO21 [PPDWE] 32KXTAL1, 32KXTAL2 LF_INT, LF_LS LF_VID, LF_HS RESET VCC_RTC BBATSEN
Dedicated Single Slot Card Boundary Scan Interface
GPIO/PC Card Power Control
GPIO16 [PCMB_VCC] GPIO17 [PCMB_VPP1] GPIO18 [PCMB_VPP2] GPIO19 [LBL2] GPIO20 [CD_A2] KBD_COL7 KBD_COL6-2 PIRQ7-3 COL1-0 [XT_CLK/DATA] SUS_RES KBD_ROW14 KBD_ROW13 [[R32BFOE]] KBD_ROW12 [MCS16]
Parallel Port Second Card GPIOs
Scan Keyboard Columns/IRQs/XT Keyboard Interface
Scan Keyboard Rows/ISA Interface
KBD_ROW11 [SBHE] KBD_ROW10 [BALE] KBD_ROW9 [PIRQ2] KBD_ROW8 [PDRQ1] KBD_ROW7 [PDACK1] KBD_ROW6 [MA12] KBD_ROW5 [RAS3]
32-kHz Crystal Loop Filters Reset
Scan Keyboard Rows/DRAM Interface
KBD_ROW4 [RAS2] KBD_ROW3 [CASH3] KBD_ROW2 [CASH2] KBD_ROW1 [CASL3] BNDSCN_EN KBD_ROW0 [CASL2] SPKR
Speaker Boundary Scan Enable
Notes:
=Two functions available same time. Function during hardware reset. Alternative function selected firmware configuration. Alternate function selected hardware configuration state power-on reset. This does apply [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], [[BNDSCN_TDO]]. These alternate functions enabled BNDSCN_EN signal.
Microcontrollers Data Sheet
LOGIC MICROCONTROLLER
VL_BE3 VL_LDEV VL_D/C VL_LRDY VL_M/IO VL_W/R CASL/H1-CASL/H0 RAS1-RAS0 MA11-MA5 {CFG3} {CFG1} {CFG0} D15-D0 SD15-SD0 [D31-D16] SA25-SA0
VESA Local
VL_ADS VL_RST VL_BE2 VL_BE1 VL_BE0 VL_LCLK VL_BRDY VL_BLAST DTR, RTS, SOUT
DRAM Interface Feature Configuration Pins
DRAM, ROM, Data ROM, Address ROM/Flash Memory Control
8-Pin Serial Port Infrared Interface Power Management Interface GPIOs GPIO/External Buffer Control
CTS, DCD, RIN, SIROUT SIRIN ACIN BL2-BL1 [CLK_IO] GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16]
ROMCS1-ROMCS0 ROMRD ROMWR MEMR MEMW RSTDRV
Command Reset
[[BNDSCN_TCK]] [[BNDSCN_TMS]]
GPIO/ISA Interface
GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 GPIO_CS14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 [LBL2] GPIO20
Microcontroller
[[BNDSCN_TDI]] [[BNDSCN_TDO]]
Boundary Scan Interface
GPIO31 [STRB] GPIO30 [AFDT] GPIO29 [SLCTIN] GPIO28 [INIT] GPIO27 [ERROR] GPIO26 [PE] GPIO25 [ACK] GPIO24 [BUSY] GPIO23 [SLCT] GPIO22 [PPOEN]
Parallel Port GPIOs
GPIO/ Power Control
Scan Keyboard Columns/IRQs/XT Keyboard Interface
KBD_COL7 KBD_COL6-2 PIRQ7-3 COL1-0 [XT_CLK/DATA] SUS_RES KBD_ROW14 KBD_ROW13 [[R32BFOE]] KBD_ROW12 [MCS16]
GPIO21 [PPDWE]
32KXTAL1, 32KXTAL2 LF_INT, LF_LS LF_HS
32-kHz Crystal Loop Filters
Scan Keyboard Rows/ISA Interface
KBD_ROW11 [SBHE] KBD_ROW10 [BALE] KBD_ROW9 [PIRQ2] KBD_ROW8 [PDRQ1] KBD_ROW7 [PDACK1] KBD_ROW6 [MA12] KBD_ROW5 [RAS3]
RESET
Reset
VCC_RTC BBATSEN
Scan Keyboard Rows/DRAM Interface
KBD_ROW4 [RAS2] KBD_ROW3 [CASH3] KBD_ROW2 [CASH2] KBD_ROW1 [CASL3] BNDSCN_EN SPKR
Speaker Boundary Scan Enable
KBD_ROW0 [CASL2] Notes: =Two functions available same time. Function during hardware reset. Alternative function selected firmware configuration. Alternate function selected hardware configuration state power-on reset. This does apply [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], [[BNDSCN_TDO]]. These functions enabled BNDSCN_EN signal.
Microcontrollers Data Sheet
TABLE CONTENTS
Distinctive Characteristics Microcontrollers Microcontroller Only General Description Block Microcontroller Block Microcontroller Logic Microcontroller Logic Microcontroller Related Products E86Family Devices Related Documents Microcontroller Evaluation Board Third-Party Development Support Products Customer Service Architectural Overview Low-Voltage Am486 Core Power Management Clock Generation ROM/Flash Memory Interface DRAM Controller Integrated Standard PC/AT Peripherals PC/AT Support Features Bidirectional Enhanced Parallel Port (EPP) Serial Port Keyboard Interfaces Programmable General-Purpose Inputs Outputs Infrared Port Wireless Communication Dual Card Controller Microcontroller Only) Graphics Controller CGA-Compatible Text Graphics Microcontroller Only) JTAG Test Features System Interfaces System Considerations Connection Microcontrollers Designations Naming Changes Microcontroller Designations (Pin Microcontroller Designations (Pin Microcontroller Designations (Pin Microcontroller Designations (Pin Microcontroller State Tables Characteristics Using State Tables Signal Descriptions Multiplexed Function Options Using Configuration Pins Select Functions. Clocking Clock Generation Integrated Peripheral Clock Sources 32-kHz Crystal Oscillator Loop Filters Intermediate Low-Speed PLLs Graphics Clock Microcontroller Only)
Microcontrollers Data Sheet
High-Speed Band Block Voltage Monitor Clock Specifications Absolute Maximum Ratings Operating Ranges Characteristics Over Commercial Industrial Operating Ranges Capacitance Typical Power Numbers Power Requirements Under Different Power Management Modes Derating Curves Switching Characteristics Waveforms Switching Waveforms Switching Test Waveforms Switching Characteristics over Commercial Industrial Operating Ranges Thermal Characteristics Physical Dimensions-BGA 292-Plastic Ball Grid Array
LIST FIGURES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Typical Mobile Terminal Design System Diagram with Microcontroller System Design with Microcontroller Clock Generation Block Diagram Clock Source Block Diagram 32-kHz Crystal Circuit 32-kHz Oscillator Circuit Intermediate Low-Speed PLLs Block Diagram Graphics Clock Block Diagram High-Speed Block Diagram Voltage Monitor Circuit Timing Diagram RTC-On Power-Down Sequence Enabling Timing Sequence 3.3-V Drive Type Rise Time 3.3-V Drive Type Fall Time 3.3-V Drive Type Rise Time 3.3-V Drive Type Fall Time 3.3-V Drive Type Rise Time 3.3-V Drive Type Fall Time 3.3-V Drive Type Rise Time 3.3-V Drive Type Fall Time 3.3-V Drive Type Rise Time 3.3-V Drive Type Fall Time Power-Up Timing Sequence Fast Mode 8-/16-/32-Bit ROM/Flash Memory Read Cycle Fast Mode Read Three Consecutive Bytes from 8-Bit ROM/Flash Memory Fast Mode 8-/16-/32-Bit Flash Memory Write Cycles Fast Mode 16-Bit Burst Read Cycles Fast Mode Burst Read from 32-Bit Burst Mode ROM/Flash Memory Normal Mode 8-/16-Bit ROM/Flash Memory Read Cycles Normal Mode 8-/16-Bit Flash Memory Write Cycles DRAM Page Read, Interleaved DRAM Page Write, Interleaved DRAM Page Miss Read, Interleaved
Microcontrollers Data Sheet
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
DRAM Page Read, Non-Interleaved DRAM Page Write, Non-Interleaved DRAM Page Miss Read, Non-Interleaved DRAM Page Read, Non-Interleaved DRAM Page Miss Read, Non-Interleaved DRAM CAS-Before-RAS Refresh DRAM Self-Refresh DRAM Slow Refresh 8-Bit Cycles 16-Bit Cycles Read Cycle Write Cycle VESA Local Cycles Parallel Port Write Cycle Parallel Port Read Cycle Decode (R/W), Address Decode Only Decode (R/W), Command Qualified Decode (R/W), GPIO_CSx 8042CS Timing Memory Decode (R/W), Address Decode Only Memory Decode (R/W), Command Qualified Card Attribute Memory Read Cycle Microcontroller Only) Card Attribute Memory Write Cycle Microcontroller Only) Card Common Memory Read Cycle Microcontroller Only) Card Common Memory Write Cycle Microcontroller Only) Card Read Cycle Card Write Cycle Card Read Cycle (Memory Read Write) Card Write Cycle (I/O Read Memory Write) Graphics Panel Interface Timing Microcontroller Only) Graphics Panel Power Sequencing Microcontroller Only)
LIST TABLES
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Product Microcontrollers Drive Output Description Type Abbreviations Power Type Abbreviations Power-Down Groups State Table-System Interface State Table-Memory Interface State Table-GPIOs/Parallel Port/PC Card Socket State Table-GPIOs/ISA State Table-GPIOs/System Data (SD) Buffer Control State Table-GPIOs State Table-Serial Port State Table-Infrared Interface State Table-Keyboard Interface State Table-PC Card Socket State Table-Graphics Controller/VESA Local Control State Table-Miscellaneous State Table-Power Ground Signal Description Table Multiplexed Configuration Options Pinstrap Buffer Options
Microcontrollers Data Sheet
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
CFG0 CFG1 Configuration CFG2 Configuration microcontroller only) CFG3 Configuration BNDSCN_EN Configuration Integrated Peripheral Clock Sources Frequency Selection Control Graphics Clock Loop-Filter Component Specification PLLs Analog (VCCA) Specification 32.768-kHz Crystal Characteristics Start-Up Time Specifications PLLs Jitter Specification Operating Voltage (Commercial Industrial) Power Estimates Power-On Reset Cycle ROM/Flash Memory Cycles DRAM Cycles Cycles VESA Local Cycles Parallel Port Cycles General-Purpose Input/Output Cycles Card Microcontroller Only Card Attribute Memory Read Function Microcontroller Only) Card Attribute Memory Write Function Microcontroller Only) Card Common Memory Read Function Microcontroller Only) Card Common Memory Write Function Microcontroller Only) Card Read Function Microcontroller Only) Card Write Function Microcontroller Only) Card Read Function Microcontroller Only) Card Write Function Microcontroller Only) Graphics Controller Microcontroller Only Thermal Resistance (°C/W) 292-BGA Package) Maximum Various Airflows
Microcontrollers Data Sheet
RELATED PRODUCTS E86Family Devices
Device 80C186 80C188 80L186 80L188 Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data
Am186TMEM High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188TMEM High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data Am186EMLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188EMLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data Am186ES Am188ES High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data
Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data Am186ED High-performance, 80C186- 80C188-compatible, 16-bit embedded microcontroller with 16-bit external data
Am186EDLV High-performance, 80C186- 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 16-bit external data Am186ER Am188ER Am186CC Am186CH Am186CU Am386®DX Am386®SX Am486®DX High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with Kbyte internal High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data Kbyte internal High-performance, 80C186-compatible 16-bit embedded communications controller High-performance, 80C186-compatible 16-bit embedded HDLC microcontroller High-performance, 80C186-compatible 16-bit embedded microcontroller High-performance, single-chip, 32-bit embedded PC/AT microcontroller Single-chip, low-power, PC/AT-compatible microcontroller Single-chip, PC/AT-compatible microcontroller High-performance, 32-bit embedded microprocessor with 32-bit external data High-performance, 32-bit embedded microprocessor with 16-bit external data High-performance, 32-bit embedded microprocessor with 32-bit external data
High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller
Related Documents
following documents provide additional information regarding microcontrollers. User's Manual, order #21030 Register Reference Manual, order #21032 Register Reference Amendment, order #21032A/1
Evaluation Board User's Manual, order #21906 Microcontroller Windows forCE Demonstration System User's Manual, order #21892 ROMCS0 Redirection Card Socket Microcontroller Application Note, order #21643
Manual
Microcontrollers Data Sheet
Microcontroller Evaluation Board
microcontroller evaluation board stand-alone evaluation platform microcontrollers. test development platform designs based microcontrollers, this product used system designers experiment with design trade-offs, make power measurements, develop software. Contact your local sales office more information evaluation board availability pricing.
World Wide Home Page access home page, www.amd.com. Then follow Embedded Processors link information about Comm86 products. Questions, requests, input concerning AMD's pages sent e-mail webmaster@amd.com. Documentation Literature Free information such data books, user's manuals, data sheets, application notes, E86Family Products Development Tools order #21058, other literature available with simple phone call. Internationally, contact your local sales office product literature. Additional contact information listed back this data sheet. Literature Ordering (800) 222-9323 (512) 602-5651 (512) 602-7639 Toll-free U.S. Canada Direct dial worldwide
Third-Party Development Support Products
FusionE86 Program Partnerships Application Solutions provides customer with array products designed meet critical time-tomarket needs. Products solutions available from FusionE86 partners include protocol stacks, emulators, hardware software debuggers, boardlevel products, software development tools, among others. addition, mature development tools applications platform widely available general marketplace.
ARCHITECTURAL OVERVIEW
architectural goals microcontrollers included focus performance, CPU-to-memory performance, internal graphics controller microcontroller only) performance. resulting architecture includes several distinguishing features interest system designer: main system DRAM shared between graphics controller, that graphics controller serviced quickly maintain video display performance higher panel resolutions. internal unified memory architecture (UMA) implemented microcontrollers means lower cost less complication system designer, with only DRAM interface, fewer pins, much smaller board many designs. CPU-to-memory performance critical both DRAM accesses. microcontroller concurrent path ROM/Flash memory interface execute code ROM/Flash memory same time graphics controller accessing DRAM screen refresh. Many system designs take advantage this concurrency without sacrificing performance.
Customer Service
customer service network includes U.S. offices, international offices, customer training center. Expert technical assistance available from worldwide staff field application engineers factory support staff answer E86and Comm86family hardware software development questions. Hotline World Wide Support answers technical questions, provides e-mail support well toll-free number direct access corporate applications hotline. World Wide home page provides latest product information, including technical information data upcoming product releases. addition, CodeKit software site provides tested source code example applications. Corporate Applications Hotline (800) 222-9323 44-(0) 1276-803-299 Toll-free U.S. Canada U.K. Europe hotline
Additional contact information listed back this datasheet. technical support questions Comm86 products, send e-mail epd.support@amd.com.
Microcontrollers Data Sheet
ROM/Flash memory interface provides flexibility optimize performance cycles, including support burst-mode ROMs. This microcontrollers implemented such that operating system application programs executed from ROM. Because microcontrollers support large number external buses interfaces, address data buses shared between various interfaces reduce count chip. These features result versatile architecture that various combinations data sizes achieve cost performance goals. architecture provides maximum performance flexibility highend vertical applications, contains functionality wider horizontal market that demand less performance. typical lower performance/lower cost system might implement 16-bit DRAM banks, 8-bit bus, 8/16-bit Card bus, internal graphic controller. higher performance, full-featured system might include 32-bit DRAM, VL-bus external graphics controller, 16-bit ISA/PC Card bus. following basic data configuration rules apply. complete list feature trade-offs considered system design found "System Considerations" page 20.) When internal graphics controller microcontroller enabled, DRAM always bits wide, 32-bit targets supported. This because graphics controller needs guaranteed short latency adequate video performance. either 32-bit DRAMs, 32-bit ROMs, VL-bus enabled, internal graphics controller unavailable. Note that, derivative original microcontroller, microcontroller shares primary architectural characteristics microcontroller described above, minus graphics controller PCMCIA interfaces. following sections provide overview features microcontrollers, including on-chip peripherals system interfaces.
performance significantly reducing traffic DRAM bus. System management mode (SMM) facilitates designs requiring power management providing mechanism control power unneeded peripherals transparently application software. reduce power consumption, floating-point unit been removed from Am486 core. Floating-point instructions supported microcontrollers, although normal software emulation easily implemented. microcontrollers industry-standard instruction set. Software written microprocessor previous members architecture family microcontrollers.
Power Management
Power management microcontrollers includes dedicated power management unit additional power management features built into each integrated peripheral. microcontrollers following techniques conserve power: Slow down clocks when system active Shut clocks parts chip that idle Switch power parts system that idle Automatically reduce power when batteries power management unit (PMU) controls stopping changing clocks, generation, timers, activities, battery-level monitoring. provides: Hyper-Speed, High-Speed, Low-Speed, Temporary Low-Speed, Standby, Suspend, Critical Suspend modes Dynamically adjusted clock speeds power reduction Programmable activity wake-up monitoring General-purpose signals control external devices external power management Battery power monitoring SMI/NMI synchronization generation
Clock Generation
microcontrollers require only 32.768-kHz crystal generate other clock frequencies required system. output on-chip crystal oscillator circuit used generate various frequencies utilizing four Phase-Locked Loop (PLL) circuits (three microcontroller). additional used Hyper-Speed mode.
Low-Voltage Am486 Core
microcontrollers based low-voltage Am486 core. core includes following features: 2.7-3.3-V operation reduces power consumption Industry-standard 8-Kbyte unified code data write-back cache improves both total sys-
Microcontrollers Data Sheet
ROM/Flash Memory Interface
integrated ROM/Flash memory interface supports following features: 16-, 32-bit ROM/Flash memory interfaces Three ROM/Flash memory chip selects Burst-mode ROMs accesses both speeds (normal fast-speed modes) Dedicated Read Write signals better performance Each space accommodate Mbyte ROM. three spaces individually writeprotected. This useful protecting code residing Flash memory devices. three ROM/Flash memory chip selects remapped Card socket pinstrap software control. This feature supports reprogramming soldered-down Flash memory boot devices also simplifies testing BIOS/XIP code. Three access modes supported: Normal mode, Fast mode, Burst mode. different timings used each mode. Normal access mode, cycles follow ISA-like timings. Fast access mode, cycle timing occurs clock rate with controls wait-state insertion. Burst access timing used when ROM/Flash memory interface fulfilling internal burst request support cache line refill. Wait states supported Flash memory accesses, including Burst mode. Burst-mode (page-mode) reads supported either 32-bit interface running Fast mode.
Fast page Extended Data (EDO) DRAMs Two-way interleaved operation among identically populated banks using fast-page mode devices Mixed depth width DRAM banks non-interleaved mode Symmetrical asymmetrical DRAM support
Integrated Standard PC/AT Peripherals
microcontrollers include standard peripheral controllers that make PC/AT system. Dual Controllers Dual, cascaded, 8237A-compatible controllers provide seven user-definable channels. seven internal channels, four 8-bit channels three 16-bit channels. Channel used cascade function. seven channels mapped simultaneously external request/acknowledge lines. controller microcontrollers software compatible with PC/AT cascaded 8237 controller pair. features include: Single, block, demand transfer modes Enable/disable channel controller Address increment decrement Software priority 64-Mbyte system address space increased performance Dynamic clock-enable design reducing clocked elements during inactivity Programmable clock frequency performance Dual Interrupt Controllers Dual, cascaded, 8259-compatible programmable interrupt controllers support user-definable interrupt levels. Eight external interrupt requests mapped internal inputs. interrupt controller block includes these features: Software-compatibility with PC/AT interrupt controllers 15-level priority controller Programmable interrupt modes Individual interrupt request mask capability Accepts requests from peripherals Resolves priority pending interrupts interrupts service Issues interrupt request processor Provides interrupt vectors interrupt service routines Tied into power management
DRAM Controller
integrated DRAM controller provides signals associated timing necessary support external DRAM array with minimal software programming overhead. Internal programmable registers provided select DRAM type operating mode, well refresh options. wide variety commodity DRAMs supported, substantial flexibility built into DRAM controller optimize performance microcontroller) internal graphics controller, which uses system DRAM buffers. DRAM controller supports following features: 3.3-V, 70-ns DRAMs four banks 16-bit 32-bit banks Mbyte total memory Self-refresh DRAMs
Microcontrollers Data Sheet
interrupt controller block functionally compatible with standard cascaded 8259A controller pair implemented PC/AT system. master controller drives CPU's interrupt input signal based highest priority interrupt request pending master controller's IRQ7-IRQ0 inputs. master IRQ2 input configured Cascade mode driven only slave controller's interrupt output signal. highest pending interrupt slave's inputs will therefore drive IRQ2 input master. interrupt controller programmable sources interrupts that controlled through extended configuration registers and, microcontroller, through Card controller configuration registers. Programmable Interval Timer (PIT) programmable interval timer (PIT) microcontrollers software-compatible with PC/AT 8254 system timers. provides three 16-bit counters that operated independently different modes. generally used timing external events, counting, produc repetitive waveforms. programmed count binary BCD. Real-Time Clock (RTC) microcontrollers compatible with MC146818A device used PC/AT systems. consists time-of-day clock with alarm interrupt 100-year calendar. clock/calendar programmable periodic interrupt, bytes static user RAM, represented either binary BCD. includes following features: Counts seconds, minutes, hours Counts days week, date, month, year 12-24 hour clock with indication 12-hour mode clock, status, control registers bytes general-purpose Three separately software-maskable testable interrupts Time-of-day alarm programmable occur from once-per-second once-per-day Periodic interrupts continued occur rates from Update-ended interrupt provides cycle status Dedicated power directly supports lithium backup battery when rest chip completely powered down (RTC-only mode)
Voltage monitor circuit checks voltage level lithium backup battery sets when battery below specification. Internal reset signal performs reset when power applied core.
PC/AT Support Features
microcontrollers provide support functions found original PC/AT. These include Port status control bits, speaker control, CPU-core reset based system control processor (SCP), gate control, well extensions fast core reset. addition, shutdown cycle (e.g., result triple fault) generates core reset.
Bidirectional Enhanced Parallel Port (EPP)
parallel port microcontrollers functionally compatible with PC/AT PS/2 systems, with added mode faster transfers. microcontroller's parallel port interface provides status inputs, control outputs, control signals necessary external parallel port data buffers. parallel port interface both microcontrollers shared with some GPIO signals and, microcontroller, with second Card socket interface. Only these interfaces enabled time. parallel port interface configured operate three different modes operation: PC/AT Compatible mode: This mode provides byte-wide forward (host-to-peripheral) channel with data status lines used according their original (Centronics) definitions PC/AT. Bidirectional mode: This mode offers byte-wide bidirectional parallel data transfers between host peripheral, equivalent parallel interface PS/2. Enhanced Parallel Port (EPP) mode: This mode provides byte-wide bidirectional channel controlled microcontroller. provides separate address data cycles over eight data lines interface with automatic address data strobe address data cycles, respectively. mode offers wider system bandwidth increased performance over both PC/AT Compatible Bidirectional modes.
Microcontrollers Data Sheet
Serial Port
microcontrollers include industry-standard 16550A UART. UART used drive standard 8-pin serial interface 2-pin infrared interface. serial interface infrared interface signals available microcontrollers times, though only available given time. UART powers 16450-compatible device. switched from FIFO (16550) mode under software control. FIFO mode, receive transmit circuitry each enhanced separate 16-byte FIFOs off-load from repetitive service routines. serial port includes following features: Eight-pin interface: serial serial out, modem control lines, four modem status lines Separately enabled receiver line status, receiver data, character timeout, transmitter holding register, modem status interrupts Baud-rate generator provides input clock divisor from 65535 create clock 8-bit data Even, odd, stick, parity generation checking 1-1/2 stop-bit generation Break generation/detection
(NMIs), wake-ups, activities power management unit. They also used memory chip selects.
Infrared Port Wireless Communication
microcontrollers support infrared data transfer. This support consists adding additional transmit receive serializers well controlling state machine interface internal UART. integrated infrared port includes these features: Low-speed mode supports rates from UART, Kbit/s High-speed mode transfers 1.152 Mbit/s using
Dual Card Controller Microcontroller Only)
Card host adapter included microcontroller conforms PCMCIA Standard Release 2.1. provides support sockets, each implementing Card memory interfaces. Card controller supported microcontroller. Card controller includes following features: ExCA-compliant, 82365-register-set compatible 8-bit 16-bit data transfers between cards system DRAM available memory windows, five socket Card sockets supported, only available modes operation. second socket multiplexed with parallel port GPIO features. Register compatibility with 82365SL Card Interface Controller maintained where features common both controllers. memory windows available, dedicated Card controller four shared with memory mapping system (MMS) Windows C-F. three ROM/Flash memory chip selects remapped Card socket pinstrap software control. This feature supports reprogramming soldered down Flash memory boot devices also simplifies testing BIOS/XIP code.
Keyboard Interfaces
integrated keyboard controller following features: Matrix keyboard support with rows columns Hardware support software emulation System Control Processor (SCP) emulation logic keyboard interface
Programmable General-Purpose Inputs Outputs
chip supports several general-purpose signals (GPIOs) that used system board. There classifications GPIO available: GPIOx signals, which programmable inputs outputs only, GPIO_CSx signals. GPIO_CSx signals have many programmable options. They configured chip selects. outputs, these signals individually programmable High following modes: Hyper, HighSpeed, Low-Speed, Standby, Suspend. inputs, they programmed cause System Management Interrupts (SMIs), Non-Maskable Interrupts
Graphics Controller CGA-Compatible Text Graphics Microcontroller Only)
graphics controller included microcontroller offers low-cost integrated graphics solution mobile terminal market. Integration with main processor system logic affords advan-
Microcontrollers Data Sheet
tages integrated local-bus interface frame font buffers that shared with main memory. graphics controller supported microcontroller. graphics controller includes following features: Supports multiple panel resolutions Provides internal unified memory architecture (UMA) with optional write-through caching graphics buffers Stores frame font buffer data system DRAM, eliminates extra memory chip Provides software compatibility with Color Graphics Adapter (CGA), Monochrome Display Adapter (MDA), Hercules Graphics Adapter (HGA) text graphics Supports single-scan dual-scan monochrome panels with 4-bit 8-bit data interface Typical panels supported include: 200, 240, 480, 320, 240, 128, 200, Other resolutions supported Supports single-scan color panels with 8-bit interface, same resolutions monochrome mode Internal local-bus interface provides high performance Logical screen larger than physical window. Supports panning scrolling Supports horizontal doubling vertical line doubling following MDA/CGA-compatible text mode features supported: columns with characters pixels wide Variable height characters lines Variable width characters-8, pixels Monochrome, gray shades, gray shades, 16-colors 16-Kbyte downloadable font area, relocatable 16-Kbyte boundaries within lower Mbytes system DRAM (can write protected) 16-Kbyte frame buffer, relocatable either 16-Kbyte boundaries within lower Mbyte system DRAM (CGA-compatible mode) 32-Kbyte boundaries when frame buffer larger than Kbyte (flat-mapped mode)
following graphics mode features supported: bit-per-pixel, CGA-compatible graphics buffer memory bits-per-pixel, CGA-compatible graphics buffer memory bits-per-pixel, flat memory (lower resolutions supported) bit-per-pixel, flat memory bits-per-pixel packed-pixel flat-mapped graphics 240/480 with mapping modes: 16-Kbyte window with bank swapping address Kbyte graphics frame buffer while consuming only Kbyte DOS/Realmode address space Direct-mapped bank swapping) with locatable base address, 128-Kbyte direct addressability Hercules Graphics mode emulation (HGA)
JTAG Test Features
microcontrollers provide boundary-scan interface based IEEE 1149.1, Standard Test Access Port BoundaryScan Architecture test access port provides scan interface testing microcontroller system hardware production environment. contains extensions that allow hardware-development system control observe microcontroller without interposing hardware between microcontroller system.
System Interfaces
Data Buses microcontrollers provide bits data that divided into separate 16-bit buses. System Data Bus: system peripheral) data (SD15-SD0) always bits wide shared between ISA, 8-bit 16-bit ROM/Flash memory, Card peripherals microcontroller only). directly connected these devices. addition, these signals upper word VESA local (VL) data bus, 32-bit DRAM interface, 32-bit interface. Data Bus: D15-D0 data used during 16-bit DRAM cycles. 32-bit DRAM, VL-bus, cycles, this combined with system data bus. other words, data signals (D31-D16) shared with system data signals SD15-SD0.
Microcontrollers Data Sheet
microcontrollers support data configurations listed below. External transceivers buffers used isolate buses. 16-bit DRAM bus, 8-/16-bit ROM, 32-bit VL-bus disabled, internal graphics controller enabled/ disabled 16-/32-bit DRAM bus, 8/16-bit ROM, 32-bit VL-bus enabled/disabled, internal graphics controller disabled 16-/32-bit DRAM bus, 32-bit ROM, 32-bit VL-bus enabled/disabled, internal graphics controller disabled Figure page Figure page block diagrams example systems. microcontrollers offer flexibility configuring DRAM data buses different widths. widths (8/16/32 bits) ROMCS0 programmed during power-up through pinstraps, CFG0 CFG1. DRAM widths (16/32 bits) programmed through configuration registers. four 32-bit banks DRAM supported. three ROM/Flash memory chip selects (ROMCS2-ROMCS0) remapped Card socket pinstrap software control. This feature supports reprogramming soldered-down Flash memory boot devices also simplifies testing BIOS/XIP (execute place) code. Address Buses There external address buses microcontrollers. System Address Bus: SA25-SA0 system address outputs physical memory port latched addresses. These addresses used external peripheral devices other than main system DRAM. addition, system address local address VL-bus mode. DRAM Address Bus: DRAM column addresses multiplexed onto DRAM address (MA12-MA0). addresses driven onto this valid upon falling edge RAS. Column addresses driven onto this valid upon falling edge CAS. shared between bus, VL-bus, ROM/Flash memory controller and, microcontroller, Card controller. microcontrollers provide programmable drive strengths buffers accommodate loading various system configurations.
Memory Management microcontrollers manage nine separate physical device memory address spaces. memory address space have depth Mbyte each. memory area limited Mbyte, defined specifications. microcontroller will drive address lines cycles allow 64-Mbyte address space, described memory management section Microcontrollers User's Manual (order #21030)-refer subsection addressing). nine memory spaces are: System memory address space (DRAM) ROM0 memory address space (ROMCS0 signal) ROM1 memory address space (ROMCS1 signal) ROM2 memory address space (ROMCS2 signal) Card Socket memory address spaces (common attribute) microcontroller only) Card Socket memory address spaces (common attribute) microcontroller only) External ISA/VL-bus memory address space system memory address space (DRAM) accessible using direct-mapped addresses also accessed indirect method using Memory Mapping System (MMS). microcontroller, DRAM also accessible integrated graphics controller enabled. ROM0 address space partially accessible direct mapping address partially accessible MMS. ROM1 ROM2 address spaces only accessible indirectly using MMS. microcontroller, Card address spaces accessed through separate, 82365SL-compatible address mapping system. ISA/VL-bus address space accessible direct mapping address bus. memory cycles generated when generates memory cycle that detected access other memory space. memory cycle also generated generates memory address that resides overlapping memory region window. This window defined overlay system memory region below Mbyte.
Microcontrollers Data Sheet
Interface External Peripherals interface consists subset ISA-compatible signals, allowing connection 16-bit devices supporting ISA-compatible I/O, memory, cycles. following features supported: 8.2944-MHz maximum clock speed Programmable clock speed 8-bit 16-bit memory cycles (ISA memory non-cacheable) Direct connection 5-volt peripherals Eight programmable input signals available. These interrupts routed software available PC/AT-compatible interrupt channel. programmable channels available external peripherals. These channels routed software available channel. VESA Local (VL) Interface Supports 32-Bit Memory Targets VESA local (VL) controller provides signals associated timing necessary support single VESA compliant VL-bus target. Multiple VL-bus targets supported using external circuitry allow multiple devices share VL_LDEV signal. This allows microcontrollers operate normal VL-bus motherboard controller, accordance with VL-Bus Standard 2.0. microcontroller, VL-bus available only when internal graphics controller disabled. microcontroller's VL-bus controller includes following features: 33-MHz operation 32-bit data Burst-mode transfers Register control local reset VESA mastering transfers from VL-bus target supported. memory non-cacheable.
SYSTEM CONSIDERATIONS
Figure shows microcontroller might used minimal system design. Figure Figure show more complex system designs each microcontroller features that traded others because multiplexing. microcontrollers support maximum banks 32-bit DRAM, because signals high word banks traded keyboard signals, minimum system would have banks DRAM (either Bank Bank populated with 16-bit DRAMs. MA12 signal asymmetrical support also traded with keyboard signal. Because VL-bus graphics controller share control signals microcontroller, internal graphics controller traded with having external VL-bus that microcontroller. either 32-bit DRAMs, 32-bit ROMs, VL-bus enabled, internal graphics controller microcontroller unavailable because internal design constraints. microcontrollers provide absolute minimum dedicated control signals. additional controls traded with GPIOs keyboard rows columns. buffer shares control signals with some GPIOs. This buffer controls high word data (D31-D16). Note that using buffer optional. high word data hooked directly devices that want data (SD15-SD0). Buffering aids voltage translation isolation heavy loading. R32BFOE signal buffers high word data (D31-D16) 32-bit ROMs. control signal associated with ROM32 buffer shared with keyboard row. microcontroller, parallel port traded Card Socket requires external buffer latch. serial infrared ports share same internal UART. Real-time switching between supported; however, only port available given time. ROMCS2 connected dedicated pin. Software enable GPIO_CS signals.
Microcontrollers Data Sheet
Bank Bank
Ctrl Word D15-D0 MA11-MA0
Matrix Keyboard Conn Column Conn
Ctrl
DRAM
DRAM
Microcontrollers Data Sheet
Figure Typical Mobile Terminal Design
32-kHz Crystal Loop Filters Backup Battery Conn Battery Ctrl Power Supply
Ctrl Rows Columns SA25-SA0 GPIO_CS12-GPIO_CS0 High SD15-SD0
Microcontroller
Ctrl Card Ctrl Card Ctrl Serial Infrared Ctrl Ctrl SA25-SA1 SD15-SD0 Ctrl
BIOS/OS Flash/
Serial Translator Serial Conn Speaker Infrared
Card Socket
Card Socket
Bank High Word Bank Bank Bank
DRAM
DRAM
DRAM
DRAM
Word
DRAM
DRAM
DRAM
DRAM
Ctrl MA12
Keyboard
Figure System Diagram with Microcontroller
High Ctrl Ctrl Rows Columns
Microcontrollers Data Sheet
Device
Microcontroller
Conn
Ctrl
Buffer 32-kHz Crystal
High Ctrl Ctrl Card Ctrl Card Ctrl Serial Infrared Ctrl
Ctrl
ROM32 Buffer
Ctrl Ctrl Ctrl Ctrl
Device
Loop Filters
Ctrl Ctrl
BIOS/ Apps Flash
Backup Battery Battery
Serial Translator Power Supply Infrared Serial Conn
Buffer
Latch Card Socket Card Socket
Parallel Port Connector
Notes: dashed indicates feature that optional traded another.
Bank High Word
Bank
Bank
Bank
DRAM
DRAM
DRAM
DRAM
Word
DRAM
DRAM
DRAM
DRAM
Ctrl MA12
Keyboard
Figure System Design with Microcontroller
High DRAM Ctrl Rows Columns Ctrl
Microcontrollers Data Sheet
Device
Microcontroller
VL-Bus Ctrl
Ctrl
Buffer 32-kHz Crystal
High Ctrl
Ctrl
ROM32 Buffer
Ctrl Ctrl Ctrl
Device
Loop Filters
Ctrl Parallel Ctrl Serial IrDA Ctrl Ctrl
BIOS/ Apps Flash
Backup Battery
Serial Translator Power Supply Infrared Serial Conn
Buffer Latch
Notes:
Parallel Port Connector
dashed indicates feature that optional traded another.
CONNECTION MICROCONTROLLERS Ball Grid Array (BGA) Package View (from component side looking through bottom)
Microcontrollers Data Sheet
DESIGNATIONS
This section identifies pins microcontrollers lists signals associated with each pin. Several different tables included this section. Designations (Pin Microcontroller table beginning page lists microcontroller signals sorted number. Designations (Pin microcontroller signals sorted number. Along with Connection Diagram page these tables used associate complete name (including multiplexed functions) with physical package. Designations (Pin microcontroller signals sorted alphabetical order. Designations (Pin microcontroller signals sorted alphabetical order. multiplexed signals included these lists. Note that these tables should used determine primary secondary functions multiplexed pins because ordering changed alphabetize every function. Please refer Designations (Pin Number) table State tables definitive listing primary secondary functions correct order each pin. State tables beginning page which group pins alphabetically function, show states during reset, normal operation, Suspend mode, along with output drive strength, maximum load, supply source, power-down groups. Signal Description table beginning page includes complete descriptions alphabetical order function. table beginning page clarifies configuration options those pins having multiple functions.
Naming
Signal Name column Designation tables beginning page State tables beginning page decoded follows: NAME1/NAME2 {NAME3} [NAME4] [[NAME5]] NAME1 This only function pin. NAME1/NAME2 slash separates functions that available same time (i.e., different times same design used different functions). {NAME3} name braces function during hardware reset. [NAME4] name square brackets alternative function pin, selected firmware configuration. Only function available each configuration. [[NAME5]] name inside double square brackets alternate function pin, selected hardware configuration state power-on reset. This does apply [[BNDSCN_TCK]], [[BNDSCN_TMS]], [[BNDSCN_TDI]], [[BNDSCN_TDO]]. These four alternate functions enabled BNDSCN_EN signal. Only function available each configuration.
CHANGES MICROCONTROLLER
following signals supported microcontroller available microcontroller. Configuration signal: CFG2 Card controller signals: MCEL_A, MCEL_B, MCEH_A, MCEH_B, RST_A, RST_B, REG_A, REG_B, CD_A, CD_B, CD_A2, RDY_A, RDY_B, BVD1_A, BVD1_B, BVD2_A, BVD2_B, WP_A, WP_B, WAIT_AB, ICDIR, PCMA_VCC, PCMA_VPP1, PCMA_VPP2, PCMB_VCC, PCMB_VPP1, PCMB_VPP2 Graphics controller signals: LCDD7-LCDD0, SCK, FRM, LVEE, LVDD Loop filter signal: LF_VID
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller
Signal Name KBD_COL5/PIRQ6 KBD_COL2/PIRQ3 KBD_ROW13 [[R32BFOE]] {CFG2} MA11 CASH1 LVDD [VL_BLAST] LVEE [VL_BRDY] KBD_COL6/PIRQ7 KBD_COL3/PIRQ4 {CFG1} {CFG3} CASL0 KBD_ROW6 [MA12] KBD_ROW3 [CASH3] Signal Name KBD_ROW0 [CASL2] LCDD0 [VL_RST] KBD_ROW11 [SBHE] KBD_ROW8 [PDRQ1] KBD_COL4/PIRQ5 GPIO_CS4 [[DBUFOE]] KBD_COL7 {CFG0} MA10 CASL1 RAS0 KBD_ROW5 [RAS3] KBD_ROW2 [CASH2] GPIO_CS2 [[DBUFRDL]] LCDD1 [VL_ADS] LCDD3 [VL_M/IO] KBD_COL1 [XT_CLK] KBD_ROW10 [BALE] KBD_ROW7 [PDACK1] CASH0 RAS1 KBD_ROW4 [RAS2] KBD_ROW1 [CASL3] Signal Name GPIO_CS3 [[DBUFRDH]] LCDD2 [VL_W/R] LCDD4 [VL_LRDY] LCDD7 [VL_BE3] KBD_COL0 [XT_DATA] KBD_ROW9 [PIRQ2] LCDD5 [VL_D/C] [VL_LCLK] [VL_BE1] [D20] [D17] KBD_ROW12 [MCS16] LCDD6 [VL_LDEV] [VL_BE2] [VL_BE0] SA24 [D22] [D19] [D16] GPIO20 [CD_A2] SA22 SA21 [D21] [D18]
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller (Continued)
Signal Name SA25 SA23 SA20 SA18 SD10 [D26] [D23] SA19 SA17 SA14 SD11 [D27] [D25] [D24] VCC_CPU SA16 SA15 SA13 SA12 SD12 [D28] SD13 [D29] SD15 [D31] VCC_CPU Signal Name SA10 SA11 REG_A [[BDNSCN_TDO]] ICDIR VCC_CPU SD14 [D30] MCEH_A [[BNDSCN_TMS]] VCC_CPU MCEL_A [[BNDSCN_TCK]] Signal Name RDY_A VCC_CPU RST_A [[BNDSCN_TDI]] CD_A BVD2_A VCC_CPU ROMCS0 WP_A GPIO22 [PPOEN] VCC_CPU MEMW ROMCS1 WAIT_AB GPIO25 [ACK] [BVD1_B] GPIO24 [BUSY] [BVD2_B] GPIO23 [SLCT] [WP_B]
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller (Continued)
Signal Name ROMWR BVD1_A GPIO31 [STRB] [MCEL_B] GPIO21 [PPDWE] GPIO27 [ERROR] [CD_B] LF_HS BBATSEN SPKR SIROUT RSTDRV GPIO19 [LBL2] GPIO16 [PCMB_VCC] GPIO_CS13 [PCMA_VCC] GPIO_CS10 [AEN] GPIO_CS6 [IOCHRDY] Signal Name GPIO_CS0 ROMRD GPIO30 [AFDT] [MCEH_B] GPIO26 [PE] [RDY_B] GPIO29 [SLCTIN] [RST_B] LF_LS LF_VID VCC_A VCC_RTC ACIN [CLK_IO] GPIO17 [PCMB_VPP1] GPIO_CS14 [PCMA_VPP1] GPIO_CS11 [PDACK0] GPIO_CS8 [PIRQ0] GPIO_CS5 [IOCS16] MEMR Signal Name GPIO28 [INIT] [REG_B] LF_INT 32KXTAL2 GND_ANALOG 32KXTAL1 RESET SIRIN SOUT BNDSCN_EN SUS_RES/KBD_ROW14 GPIO18 [PCMB_VPP2] GPIO15 [PCMA_VPP2] GPIO_CS12 [PDRQ0] GPIO_CS9 [TC] GPIO_CS7 [PIRQ1] GPIO_CS1
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller
Signal Name ACIN [ACK] [BVD1_B] GPIO25 [AEN] GPIO_CS10 [AFDT] [MCEH_B] GPIO30 [BALE] KBD_ROW10 BBATSEN [CLK_IO] BNDSCN_EN [[BNDSCN_TCK]] MCEL_A [[BNDSCN_TDI]] RST_A [[BNDSCN_TDO]] REG_A [[BNDSCN_TMS]] MCEH_A [BUSY] [BVD2_B] GPIO24 BVD1_A [BVD1_B] GPIO25 [ACK] BVD2_A [BVD2_B] GPIO24 [BUSY] CASH0 CASH1 [CASH2] KBD_ROW2 [CASH3] KBD_ROW3 CASL0 CASL1 [CASL2] KBD_ROW0 [CASL3] KBD_ROW1 CD_A [CD_A2] GPIO20 [CD_B] GPIO27 [ERROR] {CFG0} {CFG1} {CFG2} {CFG3} [CLK_IO] Signal Name [D16] [D17] [D18] [D19] [D20] [D21] [D22] [D23] [D24] [D25] [D26] SD10 [D27] SD11 [D28] SD12 [D29] SD13 [D30] SD14 [D31] SD15 [[DBUFOE]] GPIO_CS4 [[DBUFRDH]] GPIO_CS3 [[DBUFRDL]] GPIO_CS2 [ERROR] [CD_B] GPIO27 [VL_LCLK] Signal Name
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller (Continued)
Signal Name GND_ANALOG GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16] GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] Signal Name GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 [PCMA_VCC] GPIO_CS14 [PCMA_VPP1] GPIO15 [PCMA_VPP2] GPIO16 [PCMB_VCC] GPIO17 [PCMB_VPP1] GPIO18 [PCMB_VPP2] GPIO19 [LBL2] GPIO20 [CD_A2] GPIO21 [PPDWE] GPIO22 [PPOEN] GPIO23 [SLCT] [WP_B] GPIO24 [BUSY] [BVD2_B] GPIO25 [ACK] [BVD1_B] GPIO26 [PE] [RDY_B] GPIO27 [ERROR] [CD_B] GPIO28 [INIT] [REG_B] GPIO29 [SLCTIN] [RST_B] GPIO30 [AFDT] [MCEH_B] GPIO31 [STRB] [MCEL_B] ICDIR [INIT] [REG_B] GPIO28 [IOCHRDY] GPIO_CS6 [IOCS16] GPIO_CS5 32KXTAL1 32KXTAL2 KBD_COL0 [XT_DATA] KBD_COL1 [XT_CLK] KBD_COL2/PIRQ3 KBD_COL3/PIRQ4 KBD_COL4/PIRQ5 KBD_COL5/PIRQ6 KBD_COL6/PIRQ7 KBD_COL7 Signal Name KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] KBD_ROW7 [PDACK1] KBD_ROW8 [PDRQ1] KBD_ROW9 [PIRQ2] KBD_ROW10 [BALE] KBD_ROW11 [SBHE] KBD_ROW12 [MCS16] KBD_ROW13 [[R32BFOE]] KBD_ROW14 SUS_RES [LBL2] GPIO19 [VL_BE1] LCDD0 [VL_RST] LCDD1 [VL_ADS] LCDD2 [VL_W/R] LCDD3 [VL_M/IO] LCDD4 [VL_LRDY] LCDD5 [VL_D/C] LCDD6 [VL_LDEV] LCDD7 [VL_BE3] LF_HS LF_INT LF_LS LF_VID LVDD [VL_BLAST] LVEE [VL_BRDY] [VL_BE2] {CFG0} {CFG1} {CFG2} {CFG3}
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller (Continued)
Signal Name MA10 MA11 [MA12] KBD_ROW6 MCEH_A [[BNDSCN_TMS]] [MCEH_B] GPIO30 [AFDT] MCEL_A [[BNDSCN_TCK]] [MCEL_B] GPIO31 [STRB] [MCS16] KBD_ROW12 MEMR MEMW [PCMA_VCC] GPIO_CS13 [PCMA_VPP1] GPIO_CS14 [PCMA_VPP2] GPIO15 [PCMB_VCC] GPIO16 [PCMB_VPP1] GPIO17 [PCMB_VPP2] GPIO18 [PDACK0] GPIO_CS11 [PDACK1] KBD_ROW7 [PDRQ0] GPIO_CS12 [PDRQ1] KBD_ROW8 [PE] [RDY_B] GPIO26 [PIRQ0] GPIO_CS8 [PIRQ1] GPIO_CS7 [PIRQ2] KBD_ROW9 PIRQ3/KBD_COL2 PIRQ4/KBD_COL3 PIRQ5/KBD_COL4 PIRQ6/KBD_COL5 PIRQ7/KBD_COL6 [PPDWE] GPIO21 [PPOEN] GPIO22 [[R32BFOE]] KBD_ROW13 Signal Name RAS0 RAS1 [RAS2] KBD_ROW4 [RAS3] KBD_ROW5 RDY_A [RDY_B] GPIO26 [PE] REG_A [[BNDSCN_TDO]] [REG_B] GPIO28 [INIT] RESET ROMCS0 ROMCS1 ROMRD ROMWR RST_A [[BNDSCN_TDI]] [RST_B] GPIO29 [SLCTIN] RSTDRV SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 Signal Name SA20 SA21 SA22 SA23 SA24 SA25 [SBHE] KBD_ROW11 [VL_BE0] [D16] [D17] [D18] [D19] [D20] [D21] [D22] [D23] [D24] [D25] SD10 [D26] SD11 [D27] SD12 [D28] SD13 [D29] SD14 [D30] SD15 [D31] SIRIN SIROUT [SLCT] [WP_B] GPIO23 [SLCTIN] [RST_B] GPIO29 SOUT SPKR [STRB] [MCEL_B] GPIO31 SUS_RES/KBD_ROW14 [TC] GPIO_CS9
Microcontrollers Data Sheet
DESIGNATIONS (Pin Microcontroller (Continued)
Signal Name Signal Name VCC_A VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_RTC [VL_ADS] LCDD1 [VL_BE0] [VL_BE1] [VL_BE2] Signal Name [VL_BE3] LCDD7 [VL_BLAST] LVDD [VL_BRDY] LVEE [VL_D/C] LCDD5 [VL_LCLK] [VL_LDEV] LCDD6 [VL_LRDY] LCDD4 [VL_M/IO] LCDD3 [VL_RST] LCDD0 [VL_W/R] LCDD2 WAIT_AB WP_A [WP_B] GPIO23 [SLCT] [XT_CLK] KBD_COL1 [XT_DATA] KBD_COL0
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER
Signal Name KBD_COL5/PIRQ6 KBD_COL2/PIRQ3 KBD_ROW13 [[R32BFOE]] MA11 CASH1 VL_BLAST VL_BRDY KBD_COL6/PIRQ7 KBD_COL3/PIRQ4 {CFG1} {CFG3} CASL0 KBD_ROW6 [MA12] KBD_ROW3 [CASH3] Signal Name KBD_ROW0 [CASL2] VL_RST KBD_ROW11 [SBHE] KBD_ROW8 [PDRQ1] KBD_COL4/PIRQ5 GPIO_CS4 [[DBUFOE]] KBD_COL7 {CFG0} MA10 CASL1 RAS0 KBD_ROW5 [RAS3] KBD_ROW2 [CASH2] GPIO_CS2 [[DBUFRDL]] VL_ADS VL_M/IO KBD_COL1 [XT_CLK] KBD_ROW10 [BALE] KBD_ROW7 [PDACK1] CASH0 RAS1 KBD_ROW4 [RAS2] KBD_ROW1 [CASL3] Signal Name GPIO_CS3 [[DBUFRDH]] VL_W/R VL_LRDY VL_BE3 KBD_COL0 [XT_DATA] KBD_ROW9 [PIRQ2] VL_D/C VL_LCLK VL_BE1 [D20] [D17] KBD_ROW12 [MCS16] VL_LDEV VL_BE2 VL_BE0 SA24 [D22] [D19] [D16] GPIO20 SA22 SA21 [D21] [D18]
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER (Continued)
Signal Name SA25 SA23 SA20 SA18 SD10 [D26] [D23] SA19 SA17 SA14 SD11 [D27] [D25] [D24] VCC_CPU SA16 SA15 SA13 SA12 SD12 [D28] SD13 [D29] SD15 [D31] VCC_CPU Signal Name SA10 SA11 [[BNDSCN_TDO]] Reserved VCC_CPU SD14 [D30] Reserved [[BNDSCN_TMS]] VCC_CPU Reserved [[BNDSCN_TCK]] Signal Name Reserved VCC_CPU [[BNDSCN_TDI]] Reserved Reserved VCC_CPU ROMCS0 Reserved GPIO22 [PPOEN] VCC_CPU MEMW ROMCS1 Reserved GPIO25 [ACK] GPIO24 [BUSY] GPIO23 [SLCT]
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER (Continued)
Signal Name ROMWR Reserved GPIO31 [STRB] GPIO21 [PPDWE] GPIO27 [ERROR] LF_HS BBATSEN SPKR SIROUT RSTDRV GPIO19 [LBL2] GPIO16 GPIO_CS13 GPIO_CS10 [AEN] GPIO_CS6 [IOCHRDY] Signal Name GPIO_CS0 ROMRD GPIO30 [AFDT] GPIO26 [PE] GPIO29 [SLCTIN] LF_LS Reserved VCC_A VCC_RTC ACIN [CLK_IO] GPIO17 GPIO_CS14 GPIO_CS11 [PDACK0] GPIO_CS8 [PIRQ0] GPIO_CS5 [IOCS16] MEMR Signal Name GPIO28 [INIT] LF_INT 32KXTAL2 GND_ANALOG 32KXTAL1 RESET SIRIN SOUT BNDSCN_EN SUS_RES/KBD_ROW14 GPIO18 GPIO15 GPIO_CS12 [PDRQ0] GPIO_CS9 [TC] GPIO_CS7 [PIRQ1] GPIO_CS1
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER
Signal Name ACIN [ACK] GPIO25 [AEN] GPIO_CS10 [AFDT] GPIO30 [BALE] KBD_ROW10 BBATSEN [CLK_IO] BNDSCN_EN [[BNDSCN_TCK]] [[BNDSCN_TDI]] [[BNDSCN_TDO]] [[BNDSCN_TMS]] [BUSY] GPIO24 CASH0 CASH1 [CASH2] KBD_ROW2 [CASH3] KBD_ROW3 CASL0 CASL1 [CASL2] KBD_ROW0 [CASL3] KBD_ROW1 {CFG0} {CFG1} {CFG3} [CLK_IO] Signal Name [D16] [D17] [D18] [D19] [D20] [D21] [D22] [D23] [D24] [D25] [D26] SD10 [D27] SD11 [D28] SD12 [D29] SD13 [D30] SD14 [D31] SD15 [[DBUFOE]] GPIO_CS4 [[DBUFRDH]] GPIO_CS3 [[DBUFRDL]] GPIO_CS2 [ERROR] GPIO27 Signal Name
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER (Continued)
Signal Name GND_ANALOG GPIO_CS0 GPIO_CS1 GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] GPIO_CS5 [IOCS16] GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] GPIO_CS13 GPIO_CS14 GPIO15 GPIO16 GPIO17 GPIO18 Signal Name GPIO19 [LBL2] GPIO20 GPIO21 [PPDWE] GPIO22 [PPOEN] GPIO23 [SLCT] GPIO24 [BUSY] GPIO25 [ACK] GPIO26 [PE] GPIO27 [ERROR] GPIO28 [INIT] GPIO29 [SLCTIN] GPIO30 [AFDT] GPIO31 [STRB] [INIT] GPIO28 [IOCHRDY] GPIO_CS6 [IOCS16] GPIO_CS5 32KXTAL1 32KXTAL2 KBD_COL0 [XT_DATA] KBD_COL1 [XT_CLK] KBD_COL2/PIRQ3 KBD_COL3/PIRQ4 KBD_COL4/PIRQ5 KBD_COL5/PIRQ6 KBD_COL6/PIRQ7 KBD_COL7 KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] KBD_ROW7 [PDACK1] KBD_ROW8 [PDRQ1] KBD_ROW9 [PIRQ2] Signal Name KBD_ROW10 [BALE] KBD_ROW11 [SBHE] KBD_ROW12 [MCS16] KBD_ROW13 [[R32BFOE]] KBD_ROW14 SUS_RES [LBL2] GPIO19 LF_HS LF_INT LF_LS {CFG0} {CFG1} {CFG3} MA10 MA11 [MA12] KBD_ROW6 [MCS16] KBD_ROW12 MEMR MEMW [PDACK0] GPIO_CS11 [PDACK1] KBD_ROW7 [PDRQ0] GPIO_CS12 [PDRQ1] KBD_ROW8 [PE] GPIO26 [PIRQ0] GPIO_CS8 [PIRQ1] GPIO_CS7 [PIRQ2] KBD_ROW9 PIRQ3/KBD_COL2 PIRQ4/KBD_COL3 PIRQ5/KBD_COL4 PIRQ6/KBD_COL5
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER (Continued)
Signal Name PIRQ7/KBD_COL6 [PPDWE] GPIO21 [PPOEN] GPIO22 [[R32BFOE]] KBD_ROW13 RAS0 RAS1 [RAS2] KBD_ROW4 [RAS3] KBD_ROW5 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved RESET ROMCS0 ROMCS1 ROMRD ROMWR RSTDRV SA10 SA11 Signal Name SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 [SBHE] KBD_ROW11 [D16] [D17] [D18] [D19] [D20] [D21] [D22] [D23] [D24] [D25] SD10 [D26] SD11 [D27] SD12 [D28] SD13 [D29] SD14 [D30] SD15 [D31] SIRIN SIROUT [SLCT] GPIO23 [SLCTIN] GPIO29 SOUT SPKR Signal Name [STRB] GPIO31 SUS_RES/KBD_ROW14 [TC] GPIO_CS9 VCC_A VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_RTC VL_ADS
Microcontrollers Data Sheet
DESIGNATIONS (Pin MICROCONTROLLER (Continued)
Signal Name VL_BE0 VL_BE1 VL_BE2 VL_BE3 VL_BLAST Signal Name VL_BRDY VL_D/C VL_LCLK VL_LDEV VL_LRDY Signal Name VL_M/IO VL_RST VL_W/R [XT_CLK] KBD_COL1 [XT_DATA] KBD_COL0
Microcontrollers Data Sheet
STATE TABLES
state tables beginning page grouped alphabetically function show states during reset, normal operation, Suspend mode, along with output drive strength, maximum load, supply source, power-down groups. Normal Operation: Normal Operation column covers following power management modes: Hyper-Speed mode High-Speed mode Low-Speed mode Temporary Low-Speed mode Standby mode Suspend State: letters used Suspend State column defined Table Note that Critical Suspend mode, terminations remain unchanged from prior mode. Table Type Abbreviations
Symbol Meaning Brackets signify alternate state Reset configuration output during Suspend mode continues function during Suspend mode Bidirectional Driven High logical input Input open drain output Driven logical Last state prior entering Suspend mode applicable active output Open drain output typically open drain output, configured Schmitt trigger input Built-in pulldown resistor Programmable pulldown resistor Programmable pullup resistor Programmable pullup pulldown resistor Built-in pullup resistor safe Schmitt trigger input typically Schmitt trigger input, configured open-drain output Three-state output
Characteristics
following information describes individual column headings State tables beginning page Most abbreviations defined Table Drive types power-down groups defined Tables respectively. Number: Number column tables identifies number individual signal package. Type: abbreviations Type column tables defined Table Output Drive: Output Drive column designates output drive strength pin. footnote after drive strength letter designates that drive strength programmable. available drive strengths indicated Table Table
Output Drive
Drive Output Description
IohTTL/IolTTL1 -3mA/3mA -6mA/6mA -12mA/12mA -18mA/18mA -24mA/24mA
OD-STI
Notes: current given negative value. Output drive programmable.
Load: Load column designates load which timing that guaranteed. also used determine derated timing. Supply: Supply column identifies that supplies power specified pin.The state table shows state termination each power management unit mode.
PPUD STI-OD
Microcontrollers Data Sheet
Table Power Type Abbreviations
Symbol Meaning analog input power input Real-time clock input Power input
column denotes pins that 5-volt safe. This means these signals tolerate volts they will damaged. However, they cannot drive volts.
Using State Tables
following State tables, multiplexed pins include values specific each signal (across table) where that signal named. cell only value listed three different signals, then this value constant (does change) matter what signal programmed come pin. example, table page when GPIO19, bidirectional; when LBL2, output only. Because cell includes separate lines, type unique each signal. When either GPIO19 LBL2, reset state I-PU. Because there only value shown table, this value applies both signals.
Power-Down Group: signals chip grouped together interface purpose powering down chips system board that connected these signals Suspend mode. letters Power-Down Group column indicate group with which each affected signal associated. Only those signals that have different Suspend state based interface powering have letter. interfaces identified Table extended registers have bits that allow components connected each interface powered down Suspend mode. Care must taken when designing system with sections that power down, because many signals shared between components. Table
Group Interface DRAM (shared signals individually enabled) Serial port, serial IrDA infrared port GPIO Chip Selects Card Socket Card Socket parallel port buffer control signals
Power-Down Groups
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] MEMR MEMW RSTDRV SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 [D16] [D17] [D18] [D19] [D20] [D21] [D22] [D23] [D24] [D25] SD10 [D26] Type
State Table-System Interface1
Reset State TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD Normal Operation B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD Suspend State H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD I-PD Power Down Group Note
Output Load Supply Drive (pF) C-E4 C-E4 C-E4 C-E4 C-E4 C-E4
C-E4
C-E4
C-E4
C-E4
C-E4
C-E4
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] SD11 [D27] SD12 [D28] SD13 [D29] SD14 [D30] SD15 [D31] Type
State Table-System Interface1 (Continued)
Reset State TS-PD TS-PD TS-PD TS-PD TS-PD Normal Operation B-PPUD B-PPUD B-PPUD B-PPUD B-PPUD Suspend State I-PD I-PD I-PD I-PD I-PD Power Down Group Note
Output Load Supply Drive (pF) C-E4
C-E4
C-E4
Notes: states AEN, IOCHRDY, IOCS16, PDACK0, PDRQ0, PIRQ1-PIRQ0 listed Table page states BALE, MCS16, SBHE, PDACK1, PDRQ1 PIRQ7-PIRQ2 listed Table page control signals have three programmable options Suspend mode: -Driven High (inactive). -Three-stated with pullup pulldown. This useful when device left powered Suspend. board design should drive 3.3-V signals into device during Suspend because this waste power. system designer should provide large pullup resistors each these signals board this configuration programmed. Three-stated with pulldown resistors when suspended with intent powering device (Power-Down Group careful when handling because they shared with Card sockets need buffered certain combinations system components powered off. Summary: These pins have built-in pulldown resistors that invoked -Suspend mode interface programmed powered Suspend mode (Power-Down Group bus, SA25-SA0, RSTDRV signal three-stated with pulldowns Suspend mode. This accommodates having bus, Card sockets, bus, interfaces left powered powered Suspend mode. Summary: These pins have built-in pulldown resistors that invoked -Suspend mode.
output drives programmable.
combination SD15-SD0 D31-D16 same pins requires signals pulled mode (for compatibility) pulled down mode (for consistency with D15-D0). Regardless mode pins input state (i.e., they still bidirectional driven outputs) pulled down Suspend mode. These signals pulled down automatically depending whether buffer enabled (CFG3), whether system Suspend mode not. Summary: These pins have built-in pulldown pullup resistors that invoked -Reset invokes pulldown resistors. -Suspend mode invokes pulldown resistors. -Operating (Hyper/High/Low/Temp Low-Speed modes): pins will have pullups buffer control signals enabled, have pulldowns otherwise.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] CASH0 CASH1 CASL0 CASL1 KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] {CFG0} {CFG1} {CFG2} {CFG3} Type STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD
State Table-Memory Interface1
Reset State TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PD I-PD I-PD I-PD I-PD Normal Operation B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD B-PD IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU Suspend State O[L][TS-PD] O[L][TS-PD] O[L][TS-PD] O[L][TS-PD] TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU TS-PD TS-PPD TS-PPD TS-PPD TS-PPD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD
Output Load Supply Drive (pF)
Power Down Group
Note
C-E3 C-E3 C-E3
C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3 C-E3
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] MA10 MA11 RAS0 RAS1 ROMCS0 ROMCS1 ROMRD ROMWR Type
State Table-Memory Interface (Continued)
Reset State Normal Operation Suspend State TS-PD TS-PD H[TS-PD] O[L][TS-PD] O[L][TS-PD] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] Power Down Group Note
Output Load Supply Drive (pF) C-E3 C-E3 C-E3 C-E3
Notes: states D31-D16 listed Table page RAS3-RAS0, CASH3-CASH0, CASL3-CASL0, Suspend state pins: -The signals remain active DRAM interface configured CAS-before-RAS refresh Suspend mode. -The signals will DRAM configured self-refresh Suspend mode. -Will three-stated with pulldown resistor DRAM interface programmed disabled DRAM powered down (Power-Down Group -Will affected this when signals that share pins with other functions (RAS3-RAS2, CASH3- CASH2, CASL3-CASL2) enabled come chip. -The signal will driven High (deasserted) when DRAM programmed left powered (Power-Down Group Summary: These pins have built-in pulldown resistors that invoked -Suspend mode DRAM interface programmed power-down Suspend (Power-Down Group pins enabled RAS/CAS RAS3-RAS2, CASH3-CASH2, CASL3-CASL2.
output drives programmable.
data D15-D0 built-in pulldown resistors that invoked when data signals inputs. Memory Address MA12 Suspend state pin: Will three-stated with pulldown resistor. This will work CAS-before-RAS refresh, self-refresh, DRAM powered down. Summary: This built-in pulldown resistor that invoked Suspend mode. Memory Address MA4-MA0 pins shared with power-on configuration signals reset state pins pulldown resistor these signals. This default configuration will choose: test mode 8-bit ROM/Flash memory accessed ROMCS0 with buffer-control signals disabled. pulldown resistors from they need overridden pullup resistors board other configurations needed. These pulldown resistors disabled after reset; they active during normal chip operation. configuration signals CFG0, CFG1, CFG2, CFG3, system uses default configuration, pulldown resistors will active again Suspend mode. external pullup resistors used board different configuration, pins with external pullups will three-state Suspend mode without pulldown resistors. reserved signal only used testing; should pulled system design. This will always three-state with pulldown resistor Suspend mode. Summary: Each built-in pulldown resistor that invoked -Reset -Suspend mode configuration being during reset (for CFG3-CFG0). -Suspend mode reserved signal MA4.
Microcontrollers Data Sheet
CFG2 supported microcontroller. Memory Address MA11-MA4 Suspend state pins: Will three-stated with pulldown resistor. This will work CAS-before-RAS refresh, self-refresh, DRAM powered down. Summary: These pins have built-in pulldown resistors that invoked Suspend mode. control signals have three programmable options Suspend mode: -Driven High (inactive) -Three-stated with pullup pulldown. This useful when left powered Suspend. board design should drive 3.3-V signals into device during Suspend, because this waste power. system designer could provide large pullup resistors each these signals board this configuration programmed. Three-stated with pulldown resistors when suspended with intent powering ROMs (Power-Down Group Summary: These pins have built-in pulldown resistors that invoked -Suspend mode; interface programmed powered Suspend mode (Power-Down Group
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] GPIO15 [PCMA_VPP2] GPIO16 [PCMB_VCC] Type
State Table-GPIOs/Parallel Port/PC Card Socket
Output Load Supply Drive (pF) Reset State I-PD I-PD I-PD I-PD I-PU I-PU I-PU Normal Operation I-PPD[O] I-PPD[O] I-PPD[O] I-PPD[O] I-PPU[O] I-PPU[O] I-PPU I-PPU[O] TS-PD I-PPU[O] TS-PD I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] I-PU I-PPU I-PPU[O] OD-PU[O] I-PPU[O] OD-PU[O] I-PPU[O] OD-PU[O] I-PPU[O] OD-PU[O] I-PPD[O] I-PPD[O] Suspend State I-PPD[O] I-PPD[O] I-PPD[O] I-PPD[O] I-PPU[O] I-PPU[O] I-PPUD I-PPU[O] H[TS-PD][TS] TS-PD I-PPU[O] H[TS-PD][TS] TS-PD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] I-PU[I-PD] I-PPUD I-PPU[O] OD-PU[OD-PD] H[TS-PD][TS] I-PPU[O] OD-PU[OD-PD] L[TS-PD] I-PPU[O] OD-PU[OD-PD] H[TS-PD][TS] I-PPU[O] OD-PU[OD-PD] H[TS-PD][TS] I-PPD[O] I-PPD[O] Power Down Group Note
GPIO17 [PCMB_VPP1] GPIO18 [PCMB_VPP2] GPIO19 [LBL2] GPIO20 [CD_A2] GPIO21 [PPDWE] Card Enabled) GPIO22 [PPOEN] Card Enabled) GPIO23 [SLCT] [WP_B] GPIO24 [BUSY] [BVD2_B] GPIO25 [ACK] [BVD1_B] GPIO26 [PE] [RDY_B] GPIO27 [ERROR] [CD_B] GPIO28 [INIT] [REG_B] GPIO29 [SLCTIN] [RST_B] GPIO30 [AFDT] [MCEH_B] GPIO31 [STRB] [MCEL_B] GPIO_CS13 [PCMA_VCC]
I-PU
[OD][O] [OD][O] [OD][O] [OD][O]
I-PU
I-PU
I-PU
I-PU
I-PU
OD-PU
OD-PU
OD-PU
OD-PU
I-PD I-PD
GPIO_CS14 [PCMA_VPP1]
Microcontrollers Data Sheet
Notes: shared GPIO20-GPIO15, GPIO_CS14-GPIO_CS13, Card battery signals: GPIO_CSxs, signals active Suspend mode: that they inputs before Suspend, they still inputs during Suspend (the GPIO_CSs used wake system); they outputs before Suspend, they still outputs during Suspend (the GPIO_CSs programmed change state mode). inputs, pullup pulldown signal disabled; disabled, disabled modes. When signal output, built-in resistors automatically disabled. When enabled, Latched Battery Detect function (LBL2) that shared GPIO19 output modes; there pullup pulldown resistors active. microcontroller, Card functions shared these pins programmable Card socket; multiplexing options explained earlier this document. Card power control (PCMA_VCC, PCMA_VPP1, PCMA_VPP2, PCMB_VCC, PCMB_VPP1, PCMB_VPP2), signals outputs each mode. second Card Detect (CD_A2): -Reset invokes pullup. -During normal operation, pullup resistor disabled register bit. -During Suspend mode, input will have pulldown Card Socket interface programmed powered Suspend mode (Power-Down Group socket programmed powered Suspend mode, input will have same state when operating: pullup programmable enabled not. Card signals MCEL_B, MCEH_B, RST_B, REG_B, CD_B, RDY_B, BVD1_B, BVD2_B, WP_B, CD_A2, PCMB_VPP2, PCMB_VPP1, PCMB_VCC, PCMA_VPP1, PCMA_VPP2, PCMA_VCC supported microcontroller. shared parallel port, Card Socket control, GPIO signals: -These signals default GPIO interface reset. parallel port Suspend mode, these signals programmable accommodate parallel port powered down. Card control microcontroller, these signals have same features Socket control signals. GPIOs, these signals handled specially Suspend, they remain same they were when chip active (i.e., they remain inputs with pullup enabled not, continue drive same value they were outputs). Summary: Shared parallel port/PC Card Socket B/GPIO signals: Built-in pullup pulldown resistors that invoked -Reset invokes pullups parallel port signals: pullups enabled mode. Outputs without pullup pulldowns mode. pullups enabled, unless parallel port programmed powered Suspend mode, which case pulldowns enabled. mode enabled parallel port, outputs driven their last value Suspend mode. Card Socket signals microcontroller only): outputs have pullups pulldowns; inputs have pullups that disabled programming bit. outputs driven inactive with pullups pulldowns unless Card Socket programmed powered Suspend mode; then outputs three-state with pulldown resistors; inputs will same they were when operating, with pullup resistor that disabled programming, unless Card Socket programmed powered Suspend mode (Power-Down Group which case inputs have pulldown resistors enabled. GPIO signals: Suspend: outputs they have pullups pulldowns; inputs they have pullups that disabled programming bit; change state when system goes Suspend.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] GPIO_CS5 [IOCS16] GPIO_CS6 [IOCHRDY] GPIO_CS7 [PIRQ1] GPIO_CS8 [PIRQ0] GPIO_CS9 [TC] GPIO_CS10 [AEN] GPIO_CS11 [PDACK0] GPIO_CS12 [PDRQ0] Type [STI]
State Table-GPIOs/ISA
Reset State I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PD Normal Operation I-PPU[O] I-PU I-PPU[O] I-PU I-PPU[O] I-PU I-PPU[O] I-PU I-PPU[O] I-PPU[O] I-PPU[O] I-PPD[O] I-PD Suspend State I-PPU[O] I-PU[I-PD] I-PPU[O] I-PU[I-PD] I-PPU[O] I-PU[I-PD] I-PPU[O] I-PU[I-PD] I-PPU[O] TS-PD I-PPU[O] TS-PD I-PPU[O] H[TS-PD][TS] I-PPD[O] I-PD
Output Load Supply Drive (pF)
Power Down Group
Note
Microcontrollers Data Sheet
Notes: shared GPIO_CS12-GPIO_CS5 signals: GPIO_CS signals, they active Suspend mode: that they inputs before Suspend, they still inputs during Suspend (they used wake system); they outputs before Suspend, they still outputs during Suspend (they programmed change state mode). inputs, pullup pulldown signal disabled; disabled, disabled modes. When signal output, built-in resistors automatically disabled. function each programmable functional group: that system choose PIRQ0 still pins GPIO_CSxs (the multiplexing options explained elsewhere this document). signals, these pins programmable support system with peripherals powered down Suspend mode (Power-Down Group those signals that High when deasserted, there option three-state them with built-in resistors, external resistor placed board pull them Summary: GPIO_CS12: Built-in pulldown resistor that invoked -Reset -ISA signal enabled this (the will PDRQ0). -The pulldown disabled this being GPIO_CS output. -The pulldown programmed disabled when GPIO_CS input. Summary: GPIO_CS11: Built-in pullup pulldown resistors that invoked -Reset invokes pullup. -When enabled signal PDACK0: normal operation, this signal output pullup pulldown needed. pulldown invoked Suspend mode programmed powered Suspend (PowerDown Group programmed powered down Suspend, then this signal three-state without built-in pullup pulldown resistor. -When enabled GPIO_CS11 signal: output, pullup pulldown disabled modes, these GPIO_CSx signals active Suspend. input, pullup programmed enabled disabled; this will then state modes, including Suspend. Summary: GPIO_CS10-GPIO_CS9: Built-in pullup pulldown resistors that invoked -Reset invokes pullups. -When enabled signals normal operation, these signals outputs pullup pulldown needed. pulldowns invoked Suspend mode. -When enabled GPIO_CS10-GPIO_CS9 signals: output, pullup pulldown disabled modes, these GPIO_CS signals active Suspend. input, pullup programmed enabled disabled; this will then state modes, including Suspend. Summary: GPIO_CS8-GPIO_CS5: Built-in pullup pulldown resistors that invoked -Reset invokes pullups. -When enabled PIRQ1-PIRQ0, IOCHRDY, IOCS16: normal operation Suspend, these signals inputs pullup resistors active. pulldowns invoked Suspend mode interface programmed power Suspend (Power-Down Group -When enabled GPIO_CS8-GPIO_CS5 signals: output, pullup pulldown disabled modes, these GPIO_CSx signals active Suspend. input, pullup programmed enabled disabled; this will then state modes, including Suspend.
Microcontrollers Data Sheet
Table State Table-GPIOs/System Data (SD) Buffer Control
Signal Name [Alternate Function] GPIO_CS2 [[DBUFRDL]] GPIO_CS3 [[DBUFRDH]] GPIO_CS4 [[DBUFOE]] KBD_ROW13 [[R32BFOE]] Type [[O]] [[O]] [[O]] STI-OD Output Load Supply Drive (pF) Reset State I-PU I-PU I-PU I-PU Normal Operation I-PPU[O] I-PPU[O] I-PPU[O] IOD-PU Suspend State I-PPU[O] TS-PD I-PPU[O] TS-PD I-PPU[O] H[TS-PD][TS] I-PU H[TS-PD][TS] Power Down Group Note
Notes: data buffer control signals shared with GPIO_CS4-GPIO_CS2 signals with keyboard signal: When data buffer control signals enabled pins, they will drive inactive during Suspend mode, three-state without resistors allow external resistor three-state with pulldown support powering data buffer. Summary: Built-in pullup pulldown resistors that invoked -Reset invokes pullup. -When buffer control invoked configuration pin, these pins outputs without pullups pulldowns. -When buffer control enabled Suspend mode, DBUFRDH DBUFRDL three-state with pulldowns enabled; DBUFOE three options: (inactive) with pullup pulldown. with pulldown programmed buffer powered Suspend mode (Power-Down Group with pulldown programmed buffer powered Suspend mode -When enabled GPIO_CS4-GPIO_CS2 signals: output, pullup pulldown disabled modes, these GPIO_CS signals active Suspend. input, pullup programmed enabled disabled. This will then state modes, including Suspend. This data buffer control signal (R32BFOE) shared with keyboard signal: When data buffer control signals enabled pins, they will drive inactive during Suspend mode, three-state without resistors allow external resistor three-state with pulldown support powering data buffer. Summary: KBD_ROW13/R32BFOE: Built-in pullup pulldown resistors that invoked -Reset invokes pullup. R32BFOE, this output without pullup pulldown. -When buffer control enabled Suspend mode, R32BFOE three options: (inactive) with pullup pulldown. with pulldown programmed buffer powered Suspend mode. with pulldown programmed buffer powered Suspend mode -When enabled keyboard signal, this signal pullup enabled times.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] GPIO_CS0 GPIO_CS1 Type
State Table-GPIOs
Reset State I-PU I-PU Normal Operation I-PPU[O] I-PPU[O] Suspend State I-PPU[O] I-PPU[O] Power Down Group Note
Output Load Supply Drive (pF)
Notes: GPIO_CS signals become inputs Suspend mode with either pullup resistor devices that left powered, pulldown resistor devices that powered off. Summary: GPIO_CS1-GPIO_CS0: Built-in pullup pulldown resistors that invoked Reset invokes pullup. When enabled GPIO_CS1-GPIO_CS0 signals: output, pullup pulldown disabled modes, these GPIO_CSxs active Suspend. input, pullup programmed enabled disabled; this will then state modes, including Suspend.
Table
Signal Name [Alternate Function] SOUT Type
State Table-Serial Port
Reset State I-PU I-PU I-PU I-PU I-PU Normal Operation I-PU [I-PD] I-PU [I-PD] I-PU [I-PD] [TS-PD] I-PU [I-PD] [TS-PD] I-PU [I-PD] [TS-PD] Suspend State I-PU[I-PD] I-PU[I-PD] I-PU[I-PD] TS-PD I-PU[I-PD] TS-PD I-PU[I-PD] TS-PD Power Down Group Note
Output Load Supply Drive (pF)
Notes: serial port output signals three-state with built-in pulldown resistors Suspend mode. serial port input signals left inputs with pullups Suspend when serial device left powered. they configured inputs with pulldown resistors serial device powered (Power-Down Group Summary: serial port output pins have built-in pulldown resistors that invoked Suspend mode. Summary: serial port input pins have built-in pullup pulldown resistors that invoked -Reset invokes pullup resistors. -Operating: pullup resistors enabled. -Suspend mode invokes pulldown resistors serial interface programmed powered Suspend (PowerDown Group otherwise there pullup resistors Suspend mode.
Table
Signal Name [Alternate Function] SIRIN SIROUT Type
State Table-Infrared Interface
Reset State I-PD Normal Operation I-PPD Suspend State I-PPD TS-PD Power Down Group Note
Output Load Supply Drive (pF)
Notes: serial infrared interface output input settle Suspend states that allow device powered off. output three-state with built-in pulldown resistor, input built-in pulldown resistor. pulldown resistor input (SIRIN) programmed disabled during normal operation Suspend mode. Summary: serial infrared input built-in pulldown resistor that invoked -Reset invokes pulldown resistor. -The pulldown resistor then programmable there not.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] KBD_COL0 [XT_DATA] KBD_COL1 [XT_CLK] KBD_COL2/ PIRQ3 KBD_COL3/ PIRQ4 KBD_COL4/ PIRQ5 KBD_COL5/ PIRQ6 KBD_COL6/ PIRQ7 KBD_COL7 KBD_ROW0 [CASL2] KBD_ROW1 [CASL3] KBD_ROW2 [CASH2] KBD_ROW3 [CASH3] KBD_ROW4 [RAS2] KBD_ROW5 [RAS3] KBD_ROW6 [MA12] KBD_ROW7 [PDACK1] KBD_ROW8 [PDRQ1] KBD_ROW9 [PIRQ2] KBD_ROW10 [BALE] KBD_ROW11 [SBHE] KBD_ROW12 [MCS16] KBD_ROW13 [[R32BFOE]] Type OD-STI OD-STI OD-STI OD-STI OD-STI OD-STI OD-STI OD-STI STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD STI-OD
State Table-Keyboard Interface
Reset State ODPU ODPU ODPU ODPU ODPU ODPU ODPU ODPU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU I-PU Normal Operation IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD I-PPUD IOD-PPUD IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU IOD-PU I-PD IOD-PU I-PU IOD-PU IOD-PU IOD-PU I-PU IOD-PU Suspend State IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PPUD[I-PD] IOD-PPUD I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU O[L][TS-PD] I-PU TS-PD I-PU H[TS-PD][TS] I-PU I-PD I-PU I-PU[I-PD] I-PU TS-PD I-PU H[TS-PD][TS] I-PU I-PU[I-PD] I-PU H[TS-PD][TS]
Output Load Supply Drive (pF) P-C,E P-C,E P-C,E
Power Down Group
Note
Microcontrollers Data Sheet
Notes: keyboard column signals shared with programmable IRQs keyboard signals. keyboard column signals keyboard signals, they inputs open drain outputs with pullup pulldown resistors normal operation Suspend mode. Each column signal individually programmable pullup pulldown keyboard extended registers. IRQs, pins inputs with built-in pullup pulldown resistors (use same registers keyboard controller enable pullups pulldowns). During Suspend mode, they stay inputs with pullup pulldown. Power-Down Group enabled powered down Suspend mode identifying that these signals being used IRQs, they will have pulldown resistors activated. There programmable make these signals IRQs beyond extended register interrupt controller that maps particular IRQ. system must these IRQs, must set, notifying chip, that they have pulldown resistors invoked Suspend mode. Summary: keyboard column keyboard signals: -Pullup pulldown resistor depending setting Keyboard Column Pullup/Pulldown register keyboard controller. Summary: programmable signals: -Pullup pulldown resistors during normal operation Suspend (depending configuration register keyboard controller. -Pulldown resistors during suspend Power-Down Group (the bus) enabled power-down Suspend, indicating that these signals used IRQs need pulled down Suspend. RAS3-RAS2, CASH3-CASH2, CASL3-CASL2 Suspend state pins: -The signals remain active DRAM interface configured CAS-before-RAS refresh Suspend mode. -The signals will DRAM configured self-refresh Suspend mode. -Will three-stated with pulldown resistor DRAM interface programmed disabled DRAM powered down (Power-Down Group -Will affected this when signals that share pins with other functions enabled come chip. Summary: These pins have built-in pulldown resistors that invoked -Suspend mode DRAM interface programmed power-down Suspend (Power-Down Group pins enabled RAS/CAS RAS3-RAS2, CASH3-CASH2, CASL3-CASL2. Memory Address MA12 Suspend state pin: Will three-stated with pulldown resistor. This will work CAS-before-RAS refresh, self-refresh, DRAM powered down. Summary: This built-in pulldown resistor that invoked Suspend mode. data buffer control signal R32BFOE that shared with keyboard signal: When data buffer control signals enabled pins, they will drive inactive during Suspend mode, three-state without resistors allow external resistor three-state with pulldown support powering data buffer. Summary: KBD_ROW13/R32BFOE: Built-in pullup pulldown resistors that invoked -Reset invokes pullup. R32BFOE, this output without pullup pulldown. -When buffer control enabled Suspend mode, R32BFOE three options: (inactive) with pullup pulldown. with pulldown programmed buffer powered Suspend mode. with pulldown programmed buffer powered Suspend mode -When enabled keyboard signal, this signal pullup enabled times.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] BVD1_A BVD2_A CD_A ICDIR MCEH_A [[BNDSCN_TMS]] MCEL_A [[BDNSCN_TCK]] RDY_A REG_A [[BNDSCN_TDO]] RST_A [[BNDSCN_TDI]] WAIT_AB WP_A Type [[I]] [[I]] [[O]] [[I]]
State Table-PC Card Socket
Reset State I-PU I-PU I-PU I-PU I-PU I-PU Normal Operation I-PPU I-PPU I-PPU [I-PD] [I-PD] I-PPU [I-PD] I-PPU I-PPU Suspend State I-PPUD I-PPUD I-PPUD H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] H[TS-PD][TS] I-PPUD H[TS-PD][TS] L[TS-PD] I-PPUD H[TS-PD][TS] I-PPUD Power Down Group Note
Output Load Supply Drive (pF)
Notes: microcontroller only, Card control signals Socket pullup resistors input signals built disabled external pullups necessary (the external pullups different power plane). Suspend mode, signals configured for: card plugged (inputs terminated with internal resistors), card plugged powered (the output signals drive inactive), card plugged powered (the inactive High output signals three-stated pullup resistors should board), card plugged powered (the signals terminated with pulldown resistors) (Power-Down Group Summary: outputs built-in pulldown resistors that invoked -Suspend Card Socket programmed powered Suspend (Power-Down Group -These pulldowns normal operation. These driven outputs. Summary: inputs built-in pullup pulldown resistors that invoked -Reset invokes pullups. -During normal operation, pullup resistors disabled register bit. -During Suspend mode, inputs will have pulldowns Card Socket interface programmed powered Suspend mode (Power-Down Group socket programmed powered Suspend mode, inputs have same state when operating: pullups programmable enabled not. Card signals MCEL_A, MCEH_A, RST_A, REG_A, CD_A, RDY_A, BVD1_A, BVD2_A, WP_A, WAIT_AB, ICDIR supported microcontroller.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] [VL_LCLK] [VL_BE1] LCDD0 [VL_RST] LCDD1 [VL_ADS] LCDD2 [VL_W/R] LCDD3 [VL_M/IO] LCDD4 [VL_LRDY] LCDD5 [VL_D/C] LCDD6 [VL_LDEV] LCDD7 [VL_BE3] LVDD [VL_BLAST] LVEE [VL_BRDY] [VL_BE2] [VL_BE0] Type
State Table-Graphics Controller/VESA Local Control
Output Load Supply Drive (pF) Reset State TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PD TS-PU TS-PU TS-PD TS-PD Normal Operation O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] TS-PD[O] O[TS-PD] O[TS-PD] TS-PD[O] O[TS-PD] O[TS-PD] O[TS-PU] O[TS-PU] O[TS-PU] O[TS-PD] O[TS-PD] O[TS-PD] O[TS-PD] Suspend State TS-PD TS-PD TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] TS-PD I[I-PD] TS-PD H[TS-PD] TS-PD I[I-PD] TS-PD H[TS-PD] H[TS-PD] I[I-PD] TS-PD H[TS-PD] TS-PD H[TS-PD] Power Down Group
Note
Microcontrollers Data Sheet
Notes: shared graphics controller interface VESA local pins: These signals default three-state with pulldown resistors remain this until VL-bus interface selected (all except LVEE LVDD). When graphics controller enabled microcontroller, signals will three-state with pulldowns whenever enabled. This allows powered mode, prevents damage having powered when timing signals correct. Suspend these signals three-state with pulldowns. cannot driven Suspend. When VESA local interface enabled, signals will become inputs outputs necessary VL-bus support. Suspend, signals support leaving device powered (Power-Down Group Summary: control signals/VESA local control signals (all except LVEE LVDD) have built-in pulldown resistors that invoked -Reset invokes pulldowns. -Graphics controller disabled VL-bus disabled invokes pulldowns. -VL-bus enabled interface programmed power-down Suspend mode invokes pulldowns (Power-Down Group -Graphics controller enabled enabled. pins outputs with termination. -Graphics controller enabled disabled. pins three-state with pulldowns. -VL-bus enabled Suspend mode. pulldowns enabled. Summary: LVEE LVDD have built-in pullup pulldown resistors that invoked -Reset invokes pullups. -VL-bus enabled interface programmed power-down Suspend mode invokes pulldowns Suspend mode (Power-Down Group -Graphics enabled. Drive High Suspend. -Graphics enabled. Both pins outputs without pullups pulldowns. -VL-bus enabled. pullups pulldowns normal operation. graphics controller signals LCDD7-LCDD0, SCK, FRM, LVEE, LVDD supported microcontroller.
Microcontrollers Data Sheet
Table
Signal Name [Alternate Function] 32KXTAL1 32KXTAL2 ACIN BBATSEN [CLK_IO] BNDSCN_EN LF_HS LF_INT LF_LS LF_VID RESET SPKR SUS_RES/ KBD_ROW14 STI[B] STI/STI Type
State Table-Miscellaneous
Reset State Normal Operation Suspend State Power Down Group Note
Output Load Supply Drive (pF) VRTC VRTC VRTC AVCC AVCC AVCC AVCC
I-PD I-PD Analog Analog Analog Analog
I-PD I[O] I-PD Analog Analog Analog Analog
I-PD I[TS-PD] I-PD Analog Analog Analog Analog TS-PD
Notes: 32-kHz crystal signals active modes. RESET signal enabled input modes reset whole chip. BBATSEN signal active during reset sense state backup battery. Summary: pullups pulldowns these pins. LF_VID signal supported microcontroller.
Microcontrollers Data Sheet
Table
State Table-Power1 Ground
Type Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal Thermal
Signal Name (Alternate Function)
Microcontrollers Data Sheet
Table
GND_A
State Table-Power1 Ground (Continued)
Type Thermal Thermal Thermal Thermal Thermal Thermal Thermal Analog Logic Logic Logic Logic
Signal Name (Alternate Function)
Microcontrollers Data Sheet
Table
VCC_RTC VCC_A VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU
State Table-Power1 Ground (Continued)
Type Analog
Signal Name (Alternate Function)
Notes: signal descriptions under Reset Power subheading Signal Description table beginning page additional information about pins.
Microcontrollers Data Sheet
SIGNAL DESCRIPTIONS
descriptions Table organized alphabetical order within functional group listed here. System Interface page Configuration Pins page Memory Interface page VL-Bus Interface page Power Management page Clocks page Parallel Port page Serial Port page Keyboard Interfaces page General-Purpose Input/Output page Serial Infrared Port page Card Controller Microcontroller Only) page Graphics Controller Microcontroller Only) page Boundary Scan Test Interface page Reset Power page
Table
Signal System Interface Type Description
Signal Description Table
Address Enable indicates that current address active SA25-SA0 address memory address, that current cycle cycle. devices should this signal decoding their addresses, should respond when this signal asserted. When asserted, PDACK1- PDACK0 signals used select appropriate device transfer. also asserted when cycle occurring internal chip. microcontroller, also asserted accesses Card space prevent devices from responding IOR/IOW signal assertions because these signals shared between Card interfaces.
BALE
Address Latch Enable driven beginning cycle with valid address. This signal used external devices latch address current cycle. BALE also asserted accesses Card interfaces (memory I/O) microcontroller only) cycles. This prevents device from responding cycle based previously latched address. Data Buffer Output Enable controls output enable external transceiver required drive peripheral data local 32-bit DRAM modes. High Byte Data Buffer Direction Control controls direction data flow through external transceiver required drive peripheral data local 32-bit DRAM mode. This control signal upper bits data bus. Byte Data Buffer Direction Control controls direction data flow through external transceiver required drive peripheral data local 32-bit DRAM mode. This control signal lower bits data bus. Channel Ready should driven open-drain devices. When pulled during access, wait states inserted current cycle. This internal weak pullup that should supplemented stronger external pullup (usually faster rise time. Chip Select targeted device drives this signal active early cycle request 16-bit transfer. Read Command indicates that current cycle read from currently addressed device. When this signal asserted, selected device drive data onto data bus. This signal also shared with Card interface microcontroller. Write Command indicates that current cycle write currently addressed device. When this signal asserted, selected device latch data from data bus. This signal also shared with Card interface microcontroller. Memory Chip Select indicates control logic that targeted memory device 16-bit-wide device.
DBUFOE DBUFRDH
DBUFRDL
IOCHRDY
IOCS16
MCS16
Microcontrollers Data Sheet
Table
Signal MEMR Type Description
Signal Description Table (Continued)
Memory Read Command indicates that current cycle read currently addressed memory device. When this signal asserted, memory device drive data onto data bus. Memory Write Command indicates that current cycle write currently addressed memory device. When this signal asserted, memory device latch data from data bus. Programmable Acknowledge signals each mapped seven available channels. They driven active (Low) back initiator acknowledge corresponding requests. Programmable Requests each mapped seven available channels. They asserted active (High) initiator request service from controller. Programmable Interrupt Requests each mapped available 8259 interrupt channels. They asserted when peripheral requires interrupt service. (Rising Edge/Active High Trigger) System Reset reset signal. When this signal asserted, connected devices reinitialize their reset state. This signal should confused with internal RESET SRESET signals. System Address outputs physical memory port latched addresses. used external peripheral devices other than main system DRAM. addition, this local address local mode. System Byte High Enable driven active when high data byte transferred upper bits data bus. System Data shared between ISA, 16-bit ROM/Flash memory, Card peripherals microcontroller only) directly connected these devices. addition, these signals upper word local data bus, 32-bit DRAM interface, 32-bit interface. these modes, system data generated external buffer connected controlled buffer control signals provided. Speaker, Digital Audio Output controls external speaker driver. generated from internal 8254-compatible timer Channel output ANDed with Port 0061h[1] (Speaker Data Enable); microcontroller, Card speaker signals exclusively ORed with each other speaker control function timer generate SPKR signal. Terminal Count driven from controller pair indicate that transfer count currently active channel reached zero, that current cycle last transfer. Boundary Scan Enable enables boundary scan functions. When this High, boundary scan interface enabled. When this Low, boundary scan functions disabled pins configured their default functions. This must held during reset normal operation. Configuration Pins select data width physical device(s) selected ROMCS0 (i.e., 16-, 32-bit-wide). These pins sampled deassertion RESET. Configuration selects whether system will boot from Card Socket memory card from device attached ROMCS0. This sampled deassertion RESET. This supported microcontroller. Configuration enables buffer control signals, DBUFOE, DBUFRDH, DBUFRDL. This sampled deassertion RESET.
MEMW
PDACK1-PDACK0
PDRQ1-PDRQ0
PIRQ7-PIRQ0
RSTDRV
SA25-SA0
SBHE SD15-SD0
SPKR
Configuration Pins BNDSCN_EN
CFG1-CFG0 CFG2
CFG3
Microcontrollers Data Sheet
Table
Signal Memory Interface CASH3-CASH0 Type Description
Signal Description Table (Continued)
Column Address Strobe High indicates DRAM devices that valid column address asserted lines. These signals banks (Banks CASH3-CASH2 high word; CASH1-CASH0 word.
CASL3-CASL0
Column Address Strobe indicates DRAM devices that valid column address asserted lines. These signals even banks (Banks CASL1-CASL0 word; CASL3-CASL2 high word.
D31-D0 MA12-MA0
Data used DRAM local cycles. This also used when interfacing 32-bit ROMs. Memory Address: DRAM column addresses multiplexed onto this bus. addresses driven onto this valid upon falling edge RAS. Column addresses driven onto this valid upon falling edge CAS. Write Enable indicates active write cycle DRAM devices. This signal also used three-state DRAMs read cycles. 32-Bit Buffer Output Enable provides buffer enable signal external transceivers word interface. This signal automatically provided when ROMCS0 interface configured (the configuration done using either CFG1-CFG0 index 20h[1-0]). Once ROMCS0 configured bit, accesses 32-bit devices ROMCS2-ROMCS0 result assertion R32BFOE signal. Address Strobe indicates DRAM devices that valid address asserted lines. Chip Selects active outputs that provide chip select BIOS and/or ROM/Flash memory array. After power-on reset, ROMCS0 chip select will active accesses into 64-Kbyte segment that contains boot vector, address 3FF0000h 3FFFFFFh. ROMCS0 driven active during linear (direct) address decode certain addresses high memory (00A0000h-00FFFFFh) region. default, direct-mapped accesses 64-Kbyte region from 00FFFF0h 00FFFFFh enabled support Legacy PC/AT BIOS. This area known aliased boot vector. also activated accessing Memory Management System (MMS) page that points ROM0 address space. ROMCS1 activated only when accessing page that points third, MMS-mappable ROMCS2 signal available reconfiguring chip's General Purpose Input Output (GPIO) pins this function also requires access devices connected Read indicates that current cycle read currently selected device. When this signal asserted, selected device drive data onto data bus. Write indicates that current cycle write currently selected device. When this signal asserted, selected device latch data from data bus. Local Address Strobe asserted indicate start VL-bus cycle. always strobed clock period. address status lines valid rising edge VL_LCLK, which samples this signal Low. Local Byte Enables indicate which byte lanes 32-bit data involved with current VL-bus transfer. Local Burst Last asserted indicate that next VL_BRDY assertion will terminate current VL-bus transfer.
R32BFOE
RAS3-RAS0 ROMCS2-ROMCS0
ROMRD ROMWR VL-Bus Interface VL_ADS
VL_BE3-VL_BE0 VL_BLAST
Microcontrollers Data Sheet
Table
Signal VL_BRDY Type Description
Signal Description Table (Continued)
Local Burst Ready asserted VL-bus target indicate that terminating current burst transfer. chip samples this signal rising edge VL_LCLK. VL_BRDY should asserted VL_LCLK period burst transfer. VL_LRDY asserted same time VL_BRDY, VL_BRDY ignored VL-bus transfer terminated. Local Data/Code Status driven indicate that code being transferred. High this signal indicates that data being transferred. Local Memory/I/O Status driven indicate transfer. High this signal indicates memory transfer. Local Write/Read Status driven indicate read transfer. High this signal indicates write. Cycle Initiated Interrupt Acknowledge Halt/Special Cycle Read Write Code Read Reserved Memory Read Memory Write VL_M/IO VL_D/C VL_W/R
VL_D/C VL_M/IO VL_W/R
VL_LCLK
Local Clock VL-bus clock. used VL-bus target timing references. This signal phase with internal CPU's clock input. (Rising Edge Active) Local Device Select asserted VL-bus target indicate that accepting current transfer indicated address status lines. VL-bus target asserts this signal function address status presented bus. Local Ready asserted VL-bus target indicate that terminating current cycle. This signal sampled chip rising edge VL_LCLK. Local Reset VL-bus master reset. controlled with index 14h[4]. Supply Active indicates system that being powered from source. When asserted, this signal disable power management functions configured so). Battery Detects indicate chip current status system's primary battery pack. BL0-BL2 indicate various conditions battery conditions change. These inputs used force system into power saving modes when activated (Low-going Edge). Latched Battery Detect driven latched low-going edge input indicate system that chip been forced into Suspend mode battery dead indication from signal. cleared "all clear" indicators that allow system resume after battery dead indication. Suspend/Resume Operation: When chip Hyper-Speed, High-Speed, Low-Speed, Standby mode, software-configurable edge this cause internal logic enter Suspend mode. When Suspend, software-configurable edge this cause chip enter High-Speed Low-Speed mode. choice edge configured using SUS_RES C
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