IFIN Transceiver Subsystem AD6402 FUNCTIONAL BLOCK DIAGRAM

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IFIN Transceiver Subsystem AD6402 FUNCTIONAL BLOCK DIAGRAM

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FEATURES On-Chip Regulator Demodulator On-Chip Trims Excellent Sensitivity 28-Lead SSOP Package APPLICATIONS DECT/PWT/WLAN TDMA FM/FSK Systems
IFIN
Transceiver Subsystem AD6402
FUNCTIONAL BLOCK DIAGRAM
RSSI LIMITER/FILTER DEMOD TXOUT TXOUTB CFILT DOUT DFILP
AD6402
OFFSET COMP MODE CONTROL
PLLOUT
REFSEL COFF REFIN
VOLTAGE REGULATOR
FMMOD2 VREF FMMOD1
GENERAL DESCRIPTION
AD6402 complete transceiver subsystem high rate radio systems employing modulation. optimized time domain multiple access (TDMA) systems with communications rates approximately MBPS. AD6402 integrates functions, including VCOs drop-out voltage regulator. AD6402 operates directly from unregulated battery supply provides regulated voltage output which used supply regulation companion chip such AD6401. AD6402 transceiver consists mixer, integrated bandpass filter, limiter with RSSI detection, VCO, demodulator dropout voltage regulator. receive, downconverts signal range second frequency, this frequency being determined demodulator reference divide ratios. then filters, amplifies, demodulates this signal. AD6402 provides filtered baseband
VREG VBATT SLREF
CTL1.3
MODOUT
data output. transmit, accepts Gaussian Frequency Shift Keying (GFSK) baseband signal, low-pass filters signal required using on-chip modulates varying bias voltage off-chip varactor diode used tank circuit. AD6402 multiple power-down modes maximize battery life. operates over temperature range -25°C +85°C packaged JEDEC standard 28-lead smallshrink outline (SSOP) surface-mount package.
REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices. Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Site: http://www.analog.com Fax: 617/326-8703 Analog Devices, Inc., 1997
AD6402-SPECIFICATIONS
AD6402ARS
Parameter BANDPASS FILTER Center Frequency Rejection Conditions REFIN 13.824 MHz, REFSEL <0.2 20.736 Units
Stop Band Rejection RECEIVER Sensitivity RSSI High Slope Output Impedance DEMODULATOR Gain Offset Lock Time DATA FILTER Gain Slew Rate Gain Bandwidth Output Swing Output Swing High Output Impedance Frequency Phase Noise Output Power Harmonic Harmonic TRANSMIT FILTER Open Loop Gain Unity Gain Bandwidth Output Slew Rate Minimum Input Voltage Maximum Input Voltage Minimum Output Voltage Maximum Output Voltage POWER CONTROL Logical High Threshold Logical Threshold Turn-On Response Time
Modulated kHz, Deviation 0.5, Demod Output VOUT VOUT Figure
-200 VCC-0.2 -139 VCC-0.2 VCC-0.2 2.95 1.55 +200
mV/dB V/MHz
Data Filter Output Referred SLREF From SLEEP Mode From RXLOCK Mode
CLOAD CLOAD
V/µs dBc/Hz V/µs
Note Offset Differential RLOAD
CLOAD CLOAD
Steady State
VOLTAGE REFERENCE
SLREF SUPPLY REGULATOR Output Voltage Turn-On Time Line Regulation Load Regulation POWER SUPPLY Supply Current
Battery Voltages from Settling, LOAD Battery Step; Settling Step; Settling 2.85 RXLOCKP RXLOCK RXDEMOD TRANSMIT STANDBY
2.75
SLEEP
NOTES Using test tank circuit shown. Specifications subject change without notice.
REV.
AD6402
RECOMMENDED OPERATING CONDITIONS
VBAT V-4.5 IFVCC1, IFVCC2, PLLVCC .2.85 Operating Temperature Range -25°C +85°C
ABSOLUTE MAXIMUM RATINGS*
CONFIGURATION
TXOUTB MODOUT FMMOD2 FMMOD1 VCOGND
TXOUT REFSEL IFVCC1 IFIN
Supply Voltage +5.5 Storage Temperature Range -65°C +150°C Lead Temperature, Soldering sec) +300°C
*Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended rating conditions extended periods affect device reliability. Thermal Characteristics: 28-lead SSOP package: 109°C/W.
AD6402
IFGND
VIEW RSSI VREG (Not Scale) IFVCC2 VBAT CTL3 CTL2 CTL1 CFILT COFF PLLGND PLLVCC SLREF DOUT DFILP PLLOUT REFIN
ORDERING GUIDE
REXT
Model AD6402ARS AD6402ARS-REEL
Temperature Range -25°C +85°C -25°C +85°C
Package Description 28-Lead SSOP 28-Lead SSOP
FUNCTION DESCRIPTIONS
Mnemonic TXOUTB MODOUT FMMOD2 FMMOD1 VCOGND VREG VBAT CTL3 CTL2 CTL1 CFILT COFF REXT REFIN PLLOUT DFILP DOUT SLREF PLLVCC PLLGND IFVCC2 RSSI IFGND IFIN IFVCC1 REFSEL TXOUT
Function Transmit Buffer Inverting Output Frequency Modulator Filter Output Frequency Modulator Filter Noninverting input Frequency Modulator Filter Inverting input Ground Tank Connection Regulated Supply Output (Supplies Internal VCO, Mode Control, Bandgap Reference, COFF Buffer) Battery Supply Voltage Input Internal Regulator COFF Charge Pump Mode Control Input CMOS Logical Level Mode Control Input CMOS Logical Level Mode Control Input CMOS Logical Level Demodulator Loop Filter Capacitor Demodulator Frequency Offset Voltage Track/Hold Capacitor External Current-Setting Resistor Baseband Reference Frequency Input, p-p, Coupled Demodulator Output Data Filter Voltage-Follower Input Data Filter Voltage-Follower Output Demodulator Output Reference Voltage Demodulator Data Filter Supply Input Demodulator Data Filter Ground Limiter Supply Input RSSI Output Stage, Mixer, Band Pass Filter, Buffer, Amp, Mode Control, Regulator Ground Mixer Input, Mixer, Limiter Filter, Buffer Reference Frequency Select; Reference Frequency, CMOS Logical Level Input Transmit Buffer Output
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although AD6402 features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
WARNING!
SENSITIVE DEVICE
REV.
AD6402
1.2k VTUNE 4.7nF 47pF 39nH VCOGND
AD6402
100pF 180pF MODOUT TXMOD
1204-37
1204-36 TXIF+ TXIF-
TXOUT
FMMOD2 FMMOD1
TXOUTB
150pF VCCI
Figure
OVERVIEW
AD6402 forms basis highly integrated transceiver with benefits increased sensitivity wide dynamic range that dual-conversion architecture provides. contains dropout voltage regulator isolate demodulator VCOs from variation battery voltage, such power-supply transients caused AD6402 also provides control circuitry that allows subcircuits turned necessary minimize power consumption.
Operation During Receive
equal frequency plus frequency demodulator input defined reference clock divider ratios. transmit uses external tank circuit. This signal upconverted transmit frequency mixer section radio. Using transmit prevents problems: feedback from frequency does cause distortion modulating circuit because frequencies widely separated tank circuit optimized modulation linearity. output transmit passes through buffer amplifier leaves AD6402 optional filter between ICs. output filter then transmit upconversion mixer conversion final frequency.
Onboard Voltage Regulation
AD6402 contains second mixer, integrated second-IF bandpass filter, logarithmic-limiting amplifier, demodulator. bandpass filter usually required input order provide channel selectivity. placement filter signal path between AD6402 section partitioning receiver's receive circuits minimizes leakage around filter maximizes isolation. output filter enters AD6402 second downconversion mixer. This mixer high gain, doublybalanced Gilbert-cell type. mixer downconverts signal second which reference frequency. This multiple determined state REFSEL pin. on-chip section bandpass filter provides additional selectivity provide attenuation adjacent channels. control voltage output demodulator tunes this filter second bandpass filter's output enters successive-detection logarithmic-limiting amplifier. RSSI detectors distributed across entire strip, including mixer, provide RSSI range. strip's limiting gain also exceeds RSSI signal low-pass filtered proceeds off-chip baseband subsystem. limited output logarithmic amplifier enters demodulator, which provides demodulation received signal. uses integrated with external components.
Operation During Transmit
AD6402 contains dropout voltage regulator specifically isolate VCOs synthesizer from voltage "kick" that occurs when power amplifier switches battery voltage abruptly drops. AD6402 uses integral vertical pass transistor. regulator AD6402 supplies voltage VCOs both section AD6402. other sections AD6402 should powered from independently regulated source 2.85 Since VCOs isolated from this source, possible problems supply pushing considerably reduced.
Frequency Control
AD6402 requires external synthesizer provide control voltages tank circuit VCO. Normally this will section dual synthesizer controlling both frequency generation. recommended that section implement channel selection transmit receive; AD6402 therefore operate fixed frequency. This accomplishes goals: first, being modulated optimized modulation linearity optimized tuning range, second, feedback from will couple into modulating circuit cause spurious responses. sections AD6402 powered down necessary minimize power consumption maximize battery life.
transmit signal path consists low-pass filter that user configured antialiasing baseband transmit signal. VCO, which should tuned frequency equal receive frequency plus desired demodulator input frequency, open-loop modulated transmit signal schemes. receive mixer uses high side mixing therefore should frequency
REV.
AD6402
Table Power Management Functionality
CTL2
CTL3
BIAS
LOCK
DMOD
MODE SLEEP STANDBY RXLOCK RXDMOD TRANSMIT RXLOCKP
AD6402 operating modes: SLEEP, STANDBY, RXLOCK, RXDMOD, TRANSMIT RXLOCKP. These summarized Table blocks referred Table shown also Figure These modes described follows:
IFIN
IFVCC1
IFVCC2
RSSI
DOUT
SLEEP: STANDBY: RXLOCK:
entire device shut down. functions except regulator shut down. device locks local reference clock using lock PLL. lock charge pump dividers powered also powered this mode lock charge pump loop dividers shut down. receive mixer, strip, reference demodulator powered
IFGND
DMOD
DFLIP
PLLOUT VBAT VREG PLLVCC PLLGND
RXDMOD:
SLREF
BIAS
REXT CFILT COFF
TRANSMIT: This mode enables transmit amp. reference regulator also enabled. RXLOCKP: This mode used "prior timeslot, i.e., slot before actual active receive timeslot. this mode, after lock been achieved RXLOCK mode, receive mixer, strip then independently powered from demodulator loop. This result power savings, since demodulator powered down during lock acquisition time.
VCOGND
LOCK
/3,/5 REFIN REFSEL
CTL3 CTL2 CTL1 TXOUT TXOUTB
FMMOD2 FMMOD1
MODOUT
Figure Power Management Scheme
REV.
AD6402
A/RAD LIMITER 34pF 1.4k CFILT REFIN A/RAD CPUMP COFF COFFSET CFILT
PLLOUT COFF COFFSET
/3,/5
CPUMP A/RAD
34pF
Figure Demodulator Block Diagram (Lock Mode)
Demodulator Operation
Figure Demodulator Block Diagram (Dmod Mode)
itself uses loops: rapid frequency acquisition second demodulation. first, frequencyacquisition loop, locks noninteger multiple system clock, either (using fixed programmable divider). This allows only choice system clocks also prevents blocking receiver keeping integer multiples system clock passband. Once locked, this loop voltage stored external capacitor this sets free-running frequency during demodulation. first loop opened and, using second loop phase detector, compares free-running frequency frequency incoming then fast frequency locked, slow phase locked incoming Preconditioning local reference clock facilitates fast frequency lock received generates baseband voltage proportional frequency deviation received signal. demodulator uses third-order track incoming modulation signal. simplified diagram demodulator shown Figures loop bandwidth damping factor adjusted changing values indicated. internal pole present demodulator loop approximately MHz. loop kHz, values respectively optimum. loop bandwidth will approximately scale inversely square root value preserve satisfactory damping factor, should adjusted linearly with loop bandwidth. loop bandwidths however value offset must also increased enable loop lock reference frequency during prior receive time slots.
APPLICATIONS
timeslot, thereby enabling very accurate offset compensation system frequency errors. on-chip filter been designed provide some rejection adjacent channel signals channel bandwidths MHz-2 range. This filter benefit reducing contribution broadband noise through strip, hence improving overall sensitivity receiver given demodulator output signal noise ratio. also possible AD6402 applications where nonconstant envelope modulation schemes used, such QPSK. these applications amplitude information will lost through limiting action strip, certain applications, sufficient eye-opening will observed demodulated signal allow hard decision bit-slicers case. actual performance subsystem presence QPSK signal will depend factors such rate, modulation index employed. Figure shows RSSI response DECT signal port. seen from plot that AD6402 detect signals below continues detect linearly above dBm.
AD6402 optimized applications where data rate order megabit second required modulation scheme employed constant envelope, i.e., FSK. Because demodulator uses track hold technique that locks externally supplied reference clock, device optimized TDMA systems. used continuous demodulation applications, offset hold voltage demodulator differential amplifier will ultimately leak away, resulting average value demodulator output eventually limiting against supply rail. TDMA system, voltage capacitor refreshed just before active
RSSI
INPUT POWER
Figure RSSI Response
Figure shows implementation DECT subsystem. DECT 1.152 megabit/second radio, employing Gaussian modulation uses channel spacing 1.728 MHz. TDMA/TDD system. frequency used this application 110.592 MHz. AD6402's flexible power management scheme enables part operate
REV.
AD6402
100nF IFVCC1 IFVCC2 RSSI DOUT 47pF 4.7k 4.7k 3.3nF RSSI RXBB 33pF
IFIN 150nH
AD6402
B4535 100nH 150nH 12pF IFGND VBAT VREG 100nF SLREF 1.2k 47pF 39nH IFC2 IFC1 4.7nF 1204-37 1204-36 IFC0 TXIF+ TXIF- 150pF VCOGND CTL3 CTL2 CTL1 /3,/5 IFIN
DFILP PLLOUT PLLVCC PLLGND REXT CFILT COFF
68pF
100pF
VREF
131nF RCLK 100pF 180pF TXBB
REFIN 100nF REFSEL FMMOD2
VTUNE
TXOUT TXOUTB MODOUT
FMMOD1
Figure Application Circuit DECT GFSK Transceiver
supply current levels when allocated active transmit receive timeslot TDMA system. respective transmit receive blocks turned only needed thereby reducing power consumption extending battery life handheld terminals. component selection Figure explained follows: input driven from output filter impedance matching circuit shown. This matching minimizes insertion loss filter follows filter manufacturers recommendations. tank circuit shown uses varactor diodes. diode (D3) biased output loop filter ensures that frequency correctly centered. second diode provided enable modulation signal, which generated output on-chip (MODOUT), coupled into tank thereby implement modulation frequency. case DECT, control loop opened while being modulated transmit stream. loop opened tri-stating output charge pump. exact component values used around modulation amplifier will determined amount attenuation required suppression baseband transmit spurii images. These artifacts usually present baseband signal generated ROMDAC. most instances second third order Bessel Butterworth filter will required. capacitor ground required connected COFF. This capacitor stores demodulator charge-pump voltage required lock demodulator reference frequency. dynamic response demodulator loop controlled selection values which connected series CFILT. These components determine REV.
transfer characteristic loop filter hence lock time, settling time bandwidth loop. REXT should recommended value shown. Finally, demodulator followed voltage follower, which configured data filter. This data filter used bandlimit noise generated demodulator. also attenuates undesired adjacent channel interferers. component values chosen will trade-off between amount band limiting required attenuation in-band desired signal.
DECT Application Circuit Notes (Figure
Signal Description VRF: Regulated Supply Voltage; Nominal Value 2.85 VCC: Unregulated battery voltage; V-4.5 VTUNE: Synthesizer Control Voltage; Range dependent loop filter synth charge pump compliance. TXBB: Baseband transmit modulation voltage; typically SLREF RCLK: Reference clock demodulator; 13.824 (2nd frequency (N/M) Frclk where Maximum c.26 MHz) Typical input sensitivity referred input filter above application will dBm. TxBB filter user configurable. above application, filter implemented remove images generated baseband signal generators. Other implementations possible including passive pulse shaping circuits which eliminate need such filtering.
AD6402
EVALUATION BOARD
evaluation board available AD6402. This board facilitates test measurement subsystem. Parameters such sensitivity, ACI, CCI, demodulator gain, demodulator offset, etc., quickly evaluated using this board. Contact
PLLOUT DOUT SLREF PLLVCC IFVCC2 RSSI IFVCC1 REFSEL MODIN MODOUT CTL1 CTL2 CTL3 VBATX VBAT
your local sales office representative further details pricing availability evaluation boards. Header connections details shown Figure available signals shown Figure schematic evaluation board shown Figure
33pF MODOUT 33nH REXT COFF CFILT 1000pF CTL1 CTL2 CTL3 VBAT VREG VCOGND FMMOD1 FMMOD2 MODOUT TXOUTB 100nF TP10 56pF MODIN TP11
TXOUTB
VREG
CONNECT PLLOUT SLREF REFIN DFILP
AD6402
PLLGND PLLVCC IFVCC2 DOUT RSSI
REFSEL
IFVCC1
SYNTH
REFIN
IFIN
Figure Evaluation Board Header
IFGND
56pF
100pF 91pF
0.01
0.01
0.01
TXOUT
TXOUTB
TXOUT
2.2nF
100pF REFSEL CONNECTOR
AD6402
TXOUT
1.3k PLLOUT 2.2k 47pF
RSSI IFIN
INPUT
DOUT REFIN IFIN
NOTE: SYNTH TXOUTB, TXOUT, IFIN REFIN CONNECTED CONNECTORS
Figure Evaluation Board Schematic
Figure Evaluation Board Connectors
OUTLINE DIMENSIONS
Dimensions shown inches (mm).
28-Lead Small Shrink Outline Package (RS-28)
0.407 (10.34) 0.397 (10.08)
0.078 (1.98) 0.068 (1.73)
0.07 (1.79) 0.066 (1.67)
0.008 (0.203) 0.0256 (0.65) 0.002 (0.050)
0.015 (0.38) 0.010 (0.25)
SEATING 0.009 (0.229) PLANE 0.005 (0.127)
0.03 (0.762) 0.022 (0.558)
REV.
PRINTED U.S.A.
0.311 (7.9) 0.301 (7.64)
0.212 (5.38) 0.205 (5.21)
C3155-12-7/97

IFIN Transceiver Subsystem AD6402 FUNCTIONAL BLOCK DIAGRAM

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