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Specifications Features High quality, cost CMOS image sensors Industry
Top Searches for this datasheetAgilent ADCS-1121, ADCS-2121 CMOS Monochrome Image Sensors Specifications Features High quality, cost CMOS image sensors Industry-standard 32-pin CLCC package Description ADCS-1121 ADCS-2121 CMOS Monochrome Image Sensors capture high quality, noise images while consuming very power. These parts integrate highly sensitive active pixel photodiode array with timing control onboard conversion. Available either (640x480) (352x288) resolution image arrays, devices ideally suited wide variety applications. ADCS-2121 ADCS-1121, when coupled with compatible image processors from either Agilent selected Agilent partners, provide complete imaging system enable rapid end-product development. Designed low-cost consumer electronic applications, ADCS-2121 ADCS-1121 sensors deliver unparalleled performance mainstream imaging applications. ADCS-2121 (VGA) ADCS-1121 (CIF) CMOS active pixel image sensors with integrated conversion full timing control. They provide random access sensor pixels, which allows windowing panning capabilities. sensor designed video applications still image capabilities. ADCS family achieves excellent image quality with very dark current, high sensitivity, superior anti-blooming characteristics. devices operate from single bias voltage, easy configure control, feature power consumption. Programmable Features Programmable window size ranging from full array down pixel window Programmable panning capability which allows specified window (minimum pixels) located anywhere sensor array Internal register programmable either UART Synchronous serial interface Integrated timing controller with rolling electronic shutter, row/ column addressing, operating mode selection with programmable exposure control, frame rate, data rate Programmable horizontal, vertical, shutter synchronization signals Programmable horizontal vertical blanking intervals resolution (640H 480V)- ADCS-2121 resolution (352H 288V)- ADCS-1121 High frame rates digital video VGA: frames/second CIF: frames/second High sensitivity, noise design ideal capturing high-quality images variety lighting conditions Integrated analog-to-digital converters: (ADCS-2121): bit, programmable (ADCS-1121): bit, fixed Parallel serial output Automated, dark response compensation Automatic subtraction column fixed pattern noise Still image capability Synchronous serial UART interface Integrated voltage references Applications code scanners Biometrics Machine vision Optical character recognition Surveillance Brief Introduction Agilent ADCS-2121 Agilent ADCS-1121 image sensors normal CMOS digital devices from outside. Internal circuits combination sensitive analog timing circuits. Therefore, designer must attention board layout power supply design. Writing registers compatible two-wire interface provides control sensor. Sensor data normally output parallel interface (serial data output also available). Once registers programmed sensor selfclocking timing internally generated. Analog digital conversion also chip digital data output. data ready pulse follows each valid pixel output. signal follows each frame signal follows each frame. Layout Analog analog ground need routed separately from digital digital ground. Noisy circuits should placed opposite side board. Heat producing circuits such microprocessors displays should placed next opposite from sensor reduce noise image. Power Supply sensor operates VDC. There power supplies sensor. Analog Digital Vdd. supplies grounds must kept separate. separate regulators provide best isolation. noise analog supply will result noise image. Analog digital ground should tied together single point lowest impedance noise. Master Clock part requires duty cycle master clock. Maximum clock rates ADCS-2121 ADCS-1121. Reset hard reset required before sensor will function properly. Once master clock running, assert nRST_nSTBY clock cycles. Register Communication Communication (read/write) sensor registers wire serial interface-either synchronous compatible half duplex UART (9600 baud default). nTristate (pin ADCS-1121 only) must pulled high normal operation. ADCS-2121 does have nTristate. Parallel Data Output parallel data output from sensor. data ready line (DRDY) asserted when data valid. sensor acts master outputs data. There flow control data received handshake. Once (CONTROL register) set, image processor must ready accept data sensor rate when data presented. Serial Data Output this mode, output data lines (the lower bits parallel data port) wire serial interface. Handshaking data, nROW line asserted. frame data, nFRAME_nSYNC line asserted. Registers next page table sample register settings (see Figure These values good starting point. Table Register Declaration Agilent ADCS-1121 ADCS-2121 Image Sensors. Register Name Identifications Register Status Register Interrupt Mask Register Control Register Drive Control Register Interface Control Register Interface Timing Register Baud Fraction Register Baud Rate Register Control Register First Window Register First Window Column Register Last Window Register Last Window Column Register Timing Control Register Exposure Register Exposure High Register Sub-Row Exposure Register Error Control Register Interface Timing Register Interface Control Register Horizontal Blank Register Vertical Blank Register Configuration Register Control Register Reserved Reserved Reserved Reserved Mnemonic IDENT STATUS IMASK PCTRL PDRV ICTRL ITMG BFRAC BRATE ADCCTRL FWROW FWCOL LWROW LWCOL TCTRL ROWEXPL ROWEXPH SROWEXP ERROR ITMG2 ICTRL2 HBLANK VBLANK CONFIG CONTROL Address (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 Sample Value (hex) 0x7F 0x00 0x03 0x00 0x20 0x00 0x00 0x00 0x08 0x00 0x07 0x79 0xA8 0x04 0x00 0x02 0x00 0x00 0x4B 0x00 0x00 0x00 0x0C 0x04 Setting Exposure Gain exposure image function exposure gain registers. Exposure sets length time each pixel integrates light (shutter speed). Gain settings allow pixel values amplified. Gain values from allowed, higher gain settings amplify noise (much like higher film speeds grainier). best lower gain settings better images. Gains from generally recommended. There three exposure registers (see Table exposure high register (upper bits) exposure register (lower bits) single register. This register sets integration time (shutter speed) sensor. sub-row exposure register used very small changes exposure allow fine-tuning exact shutter speeds. Table Exposure Register Settings. Register Name Exposure Register Exposure High Register Sub-Row Exposure Register Mnemonic ROWEXPL ROWEXPH SROWEXP Address (hex) 0x13 0x14 0x15 Proper exposure will result black values near 0x00 white values near 0xFF (assuming bits). grey patches MacBeth chart should have different average intensity values image. brightest patches both appear white then exposure long. darkest patches both appear black then exposure short. Remember that image does have gamma correction applied yet. final grey scale image needs evaluated after gamma correction. Image Processing data from sensor requires image processing before digital image ready viewing. Some standard steps image processing follows: Defective pixel correction Lens flare subtraction Auto-exposure Gamma correction Data compression Image processing part sensor must supplied separately. Image processors that compatible with these sensors available from Agilent Technologies selected Agilent partners. Typical Application Clock IMODE0 IMODE1 nTRISTATE DRDY DATA READY Reset Frame TxD/RxD Clock Parallel Interface ADCS-1121 nRST_nSTBY nROW nFRAME_nSYNC nIRQ Analog Analog Digital Digital 3.3V Regulator 3.3V Regulator Serial Interface Host System Star Ground Typical Electrical Specifications Part Number Pixel size Maximum Clock Rate Effective Sensor Dynamic Range Effective Noise Floor Dark Signal [1,3] ADCS-2121 (VGA) (VGA) (VGA) e240 e-/sec 22°C) 1.22 68,000 µV/e1- resolution) µsec minimum, µsec increments -5%/+10% operating, standby operating, standby 1/3" +65°C -40° +125°C ADCS-1121 (CIF) (CIF) (CIF) e240 e-/sec 22°C) 1.22 68,000 µV/e1- resolution) µsec minimum, µsec increments -5%/+10% operating, standby operating, standby 1/4" +65°C -40° +125°C Saturation Voltage Full Well Capacity Conversion Gain Programmable Gain Range Fill Factor Exposure Control Supply Voltage Absolute Max. Power Supply Voltage Absolute Max. Input Voltage (any pin) Power Consumption (typical) Power Consumption (max) Optical Format Operating Temperature Storage Temperature Notes: Specified over complete pixel area Measured unity gain Excludes dark current shot noise ADCS Sensor Level Block Diagram IMAGE ARRAY 12C/UART Compatible/ UART PROGRAMMABLE AMPLIFIER CLOCK TIMING CONTROLLER ANALOG DIGITAL CONVERTER 8/10 DIGITAL OUTPUT SYNC/IRQ ADCS-2121 Package Diagram nRST_nSTBY SDATA_TxD SCLK_RxD AGND3 ADCS-1121 Package Diagram nRST_nSTBY SDATA_TxD SCLK_RxD AGND3 DATA6 DATA8 DATA9 DATA7 nROW PVDD DATA7 AGND2 AVDD2 VDD3 GND3 DRDY DATA6 DATA5 IMODE0 IMODE1 nIRQ_nCC nFRAME_nSYNC AVDD1 AGND1 GND1 DATA5 AGND2 AVDD2 VDD3 GND3 DRDY DATA4 DATA3 nROW PVDD IMODE0 IMODE1 nIRQ_nCC nFRAME_nSYNC AVDD1 AGND1 GND1 VDD1 DATA4 VDD2 GND2 DATA3 VDD1 DATA2 DATA1 DATA0 DATA2 VDD2 GND2 DATA1 DATA0 nTRISTATE ADCS-2121 Description Pins Signal Name IMODE1 IMODE0 nRST_nSTBY Data Data Data Data DRDY SDATA_TxD SCLK_RxD nFRAME_nSYNC nROW nIRQ_nCC PVDD AVDD AGND Type Input Input Input Input Output Output Input/output open drain Input Output Output Output PVDD AVDD AGND Description Half duplex UART slave interface mode Synchronous serial slave interface mode Always System Clock Active system reset input stand-by mode input Parallel digitized pixel data Data valid parallel digitized pixel data Serial output data Transfer clock serial data input Signals frame Signals Programmable interrupt request Digital power supply Digital ground Array power supply Analog power supply Analog, array, substrate ground ADCS-1121 Description Pins (Location) Signal Name IMODE1 IMODE0 nRST_nSTBY Data Data Data Data DRDY SDATA_TxD SCLK_RxD nFRAME_nSYNC nROW nIRQ_nCC PVDD AVDD AGND nTRISTATE Type Input Input Input Input Output Output Input/output open drain Input Output Output Output PVDD AVDD AGND Input Description Half duplex UART slave interface mode Synchronous serial slave interface mode Always System Clock Active system reset input stand-by mode input Parallel digitized pixel data Data valid parallel digitized pixel data Serial output data Transfer clock serial data input Signals frame Signals Programmable interrupt request Digital power supply Digital ground Array power supply Analog power supply Analog, array, substrate ground Disables sensor tristate mode connect Packaging General Package Specs 32-pin CLCC side) Package dimensions, optical center shown diagram below 1.15 0.10 0.50 Note: This packaging complies with JEDEC Moisture Sensitivity Level 5.33 0.23 0.30 (PAD LENGTH) Optical center 4.38 0.23 center Glass 1.26 0.15 0.55 32.1 7.36 CROSS SECTION 8.12 +0.10 -0.15 10.66 0.13 VIEW 0.50 PLATED LEAD AREA 1.65 0.13 10.66 0.13 7.11 0.07 1.02 0.05 TYP-NON ACCUM INDEX (1.02) 1.27 CASTELATION 2.23 0.20 0.51 (2.02) 0.15 SIDE VIEW BOTTOM VIEW www.agilent.com/semiconductors product information complete list distributors, please site. technical assistance call: Americas/Canada: (800) 235-0312 (408) 654-8675 Europe: 6441 92460 China: 10800 0017 Hong Kong: (+65) 6271 2451 India, Australia, Zealand: (+65) 6271 2394 Japan: (+81 0120-61-1280(Domestic Only) Korea: (+65) 6271 2194 Malaysia, Singapore: (+65) 6271 2054 Taiwan: (+65) 6271 2654 Data subject change. Copyright 2003 Agilent Technologies, Inc. Obsoletes 55988-7291EN January 2003 5988-8615EN 10.05 Pics 7.36 Other recent searchesXLUR81D - XLUR81D XLUR81D Datasheet SBF0408LPL - SBF0408LPL SBF0408LPL Datasheet P4404EDG - P4404EDG P4404EDG Datasheet FD1495 - FD1495 FD1495 Datasheet EE-144 - EE-144 EE-144 Datasheet BUW22A - BUW22A BUW22A Datasheet 2SK4208 - 2SK4208 2SK4208 Datasheet 2SC5172 - 2SC5172 2SC5172 Datasheet
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