MH16D36ABGA-10,-75,-75A 603979776-BIT (16777216 WORD 36-BIT) Doub
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MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM CONFIGURATION VIEW DESCRIPTION
MH16D36ABGA word 36-bit Double Data Rate nchronous DRAM module.This consists three industry standard Double Data Rate nchronous DRAMs STSOP. mounted both sides Similar package.
FEATURES
Utilizes industry standard Synchronous DRAMs STSOP package (including Dummy pins) Vdd=Vddq= 2.5V 0.2V Double data rate architecture; data transfers clock cycle Bidirectional, data strobe (DQS) transmitted received with data Differential clock inputs (CLK /CLK) aligns transitions with transitions edges Commands entered each positive edge /CAS latency (programmable) Burst length 2/4/8 (programmable) Burst type sequential interleave (programmable) Auto precharge bank precharge controlled Auto refresh Self refresh 8192 refresh cycle 64ms SSTL_2 Interface
OPERATING FREQUENCIES
Clock Rate Type name CL=2 CL=2.5
MH16D36ABGA-75A
133MHz
133MHz
MH16D36ABGA-75
100MHz
133MHz
MH16D36ABGA-10
100MHz
100MHz CAS(Read) Latency
APPLICATION
Main memory unit computers, Microcomputer memory, PDA, Refresh memory
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
Configuration
DQ28 DQ29 DQ30 DQ31 VREF
DQS3 DQ24 DQ25 DQ26 DQ27
DQS1 DQ12 DQ13 DQ14 DQ15
/CLK DQ10 DQ11
/CAS DQS4 DQ32
/RAS DQS0 DQ35
DQS2 DQ19 DQ18 DQ17 DQ16 DQ34 DQ33
DQ23 DQ22 DQ21 DQ20
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
Block Diagram
A<12.0>,BA<1.0> /RAS /CAS /CLK DQS0 DQS1 DQS2 DQS3 DQS4
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQS
UDQS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
LDQS
DQ32 DQ33 DQ34 DQ35
LDQS
UDQS
L/UDM
0.1uF
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
FUNCTION
CLK, /CLK Input
Clock: /CLK differential clock inputs. address control input signals sampled crossing positive edge negative edge /CLK. Output (read) data referenced crossing /CLK (both directions crossing). Clock Enable:CKE controls internal clock. When low,internal clock following cycle ceased. also used select auto self refresh. After self refresh mode started, becomes asynchronous input. Self refresh maintained long low. Chip Select: When high,any command means Operation. Combination /RAS,/CAS,/WE defines basic commands. A0-12 specify Row/Column Address conjunction with BA0,1.The Address specified A0-12. Column Address specified A0-8. also used indicate precharge option. When high read write command, auto precharge performed. When high precharge command, banks precharged.
Input
/RAS,/CAS,/WE
Input Input
A0-12
Input
BA0,1
Input
Bank Address: BA0,1 specifies bank which command applied.BA0,1 must with ACT,PRE,READ,WRITE commands
DQ0-35
Input/Output
Data Input/Output: Data
DQS0-4
Input/Output
Data Strobe: Output with read data, input with write data. Edge aligned withread data, centered write data. Used capture write data.
Vdd,Vss Vref
Power Supply Power Supply memory mounted module. Input
SSTL_2 reference voltage.
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
BASIC FUNCTIONS
MH16D36ABGA provides basic read write, bank(row) precharge,and auto self refresh. Each command defined control signals /RAS,/CAS rising edge. addition signals,/CS,CKE used chip select, refresh option precharge option, respectively. know detailed definition commands, please command truth table.
/CLK
/RAS /CAS
Chip Select L=select, H=deselect Command Command Command resh Option @ref resh command Precharge Option @precharge read/write command basic commands
Activate(ACT) [/RAS /CAS command activates idle bank indicated Read(READ) [/RAS =H,/CAS READ command starts burst read from active bank indicated First output data appears after /CAS latency. When this command, bank deactivated after burst read (auto-precharge,READA). Write(WRITE) [/RAS /CAS WRITE command starts burst write active bank indicated Total data length written burst length. When this command, bank deactivated after burst write (auto-precharge,WRITEA). Precharge(PRE) [/RAS /CAS command deactivates active bank indicated This command also term inates burst read write operation. When this command, both banks deactivated (precharge all, PREA). Auto-Refresh(REFA) [/RAS =/CAS =CKE REFA command starts auto-refresh cycle. Refresh address including bank address generated internally. After this command, banks precharged automatically.
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
POWER SEQUENCE
Before starting normal operation, following power sequence necessary prevent SDRAM from damaged maltifunctioning. Apply before same time VDDQ Apply VDDQ before same time Vref Maintain stable condition 200us after stable power CLK, apply DSEL. Issue precharge commands banks device. Issue EMRS Issue Mode Register reset Issue more Auto Refresh commands Maintain stable condition cycle After these sequence, SDRAM idle state ready normal operation.
MODE REGISTER
Burst Length, Burst Type /CAS Latency programmed setting mode register(MRS). mode register stores these date until next command, which issue when both banks idle state. After tMRD from command, SDRAM ready command.
/RAS /CAS LTMODE A11-0 SEQUENTIAL INTERLEAVED
LATENCY MODE
/CAS LATENCY
BURST LENGTH
BURST TYPE
Reset
R:Reserved Future
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
EXTENDED MODE REGISTER
disable enable mode programmed setting extended mode register (EMRS). extended mode register stores these data until next EMRS command, which issued when banks idle state. After tMRD from EMRS command, DIMM ready command.
/CLK /RAS /CAS
A11-A0
Disable
enable disable
Drive Strength
Normal Weak
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM /CLK Command Address /CAS Latency
Read
Write
Burst Length
Burst Length
Initial Address
Sequential
Column Addressing Interleaved
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
ABSOLUTE AXIMUM RATINGS
Symbol Topr Tstg Parameter Supply Voltage Input Voltage Output Voltage Output Current Power Dissipation Operating Temperature Storage Temperature Ta=25°C Condition with respect with respect with respect Ratings -0.5 -0.5 Vdd+0.5 -0.5 Vdd+0.5 Unit
RECOM ENDED OPERATING CONDITION
(Ta=0 70°C, unless otherwise noted)
Limits Symbol Vref VIH(DC) VIL(DC) VIN(DC) Parameter Supply Voltage Input Reference Voltage High-Level Input Voltage Low-Level Input Voltage Input Voltage Level, /CK0 Min. 0.49*Vdd Vref 0.15 -0.3 -0.3 0.36 Vref 0.04 Typ. 0.5*Vdd Max. 0.51*Vdd Vdd+0.3 Vref 0.15 Vref 0.04 Unit Notes
VID(DC) Input Differential Voltage, /CK0 Termination Voltage
CAPACITANCE
(Ta=0 70°C, 0.2V, unless otherwise noted) Parameter Symbol Test Condition CI(A) Input Capacitance, address
1.25V
Limits(max.)
Unit Notes
CI(C) CI(K) CI/O
Input Capacitance, control Input Capacitance, Capacitance, I/O,DQS
=100MHz 25mVrm
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
AVERAGE SUPPLY CURRENT from
(Ta=0 ~70°C, 0.2V, Output Open, unless otherwise noted)
Limits(max) Symbol Parameter/Test Conditions -75A OPERATING CURRENT: Bank(Discrete); Active-Precharge; MIN; MIN; inputs changing twice clock cycle; address control inputs changing once clock cycle OPERATING CURRENT: Bank(Discrete); Active-Read-Precharge; Burst MIN; 2.5; MIN; IOUT= mA;Address control inputs changing once clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: banks idle; power-down mode; (MAX); IDLE STANDBY CURRENT: (MIN); banks idle; (MIN); MIN; Address other control inputs changing once clock cycle ACTIVE POWER-DOWN STANDBY CURRENT: bank active; power-down mode; (MAX); ACTIVE STANDBY CURRENT: (MIN); (MIN); bank; Active-Precharge; MAX; MIN; inputs changing twice clock cycle; address other control inputs changing once clock cycle OPERATING CURRENT: Burst Reads; Continuous burst;One bank active(Discrete); Address control inputs changing once clock cycle; 2.5; MIN; IOUT OPERATING CURRENT: Burst Writes; Continuous burst; bank active(Discrete); Address control inputs changing once clock cycle; 2.5; MIN; inputs changing twice clock cycle AUTO REFRESH CURRENT: (MIN) SELF REFRESH CURRENT: 0.2V Unit Notes
IDD0
IDD1
IDD2P
IDD2F
IDD3P
IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
OPERATING CURRENT-Four bank Operation: Four interleaving with BL=4 -Refer Notes
OPERATING CONDITIONS CHARACTERISTICS
(Ta=0 70°C, 0.2V, Output Open, unless otherwise noted)
Symbol Parameter/Test Conditions Limits Min. Vref 0.31 Vref 0.31 0.5*Vdd-0.2 -16.8 16.8 0.5*Vdd+0.2 Max. Unit Notes 11.Jan.2002
VIH(AC) High-Level Input Voltage (AC) VIL(AC) Low-Level Input Voltage (AC) VID(AC) Input Differential Voltage, /CLK VIX(AC) Input Crossing Point Voltage, /CLK Off-state Output Current floating Vo=0~V Input Current VIN=0 VddQ Output High Current (VOUT=VTT+0.84V) Output Current (VOUT=VTT-0.84V)
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
TIMING REQUIREMENTS (DDR SDRAM Component)
(Ta=0 70°C VddQ 0.2V, VssQ unless otherwise noted)
Characteristics Parameter Output Valid data delay time CLK//CLK -75A Min. -0.75 -0.75 0.45 0.45 CL=2.5 tDIPW tDQSQ tDQSS tDQSH tDQSL tDSS tDSH tMRD time CL=2 Input Setup time (DQ) Input Hold time(DQ) input pulse width each input) Data-out-high impedance time CLK//CLK Data-out-low impedance time CLK//CLK Valid data delay Clock half period Output alid window Write command irst latching transition input High width input width alling edge setup time alling edge hold time Mode Register command time
tCLmin tCHmin tHP0.75
Min. -0.75 -0.75 0.45 0.45 1.75 Max. 0.75 0.75 0.55 0.55 Min. -0.8 -0.8
Max. 0.55 0.55 Unit
tCLmin tCHmin tHP-1.0
Max. 0.75 0.75 0.55 0.55
Notes
tDQSCK Output Valid data delay time CLK//CLK High width width
0.45 0.45
1.75 -0.75 -0.75
0.75 0.75
-0.75 -0.75
0.75 0.75
-0.8 -0.8
tCLmin tCHmin tHP0.75
0.75 0.35 0.35 0.25
1.25
0.75 0.35 0.35
1.25
0.75 0.35 0.35
1.25
tWPRES Write preamble setup time tWPST tWPRE tRPST tRPRE Write postamble Write preamble Input Setup time (address control) Input Hold time (address control) Read postamble Read preamble
0.25
0.25
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
TIMING REQUIREMENTS (DDR SDRAM Component, Continues)
(Ta=0 70°C, 0.2V, unless otherwise noted)
Characteristics Symbol tRAS tRFC tRCD tRRD tDAL tWTR tXSNR tXSRD tXPNR tXPRD tREFI Active time Cycle time(operation) Auto Ref. Active/Auto Ref. command period Column Delay Precharge time Delay time Write Recovery time Auto Precharge write recovery precharge time Internal Write Read Command Delay Exit Self Ref. non-Read command Exit Self Ref. -Read command Exit Power down command Exit Power down -Read command Average Periodic Refresh interval Parameter -75A
Min. Max. Min. Max. Min. Max. Unit Notes
120,000
120,000
120,000
Output Load Condition
component measurement)
50ohm VOUT Zo=50 30pF
Output Timing Measurement Reference Point
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
Notes oltages erenced Vss. Tests timing, IDD, electrical, characteristics, conducted nominal erence/supply oltage els, related specif ications operation guaranteed oltage range specif ied. timing tests swing 1.5V test ironment, input timing still erenced VREF crossing point CK//CK), parameter specif ications guaranteed specif input under normal conditions. minimum slew rate input signals 1V/ns range between VIL(AC) VIH(AC). input specif ications ined SSTL_2 Standard (i.e. receiv will ectiv switch result signal crossing input will remain that state long signal does ring back abov (below) input (HIGH) VREF expected equal 0.5*VddQ transmitting ice, track ariations same. Peak-to-peak noise VREF exceed +/-2% alue. applied directly ice. system supply signal termination resistors, expected equal VREF, must track ariations VREF. magnitude erence between input input /CLK. alue expected equal 0.5*VddQ transmitting must track ariations same. Enables on-chip resh address counters. specif ication tested properly initialized. This parameter sampled. VddQ +2.5V+/-0.2V, +2.5V+/-0.2V, =100MHz, 25'C, VOUT(DC)=VddQ/2, VOUT(PEAK PEAK) 25mV, inputs grouped with pins lecting that they matched laoding aciliate trace matching board el). CLK//CLK input erence timing erenced CLK//CLK) point which /CLK cross; input erence signals other than CLK//CLK, VREF. Inputs recognized alid until VREF stabilized. Exception: during period VREF stabilizes, CKE=<0.3VddQ recognized LOW. transitions occur same access time windows alid data transitions. These parameters erenced specif oltage specif when output longer driv (HZ), begins driv (LZ). maximum limit this parameter limit. will operate with greater alue this parameter, stem perf ormance (bus turnaround) will degrade accordingly specif requirement that alid (HIGH, LOW, some point alid transition) this edge. alid transition ined monotonic, meeting input slew rate specif ications ice. When writes were prev iously progress bus, will transitioning High-Z logic LOW. prev ious write progress, could HIGH, LOW, transitioning HIGH this time, depending tDQSS. maximum eight AUTO REFRESH mands posted SDRAM ice. tXPRD should tCLK condition unstable operation during power down mode. command/address /CLK slew rate >1.0V/ns. IDD7 Operating current:Four Bank Bank being interleav with tRC(min),Burst Mode,Address Control inputs changing. Iout=0mA Timing patterns: with Autoprecharge Read:A0 R0-repeat same timing with random address changing *100% data changing burst Legend:=A=Activ ate,R=Read,P=Precharge,N=NOP
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
OUTLINE
MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
MH16D36ABGA-10,-75,-75A
603979776-BIT (16777216 WORD 36-BIT) Double Data Rate Synchronous DRAM
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MIT-DS-0424-0.3
MITSUBISHI ELECTRIC
11.Jan.2002
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