GIGABIT ERROR CORRECTED DRAM 98C100032DRP DRAM EDAC Gigabit
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SPACE PRODUCTS
GIGABIT ERROR CORRECTED DRAM
98C100032DRP
DRAM EDAC Gigabit DRAM
DATA BITS
CD[31:0]
[31:0]
256Mb (32Mx8b) 256Mb (32Mx8b)
EDAC
[31:0]
[7:0]
256Mb (32Mx8b)
256Mb (32Mx8b)
ERROR
[7:0]
Control
CHECK BITS
Memory
D[7:0]
Module
256Mb (32Mx8b)
Memory Control
FEATURES:
Gigabit available DRAM (five DRAM stacks, four data, checkbit) bits wide, built EDAC RAD-PAK® radiation-hardened against natural space radiation Total dose hardness: krad (Si) typical; dependent upon orbit Single event effect SELTH: latchup MeV/mg/cm2 SEU: errors/device with memory scrubbing Single error detection/correction Double error detection Package: RAD-PAK® quad flat package Access time: Common Data Inputs Outputs Fast Page Mode capability 4096 Cycles 64ms Refresh
0407.99Rev0
DESCRIPTION:
Space Electronics' 98C100032DRP RAD-PAK®) high-performance Gigabit Multi-Chip Module (MCM) Dynamic Random Access Memory features typical kilorad (Si) total dose tolerance; dependent upon orbit. device single event latchup single event upset error rate IE-10 errors/device day. 98C100032DRP combines plastic TSOP DRAM stacks SEi's 48D32DRP 32-bit EDAC into hermetically sealed package. design architected using 32/7 hamming code EDAC, providing data bits check bits; DRAM stacks manufactured using DRAM devices, stacked four high create each 8-bit wide stack. Five stacks combined into 98C100032DRP create 32-bit wide, usable memory area. 98C100032DRP available with packaging screening Class
data sheets subject change without notice
(619) 452-4167 Fax: (619) 452-5499 www.spaceelectronics.com
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
Internal EDAC
GIGABIT ERROR CORRECTED DRAM INTERNAL EDAC DESCRIPTION:
EDAC broken down into main blocks check generator (CBG) read/correct data (CORR). unique flow-thru architecture achieves from data (MD) corrected data (CD). readable error counters allow single-bit error (ERR) doubel-bit error (DBERR) tracking. Error signals internally marked mask bits.
EDAC-CORE
MD(31:0)
D(31:0) ND(31:0) CB(7:0) DBERR Checkbit Generator
CD(31:0)
MC(7:0)
CB(7:0)
D(31:0)
CS/RD/WR
I/OA(3:0)
EDAC CONTROL LOGIC
I/O(7:0)
ERROR COUNTER
DBERR
Memory
INTERNAL DRAM DESCRIPTION:
data DRAM uses four Megabit stacks. 32-bit wide data that byte addressable. component designed specifically high-speed, low-power high-reliability application. device CAS-before refresh, RAS-only refresh Hidden refresh capabilities.
RAS0 RAS3 CAS0 CAS3
256Megabit (32M 8-bit) CAS3 RAS3 CAS2 RAS2 CAS1 RAS1 CAS0 RAS0
256Megabit (32M 8-bit)
256Megabit (32M 8-bit)
256Megabit (32M 8-bit)
256Megabit (32M 8-bit)
DQ31
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP DESCRIPTION
NUMBER
SIGNAL CD10 CD11 CD12 CD13 CD14 CD15 CD16
NUMBER
SIGNAL CD24 CD25 CD26 CD27 CD28 CD29 CD30 CD31 CBOE
NUMBER
SIGNAL IO_D5 IO_D6 IO_D7 CLKIN IO_WR IO_A0 IO_RD IO_CS IO_A2 IO_A1 CB_CAS0 CB_CAS1 CB_CAS2 CB_CAS3 CB_RAS0 CB_RAS1 CB_RAS2
NUMBER
SIGNAL RAS3
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
NUMBER SIGNAL CD17 CD18 CD19 CD20 CD21 CD22 CD23 NUMBER SIGNAL ADDR_R/C CB_WE IO_D0 IO_D1 IO_D2 IO_D3 IO_D4 NUMBER
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP DESCRIPTION
SIGNAL CB_RAS3 CAS0 CAS1 CAS2 CAS3 RAS0 RAS1 RAS2 NUMBER SIGNAL
Memory
TABLE 98C100032DRP ABSOLUTE MAXIMUM RATINGS
PARAMETER Voltage relative Voltage supply relative Operating Temperature Storage Temperature Output Current (Source/Sink) SYMBOL VIN, VOUT TSTG IOUT -0.5 -0.5 UNIT
TABLE 98C100032DRP RECOMMENDED OPERATING CONDITIONS
(VOLTAGE REFERENCED VSS, UNLESS OTHERWISE SPECIFEID) PARAMETER Supply Voltage Ground Input High Voltage Input Voltage SYMBOL -1.0 -MAX +1.0 UNIT
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP CAPACITANCE
5.0V, MHZ)
PARAMETER Address Input Input Input Write Enable Output Enable Data Input/Output
SYMBOL CADR CCAS CRAS CI/O
UNIT
TABLE 98C100032DRP CHARACTERISTICS
(RECOMMENDED OPERATING CONDITIONS UNLESS OTHERWISE SPECIFIED) PARAMETER Input Leakage Current Output Leakge Current Output High Voltage Level Output Voltage Level Operating Current 98C100032DRP-9 98C100032DRP-12 Standby Current RAS-only Refresh Current 98C100032DRP-9 98C100032DRP-12 FAST-PAGE-MODE Current 98C100032DRP-9 98C100032DRP-12 Standby Current CAS-Before-RAS Refresh Current 98C100032DRP-9 98C100032DRP-12 SYMBOL IOUT ICC1 TEST CONDITIONS CAS, Data disabled, VOUT -5mA 4.2mA cycling -ICC2 ICC3 VIH, cycling -ICC4 address cycling ICC5 ICC6 0.2V cycling -750 -400 -750 -MAX -0.4 UNITS
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP CHARACTERISTICS (-40 5.0V 10%, VIH/VIL 2.0/0.8V, VOH/VOL 2.0/0.8V UNLESS OTHERWISE SPECIFIED)
PARAMETER Random read write cycle time 98C100032DRP-9 98C100032DRP-12 Read-modify-write cycle time 98C100032DRP-9 98C100032DRP-12 Access time 1,2,3 98C100032DRP-9 98C100032DRP-12 Access time 1,2,4 98C100032DRP-9 98C100032DRP-12 Access time from column address 98C100032DRP-9 98C100032DRP-12 output LOW-Z 98C100032DRP-9 98C100032DRP-12 Output buffer turn-off delay 98C100032DRP-9 98C100032DRP-12 Transition time (rise fall) 98C100032DRP-9 98C100032DRP-12 precharge time 98C100032DRP-9 98C100032DRP-12 pulse width 98C100032DRP-9 98C100032DRP-12 hold time 98C100032DRP-9 98C100032DRP-12 hold time 98C100032DRP-9 98C100032DRP-12 pulse width 98C100032DRP-9 98C100032DRP-12 delay time 98C100032DRP-9 98C100032DRP-12
0407.99Rev0
SYMBOL
tRWC tRAC -tCAC -tAA -tCLZ tOFF tRAS tRSH tCSH tCAS tRCD -10K
Memory
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
PARAMETER column address delay time 98C100032DRP-9 98C100032DRP-12 precharge time 98C100032DRP-9 98C100032DRP-12 address set-up time 98C100032DRP-9 98C100032DRP-12 address hold time 98C100032DRP-9 98C100032DRP-12 Column address set-up time 98C100032DRP-9 98C100032DRP-12 Column address hold time 98C100032DRP-9 98C100032DRP-12 Column address lead time 98C100032DRP-9 98C100032DRP-12 Read command set-up time 98C100032DRP-9 98C100032DRP-12 Read command hold time referenced 98C100032DRP-9 98C100032DRP-12 Read command hold time referenced 98C100032DRP-9 98C100032DRP-12 Write command hold time 98C100032DRP-9 98C100032DRP-12 Write command pulse width 98C100032DRP-9 98C100032DRP-12 Write command lead time 98C100032DRP-9 98C100032DRP-12 Write command lead time 98C100032DRP-9 98C100032DRP-12
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP CHARACTERISTICS (-40 5.0V 10%, VIH/VIL 2.0/0.8V, VOH/VOL 2.0/0.8V UNLESS OTHERWISE SPECIFIED)
SYMBOL tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tRWL tCWL
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
PARAMETER Data set-up time 98C100032DRP-9 98C100032DRP-12 Data hold time 98C100032DRP-9 98C100032DRP-12 Refresh Period 98C100032DRP-9 98C100032DRP-12 Write command set-up time 98C100032DRP-9 98C100032DRP-12 delay time 98C100032DRP-9 98C100032DRP-12 delay time 98C100032DRP-9 98C100032DRP-12 Column address delay time 98C100032DRP-9 98C100032DRP-12 precharge delay time 98C100032DRP-9 98C100032DRP-12 set-up time (CAS-before-RAS refresh) 98C100032DRP-9 98C100032DRP-12 hold time (CAS-before-RAS refresh) 98C100032DRP-9 98C100032DRP-12 precharge time 98C100032DRP-9 98C100032DRP-12 Fast Page mode cycle time 98C100032DRP-9 98C100032DRP-12 Fast Page mode read-modify-write cycle time 98C100032DRP-9 98C100032DRP-12 precharge time (Fast Page cycle) 98C100032DRP-9 98C100032DRP-12
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP CHARACTERISTICS (-40 5.0V 10%, VIH/VIL 2.0/0.8V, VOH/VOL 2.0/0.8V UNLESS OTHERWISE SPECIFIED)
SYMBOL tREF -tWCS tCWD tRWD tAWD tCPWD tCSR tCHR tRPC tPRWC
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
PARAMETER pulse width (Fast Page cycle) 98C100032DRP-9 98C100032DRP-12 hold time from precharge 98C100032DRP-9 98C100032DRP-12 access time 98C100032DRP-9 98C100032DRP-12 data delay 98C100032DRP-9 98C100032DRP-12 Output buffer turn delay time from 98C100032DRP-9 98C100032DRP-12 command hold time 98C100032DRP-9 98C100032DRP-12 precharge time (C-B-R refresh) 98C100032DRP-9 98C100032DRP-12 hold time (C-B-R refresh) 98C100032DRP-9 98C100032DRP-12 Measured with load equivalent load
GIGABIT ERROR CORRECTED DRAM
TABLE 98C100032DRP CHARACTERISTICS (-40 5.0V 10%, VIH/VIL 2.0/0.8V, VOH/VOL 2.0/0.8V UNLESS OTHERWISE SPECIFIED)
SYMBOL tRASP tRHCP tOEA -tOED tOEZ tOEH tWRP tWRH 200K 200K
Memory
Operation within tRCD (max) limit ensures that tRAC (max) met. tRCD (max) specified reference point only. tRCD greater than specified tRCD (max) limit, then access time controlled exclusively tCAC. Operation within tRAD (max) met. tRAD (max) specified reference point only. tRAD greater than specified tRAD (max) limit, then access time controlled tAA. Assumes that tRCD tRCD (max). tOFF (max) tOEZ (max) define time which output achieves open circuit condition referenced VOL. (min) (max) reference levels measuring timing input signals. Transition times measured between (min) (max) assumed inputs. Guaranteed design. Either tRCH tRRH must satisfied read cycle. These parameters referenced leading edge early write cycles leading edge read-modify-write cycles. tWCS, tRWD, tCWD tAWD non-restrictive operating partners. They included data sheet electric characteristics only. tWCS tWCS (min), cycles early write cycle data output will remain high impedance duration cycle. tCWD tCWD (min) tAWD tAWD (min), then cycle read-modify-write cycle data output will contain data read from selection address. neither above conditions satisfied, condition data indeterminable. less CAS-before-RAS current loss tCHR tRAS CAS-before-RAS refresh mode.
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
FIGURE READ CYCLE
GIGABIT ERROR CORRECTED DRAM
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
NOTE: DOUT OPEN
GIGABIT ERROR CORRECTED DRAM
FIGURE WRITE CYCLE (EARLY WRITE)
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
NOTE: DOUT OPEN
GIGABIT ERROR CORRECTED DRAM
FIGURE WRITE CYCLE CONTROLLED WRITE)
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
FIGURE READ-MODIFY-WRITE CYCLE
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
FIGURE FAST PAGE READ CYCLE
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
NOTE: DOUT OPEN
GIGABIT ERROR CORRECTED DRAM
FIGURE FAST PAGE WRITE CYCLE (EARLY WRITE)
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
FIGURE FAST PAGE READ-MODIFY-WRITE CYCLE
Memory
FIGURE RAS-ONLY REFRESH CYCLE
NOTE: DON'T CARE; DOUT OPEN
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
NOTE: DON'T CARE
GIGABIT ERROR CORRECTED DRAM
FIGURE CAS-BEFORE-RAS REFRESH CYCLE
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
FIGURE HIDDEN REFRESH CYCLE (READ)
Memory
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
NOTE: DOUT OPEN
GIGABIT ERROR CORRECTED DRAM
FIGURE HIDDEN REFRESH CYCLE RITE)
Memory
FIGURE CAS-BEFORE-RAS SELF REFRESH CYCLE
NOTE: DON'T CARE
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
98C100032DRP
GIGABIT ERROR CORRECTED DRAM
Memory
RAD-PAK® QUAD FLAT PACKAGE
SYMBOL DIMENSION
0407.99Rev0
data sheets subject change without notice
©1999 Space Electronics Inc. rights reserved.
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