PowerPC 440EP Embedded Processor Advanced technology Imaging

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PowerPC 440EP Embedded Processor Advanced technology Imaging

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Highly integrated, cost-effective embedded processor solution
PowerPC 440EP Embedded Processor
Advanced technology Imaging
Industrial Control applications PowerPC 440EP embedded processor offers exceptional performance, design flexibility, robust features geared demanding Imaging, industrial control, networking other embedded applications. With speeds 533MHz, PowerPC Book Architecture, rich peripheral mix, PowerPC 440EP processors ideally
suited wide range high-performance applications. IBM's advanced 0.13-micron CMOS copper process technology innovative design provide power dissipation small footprint. Application code compatibility with other PowerPC processors enables manufacturers bring products market quickly cost satisfy changing needs. High integration with robust peripheral support further simplify board design help reduce manufacturing costs.
PowerPC 440EP Embedded Processor Block Diagram
Highlights
Delivers 333MHz 533MHz performance high-speed embedded designs 32-bit implementation Book Enhanced PowerPC® Architecture Superscalar PowerPC core, with large caches, with high-speed CoreConnectbus technology Single/double-precision floating point unit State-of-the-art peripherals including SDRAM, extensive connectivity Ethernet, USB, UARTs, IIC, Offers power dissipation small form factor high-density power-conscious applications Provides application code compatibility with other PowerPC processors
PowerPC Core: Designed high performance leadership performance PowerPC core derives from IBM's state-of-the-art CMOS technology applied embedded-application requirements. PowerPC superscalar core incorporates 7-stage pipeline executes instructions cycle, enhancing overall throughput. core's large data cache (32KB) instruction cache (32KB) 64-way associative, with versatile configurations enhance performance tuning. memory management unit (MMU) allows software developer configure cache regions three modes allow application optimization: locked regions used low-latency code interrupt service routines; transient regions handle use-once data without disturbing whole cache; normal regions typical round-robin replacement algorithms. also supports multiple page sizes, further contributing PowerPC core's memory efficiency maximizing translation lookaside buffer (TLB) hits. added system performance, PowerPC includes dynamic branch prediction, instructions, non-blocking caches that managed either write-through write-back mode.
PowerPC 440EP includes highperformance FPU. superscalar supports both single double precision operations, offers single cycle throughput most instructions. Wide data paths simultaneous reads writes boost throughput PowerPC 440EP CoreConnect 128-bit Processor Local (PLB4) separate read write data buses that offer 4.2GBps on-chip bandwidth (peak) between processor core memory. With 36-bit address path, offers 64GB memory addressability. CoreConnect 64-bit Processor Local (PLB3) 32-bit On-Chip Peripheral (OPB) collect less demanding devices improve utilization. Book Enhanced PowerPC Architecture Book Enhanced PowerPC Architecture features increased architectural flexibility optimized embedded applications. adaptable memory management features robust debug capabilities geared real-time other high-performance operating environments. Book PowerPC Architecture addresses requirements embedded applications while providing application code compatibility with current PowerPC applications. Robust features provide design flexibility PowerPC 440EP incorporates range versatile features that complement processor core
powerful solution diverse embedded applications: PPC440 core with 32KB/32KB I-cache/D-cache, with parity Floating point unit, IEEE 754, with single-precision double-precision support; single-cycle throughput most instructions SDRAM controller, DDR200/ DDR266 compliant, 32-bit data, 13-addr with support (ECC under evaluation) revision 2.2, 32-bit interface 66MHz, with internal arbiter devices External Peripheral Controller (EBC), 50-66MHz, 16-bit data, 30-bit address, chip selects, supports ROM, EPROM, SRAM, flash slave peripherals banks, with master support Nand Flash support External Master interface host with on-chip device controller with UTMI interface USB1.1 device with on-chip host controller muxed with device Ethernet 10/100 Mbps, full duplex (1xMII 2xRMII) with packet reject interface support Memory Access Layer (MAL) provides capability both Ethernet channels
four serial port UARTs 8-pin, 4-pin, 2-pin, 4-pin 2-pin) (with integrated Boot Strap Controller) serial interface 4-channel available internal external Programmable interrupt controller with external inputs, internal inputs Programmable timers General-purpose (64) Support JTAG board testing RISCWatchdebugger Details features core interface connect CoreConnect PLB4 100-133MHz, 128-bit data read write buses, 36-bit address Performance monitor Bridge PLB3, 100-133MHz, PCI, EBC, Ethernet, peripherals On-chip Double Data Rate (DDR) SDRAM controller 32-bit interface with optional 13-bit addressing GBps peak data rate Support banks 256MB, maximum capacity Support 128, 256, 512Mb devices, with latencies 2.5, interface 32-bit V2.2, with 3.3V interface, frequencies 66MHz Multiple read prefetch write post buffers
PowerPC 440EP Specifications
Technology (CMOS) Performance (est.) Frequency Memory Typical power dissipation Case temperature range Power supply Signal I/Os Packaging 0.13 CMOS CU-11 Copper Dhrystone MIPS 333MHz 1,066 Dhrystone MIPS 533MHz 533MHz 32-bit width: 800MBps (DDR200) 1.1GBps (DDR266) 32-bit, 66MHz 533MHz (preliminary estimate, application dependent) -40° 1.5V (logic), 2.5V (SDRAM/Ethernet/USB), 3.3V (other I/O) 456-e-PBGA, 35mm 35mm (with 1.27mm pitch)
Ability boot processor from memory host, host muxed with device device UTMI device device supports points out), 1024 Byte FIFO (double buffering byte packets) stage with MFLOPS/ (SP/DP) Hardware support IEEE Single-precision doubleprecision operation Single cycle throughput most instructions Thirty-two 64-bit floating point registers External controller 50-66MHz 8-bit 16-bit external data width 30-bit address Support ROM, EPROM, SRAM, Flash, slave peripheral devices External master support Nand Flash controller Block-oriented device, accessed manner much like diskette
drives with pages, blocks, and, some devices, zones districts banks Nand Flash supported Direct interfacing Discrete Nand Flash devices devices) SmartMedia Card socket (22-pins) Device sizes 4MB-256MB supported 512-byte 16-byte 64byte device page sizes supported Boot-from-Nand: Execute linear sequence boot code single page block (512bytes) Support allow direct, noprocessor-intervention block copy from Nand Flash SDRAM providing single error correction double error detection each 256-bytes stored data Chip selects shared with controller independent channels supporting internal external peripherals
Option external internal channels Support memory-to-memory, peripheral-to-memory, memory-to-peripheral transfers Scatter/gather capability 32-byte buffer with programmable thresholds On-chip Ethernet Multi-speed: full half duplex 10/100 Mbps RMII ports Packet reject interface support Other on-chip peripherals serial ports configurable 8-pin 4-pin four 2-pin 4-pin 2-pin controllers, compliant with Philips spec serial peripheral interface (SPI) GPIO, shared with other signals external interrupts General purpose timers Debug support JTAG RISCTraceinterface RISCWatch support
Development tools support PowerPC embedded processors supported more than hundred third-party vendors through PowerPC Embedded Tools program. This program provides compilers, debuggers, real-time operating systems, emulators, logic analyzers, full range tools help manufacturers develop products more quickly. PowerPC 440EP reference board will available help expedite product evaluation project development. more information, visit site www.ibm.com/powerpc.
Copyright Corporation 2001, 2002, 2003 Rights Reserved Printed United States America 9-03 following trademarks International Business Machines Corporation United States, other countries, both: Logo CoreConnect PowerPC PowerPC Logo RISCTrace RISCWatch Other company, product service names trademarks service marks others. This document contains information product under development IBM. reserves right change discontinue this product without notice. While information contained herein believed accurate, such information preliminary, should relied upon accuracy completeness, representations warranties accuracy completeness made. information contained this document subject change without notice. products described this document intended applications such implantation, life support other hazardous uses where malfunction could result death, bodily injury, catastrophic property damage. information contained this document does affect change IBM's product specifications warranties. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. information contained this document obtained specific environments, presented illustration. results obtained other operating environments vary. INFORMATION CONTAINED THIS DOCUMENT PROVIDED BASIS WITHOUT EXPRESS IMPLIED WARRANTY KIND, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. event will liable damages arising directly indirectly from information contained this document. Microelectronics Division 2070 Route Bldg. Hopewell Junction, 12533-6351 home page found http://www.ibm.com Microelectronics Division home page found http://www.chips.ibm.com receive latest updates PowerPC technical information from Microelectronics, subscribe tech e-mail www.chips.ibm.com/techemail.

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