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PowerPC 440GP Embedded Processor Highlights Delivers 400MHz
Top Searches for this datasheetHighly integrated processor offers leading-edge performance PowerPC 440GP Embedded Processor Highlights Delivers 400MHz 500MHz performance high-speed embedded designs 32-bit implementation Book Enhanced PowerPC® architecture State-of -the-art peripherals including SDRAM PCI-X Incorporates performanceenhancing features, including superscalar operation, large caches, high-speed CoreConnectbus technology Offers power dissipation small form factor high-density power-conscious applications Provides application code compatibility with other PowerPC processors IBM's advanced 0.18-micron CMOS copper process technology innovative design provide power dissipation small footprint. Application code compatibility with other PowerPC processors enables manufacturers bring products market quickly cost satisfy changing needs. High integration, including on-chip SRAM robust peripheral support, further simplify board design help reduce manufacturing costs. PowerPC Core: designed high performance leadership performance PowerPC core derives from IBM's state-of-the-art CMOS techAdvanced technology most demanding networking storage applications PowerPC 440GP embedded processor offers exceptional performance, design flexibility, robust features geared demanding networking, storage, other embedded applications. With speeds 500MHz, PowerPC Book architecture, rich peripheral mix, PowerPC 440GP processors ideally suited wide range high-performance applications. memory management unit (MMU) allows software developer configure cache regions three modes allow application optimization: locked regions used low-latency code interrupt service routines; transient regions handle use-once data without disturbing whole cache; normal regions, which typical least-recently-used (LRU) algorithms. nology applied embedded-application requirements. PowerPC superscalar core incorporates 7-stage pipeline executes instructions cycle, enhancing overall throughput. core's large data cache (32K) instruction cache (32K) 64-way associative, with versatile configurations enhance performance tuning. also supports multiple page sizes, further contributing PowerPC core's memory efficiency maximizing translation lookaside buffer (TLB) hits. added system performance, PowerPC includes dynamic branch prediction, instructions, non-blocking caches that managed either write-through write-back mode. Wide data paths simultaneous reads writes boost throughput PowerPC 440GP CoreConnect 128-bit Processor Local (PLB) separate read write data buses that offer 4.2GBps on-chip bandwidth (peak). With 36-bit address path, offers 64GB memory addressability. integrated performance monitor enables performance tuning maximize on-chip resource utilization. 32-bit On-Chip Peripheral (OPB) collects less demanding devices improve utilization. Book Enhanced PowerPC Architecture Book Enhanced PowerPC architecture features increased architectural flexibility optimized embedded applications. adaptable memory management features robust debug capabilities geared real-time other highperformance operating environments. Book PowerPC architecture addresses requirements embedded applications while providing application code compatibility with current PowerPC applications. Robust features provide design flexibility PowerPC 440GP incorporates range versatile features that complement processor core powerful solution diverse embedded applications: External masters access internal devices Controller independent channels supporting internal external peripherals Support memory-to-memory, peripheral-to-memory, memory-to-peripheral transfers Scatter/gather capability 128-byte buffer with programmable thresholds On-chip Double Data Rate (DDR) SDRAM Controller 32-bit 64-bit interface with optional GBps peak data rate Support 128, 256Mb devices On-chip Ethernet Multi-speed: full half duplex 10/100 Mbps MII, RMII, SMII ports PCI-X Interface 32-bit 64-bit PCI-X V1.0, frequencies 133MHz 32-bit 64-bit V2.0, frequencies 66MHz Multiple read prefetch write post buffers Ability boot processor from PCI-X memory on-chip SRAM Other on-chip Peripherals serial ports, 9-pin 5-pin controllers, compliant with Phillips spec GPIO external interrupts General purpose timers External Controller 16-, 32-bit external data width 32-bit address Support ROM, EPROM, SRAM, Flash, slave peripheral devices Debug support JTAG RISCTraceinterface RISCWatchsupport SDRAM Controller Arbiter PCI-X Bridge Monitor RAM/ROM Peripheral Controller Ext. Master Controller On-Chip Peripheral (OPB) Processor Local (PLB) 128-Bit I-Cache D-Cache SRAM Control SRAM Bridge UART Controller Interrupt Control Timers Arbiter 32-Bit GPIO 10/100 Ethernet JTAG Trace PowerPC Core 440GP block diagram PowerPC 440GP Specifications Technology Performance (est.) 0.18µm (0.11-µm CMOS SA-27E Copper Dhrystone MIPS 400MHz Dhrystone MIPS 466MHz 1,000 Dhrystone MIPS 500MHz 500MHz Memory 32-bit width: 800MBps (DDR200) 1.1GBps (DDR266) 64-bit width: 1.6GBps (DDR200) GBps (DDR266) 66MHz PCI-X 133MHz Frequency Typical Power Dissipation 400MHz Case Temperature Range -40° 85°C Power Supply Signal I/Os Packaging 1.8V (logic), 2.5V (SDRAM), 3.3V (I/O) 552-ball, 25mm 25mm CBGA (with 1.0mm pitch) Development tools support PowerPC embedded processors supported more than third-party vendors through PowerPC Embedded Tools program. This program provides compilers, debuggers, real-time operating systems, emulators, logic analyzers, full range tools help manufacturers develop products more quickly. PowerPC 440GP reference board available help expedite product evaluation project development. more information, visit site www.ibm.com/chips. Copyright Corporation 2002 Rights Reserved Printed United States America 3-02 following trademarks International Business Machines Corporation United States, other countries, both: Logo CoreConnect PowerPC PowerPC Logo RISCWatch RISCTrace Other company, product service names trademarks service marks others. information contained this document subject change without notice. products described this document intended implantation other life support applications where malfunction result injury death persons. information contained this document does affect change product specifications warranties. Nothing this document shall operate express implied license indemnity under intellectual property rights third parties. information contained this document obtained specific environments, presented illustration. results obtained other operating environments vary. INFORMATION CONTAINED THIS DOCUMENT PROVIDED BASIS. event will liable damages arising directly indirectly from information contained this document. Microelectronics Division 2070 Route Bldg. Hopewell Junction, 12533-6351 home page found ibm.com. Microelectronics Division home page found ibm.com /chips. receive latest updates PowerPC technical information from Microelectronics, subscribe tech e-mail ibm.com /chips/newsbriefs. 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