8-Bit with embedded program memory, 12-ch 14-Bit converter, noise ampl
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
FS9823 Datasheet [V1.0]
Contents
Description,Feature Application-Block Diagram -Package Assignment -Pin Description -Electronic Characteristic -Function Description Core Power System Clock System -4.Dual Programmable Counter bits Timer
Page
Watch Timer Port Module -10. Function Network -11. Application Guide-12. OPAMP Application -13. Driver-14 Halt Sleep Mode -Package Outline
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Description
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
FS9823 CMOS 8-bit single chip microcontroller with embedded 8kx16 bits one-time pregramming ROM, 12-channel 14-bit fully differential input analog digital converter, noise amplifier, driver. FS9823 best suited applications such feature electrical scale, memter, sensor transducer measurement application etc.
Feature
8-bit microcontroller, single word instructions. Embedded bits program memory, 384-byte data memory. Voltage operation ranges from 2.2V 3.6V. Embedded oscillator. External 32768Hz crystal oscillator (RTC). Embedded Voltage Reset (LVR) Voltage Detector (LVD). Operation current less than sleep mode current about 3uA. 8-level deep hardware stacks. Interrupt sources (external: internal: 12-channel with program output rate resolution. Embedded charge pumper (Voltage double) voltage regulator (3.6V regulated output). Embedded bandgap voltage reference (typical 1.18V±50mV, 100ppm/°C). Internal silicon temperature sensor. noise (1uV without chopper, 0.5uV with chopper, 0.1Hz~1Hz) OPAMP with chopper controller. Dual 16-bit Programmable counter Watchdog timer. 28-bit bi-directional port (Pulse Density Modulator) output Buzzer output. serial port (slave mode only). drivers. Package: dice form (98-pin), 100-pin QFP.
Application
Sensor Transducer measurement application Product Electrical scale, meter.
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Block Diagram
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Driver
8kx16 Program Memory
byte Data Memory
Voltage Double Voltage Regulator Common Generator Bandgap Reference Temperature sensor
8bit
Internal/External Oscillator
Analog Input Multiplex
Port External Interrupt output Serial Buzzer output
Timer
Noise Amplifier
Dual Programmable Counter
Analog Digital Converter
Watch Timer
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Package Assignment
SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
COM2 COM1 VDDA VSSP VDDP XOUT PT2<2>/PDM1 PT2<5>/PDM2 PT1<0>/AIN0 PT1<1>/AIN1 PT1<2>/AIN2 PT1<3>/AIN3 PT1<4>/AIN4 PT1<5>/AIN5 PT1<6>/AIN6 PT1<7>/AIN7 PT2<0>/INT0 PT2<1>/INT1 PT3<0>/INT2 AGND REFO OP2O OP1O PT3<1>/INT3 PT2<3>/SDA PT2<4>/SCL PT2<7>/BZ
SEG26
COM3
COM4
9823
SEG37 SEG38 SEG39 SEG40 PT4<3> PT4<2> PT4<1> PT4<0> PT3<7>/AIN11 PT3<6>/AIN10 PT3<5>/AIN9 PT3<4>/AIN8 PT3<2> /PFI PT3<3> /PFO
PT2<6>
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Description
Name OP2O OP1O REFO FTB, AGND PT1<0~7>/AIN0~7, PT3<4~7>/AIN8~11 PT2<0~1>/INT0~1, PT3<0~1>/INT2~3 PT2<2,5>/PDM1,2 PT2<3>/SDA PT2<4>/SCL PT2<7>/BZ PT3<2>/PFI PT3<3>/PFO PT2<6>, PT4<0~3> SEG40~SEG1 COM4~COM1 V3,V2,V1 VDDA VSSP VDDP XOUT
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
In/Out 11~18 31~34 19~20 27~28 21,24 35~38 39~78 79~82 85~87
Description Programming Power Supply OPAMP Output OPAMP Output Band Reference Output Pre-Filter Capacitor Connection Analog Circuit Bias Current Input Analog Ground Digital Port Analog input channel Digital Port External Interrupt input Digital Port output Digital Port serial Bi-Directional data line Digital Port clock input Digital Port Buzzer Output Digital Port Programmable Frequency Input Digital Port Programmable Frequency Output Digital Port Segment Driver Output Common Driver Output Charge Pump Capacitor Positive Connection Charge Pump Capacitor Negative Connection Bias Analog Power Output Voltage Source from VDDA Charge Pump Voltage Charge Pump Negative Power Supply Charge Pump Capacitor Negative Connection Charge Pump Capacitor Positive Connection Charge Pump Positive Power Supply Positive Power Supply Negative Power Supply (Ground) 32768Hz Oscillator Output 32768Hz Oscillator Input Testing Mode Reset Connection
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Electronic Characteristic
Absolute Maximum Ratings
Parameter Supply Voltage Ground Potential Applied Input/Output Voltage Ambient Operating Temperature Storage Temperature Soldering Temperature, Time Rating -0.3 -0.3 VDD+0.3 +150 260°C, Unit
Characteristic (Unless otherwise specified VDD=3VTa=25)
Symbol IDD1 Parameter Recommend Operation Power Voltage Supply Current Test Condition Units
MCK=1MHz, CPUCLK=MCK/2, Charge Pump, ADC,OPAMP IDD2 Supply Current Internal Oscillator Off, MCK=32768Hz Sleep Mode Supply Current Sleep Mode Digital Input High Voltage PT1, Reset Digital Input Voltage PT1, Reset VIHSH Input Hys. High Voltage Schmitt-trigger port VIHSL Input Hys. Voltage Schmitt-trigger port Pull Current Vin=0 High Level Output Current VOH=VDD-0.3 Level Output Current VOL=0.3 VDDA Analog Power IREG VDDA Regulator Output VDD=3V Current Internal Voltage Double VDDA=0.95*VDD A(unload) VCVDDA VDDA Voltage Coefficient AGND Analog Ground Voltage VREF Build Reference Voltage AGND TCREF Build Reference Voltage Ta=0~50 Temperature Coefficient S_LB [1:0]=00 VLBAT Battery Detector Voltage S_LB [1:0]=01 Switch Resister Internal oscillator FWDT Internal Clock
0.45 0.20
VDDA/2 1.18
ppm/
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Characteristic (Unless otherwise specified VDD=3VTa=25)
Symbol VACIN VADIN Parameter Test Condition Common Mode Input INH,INL,VRH,VRL Range Differential Mode Input (INH,INL),(VRH,V Range Resolution Linearity Error VRFIN=0.44V Input Offset Voltage VRFIN=0.44V With Zero Cancellation VAIN=0 ±15625 Units Counts
-0.1
+0.1
OPAMP Characteristic (Unless otherwise specified VDD=3VTa=25)
Symbol Parameter Input Offset Input Offset Voltage with Chopper Input Reference Noise Input Reference Noise with Chopper Input Bias Current Input Bias Current with Chopper Input Common Mode Range Output Voltage Range Chopper Clock Frequency Capacitor Load S_CHCK[1:0]=11 Rs<100 Rs=100, 0.1Hz~1Hz Rs=100, 0.1Hz~1Hz Test Condition Units µVpp µVpp
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Function Description
Core
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
1.1. Program Memory Organization
13-bit program counter capable address program memory space. reset vector 0000h interrupt vector 0004h.
eset ector Program onter Interrupt ector 0004h 0000h
tack evel tack evel tack evel tack evel tack evel tack evel tack evel tack evel 1FFFh
1.2. Data Memory Organization
data memory partitioned into three parts. address 00h~07h 16~17h areas system special registers, like indirect address, indirect address pointer, status register, working register, interrupt flag, interrupt control register. address 08h~7Fh areas peripheral special registers, like ports, timer, ADC, signal conditional network control register, driver. address 80h~1FFh areas general data memory. Address Name IND0 IND1 FSR0 FSR1 STATUS WORK INTF INTE INTF2 INTE2 08h~7Fh 80h~FFh 100h~1FFh Content mean unknown unchanged) contents FSR0 address data memory contents FSR1 address data memory Indirect data memory, address point Indirect data memory, address point IRP1 IRP0 WORK register TMIF I2CIF ADIF TMIE I2CIE ADIE CTIF CTIE Peripheral special registers General data Memory page General data Memory page Reset State uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 00u00uuu uuuuuuuu 00000000 00000000 00000000 00000000 uuuuuuuu uuuuuuuu
E1IF E1IE E3IF E3IE
E0IF E0IE E2IF E2IE
IND0, IND1: indirect addressing mode address FSR0, FSR1: indirect addressing mode point
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
IRP0: Indirect address page select. IRP1: Indirect address page select. Power down Flag. Cleared writing power-on reset. sleep instruction Watch Time Flag. Cleared writing power-on reset. Watch Time Digit Carry Flag, ADDWF(C) SUBWF(C), this there carry from order resultant. Carry Flag (~Borrow) Zero Flag E0IF, E0IE: PT2.0 External Interrupt flag enable. E1IF, E1IE: PT2.1 External Interrupt flag enable. E2IF, E2IE: PT3.0 External Interrupt flag enable. E3IF, E3IE: PT3.1 External Interrupt flag enable. ADIF, ADIE: Analog digital converter Interrupt flag enable. CTIF, CTIE: Dual 16bit programmable counter Interrupt flag enable. TMIF, TMIE: 8-bit Timer Interrupt flag enable. I2CIF, I2CIE: Interface Interrupt flag enable. GIE: Global interrupt enable.
1.3. Peripheral special registers
Address Name CTAH CTAL CTBH CTBL CTCON TMOUT TMCON ADOH ADOL ADCON NETA NETB NETC NETD NETE NETF PT1EN PT1PU AIENB1 PT2EN PT2PU PT2MR Content mean unknown unchanged) CTA[15:8] CTA[7:0] CTB[15:8] CTB[7:0] MUXSEL[2:0] FQTMB Reset State uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 0000000u 0uuuu000 00000000 1uuu0000 00000000 00000000 uuuu0000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 uuuuuuuu uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu
Ver.
WDTCON WTDTEN
OVAB [2:0] [2:0]
TMOUT [7:0] TMEN [15:8] [7:0] ADRST M7_CK M6_CK M5_CK M3_CK M2_CK ENPUMP S_CH2CK [1:0] S_CH1CK [1:0] SINL[1:0] SINH[2:0] SOP2N[1:0] SOP1N[1:0] SVRL[1:0] SREFO ADG[1:0] OP2EN SOP2P[2:0] OP1EN ENVS SILB[1:0] ENBAND ENVDDA TRST [7:0] PT1EN [7:0] PT1PU [7:0] AIENB[7:0] [7:0] PT2EN [7:0] PT2PU [7:0] PM1EN E1M[1:0] [7:0]
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[2:0] M1_CK M0_CK S_BEEP S_PCK SFTA[2:0] SVRH[1:0] ADEN SOP1P[2:0] ENLB ENAGND ENVB LBOUT
BZEN
PM2EN
E0M[1:0]
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PT3EN PT3PU PT3MR PT4EN PT4PU AIENB2 PMD1H PMD1L PMD2H PMD2L PMCON PT2OCB LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19 LCD20 LCDENR I2CCON I2CSTA I2CADD I2CBUF
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers PT3EN [7:0] PT3PU [7:0] PFOEN E3M[1:0] 00000000 00000000 E2M[1:0] 00000000 [3:0] uuuuuuuu PT4EN [3:0] uuuu0000 PT4PU [3:0] uuuu0000 0000uuuu 00000000 00000000 00000000 00000000 PMCS[2:0] 00000000 uuu11uuu SEG1 [3:0] uuuuuuuu SEG3 [3:0] uuuuuuuu SEG5 [3:0] uuuuuuuu SEG7 [3:0] uuuuuuuu SEG9 [3:0] uuuuuuuu SEG11 [3:0] uuuuuuuu SEG13 [3:0] uuuuuuuu SEG15 [3:0] uuuuuuuu SEG17 [3:0] uuuuuuuu SEG19 [3:0] uuuuuuuu SEG21 [3:0] uuuuuuuu SEG23 [3:0] uuuuuuuu SEG25 [3:0] uuuuuuuu SEG27 [3:0] uuuuuuuu SEG29 [3:0] uuuuuuuu SEG31 [3:0] uuuuuuuu SEG33 [3:0] uuuuuuuu SEG35 [3:0] uuuuuuuu SEG37 [3:0] uuuuuuuu SEG39 [3:0] uuuuuuuu LCD_DUTY[1:0] ENPMPL 00000000 0001uuuu uu0000u0 00000000 00000000
AIENB[11:8] PMD1[15:8] PMD1[7:0] PMD2[15:8] PMD2[7:0] PDMEN PT2OC[4:3] SEG2 [3:0]] SEG4 [3:0] SEG6 [3:0] SEG8 [3:0] SEG10 [3:0] SEG12 [3:0] SEG14 [3:0] SEG16 [3:0] SEG18 [3:0] SEG20 [3:0] SEG22 [3:0] SEG24 [3:0] SEG26 [3:0] SEG28 [3:0] SEG30 [3:0] SEG32 [3:0] SEG34 [3:0] SEG36 [3:0] SEG38 [3:0] SEG40 [3:0] LCDCKS [1:0] LCDEN WCOL I2COV I2CEN
LEVEL I2CADD [7:0] I2CBUF [7:0]
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
1.4. Special Register External Reset (Power Reset) Reset State
Address Name STATUS
WDTCON
PT1EN PT1PU AIENB1 PT2EN PT2PU PT2MR PT3EN PT3PU PT3MR PT4EN PT4PU AIENB2 PT2OC I2CCON I2CSTA I2CADD I2CBUF
External Reset 00u00uuu 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 uuuu0000 uuuu0000 0000uuuu uuu11uuu 0001uuuu uu0000u0 00000000 00000000
Reset uuuu1uuu uuuuu000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu
Other special register reset state same Power reset.
1.4. Instruction
INSTRUCTION CLRF ADDWF INCF INCFSZ DECF DECFSZ SUBWF COMF MOVWF MOVFW ADDWFC ANDWF IORWF XORWF
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OPERATION operation d=f+W d=f+1 d=f+1 skip d=f-1 d=f-1 skip f+(~W)+1 d=~f d=f+W+C d=f&W d=f|W d=f^W [7:0]=f [7:0],
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FLAG None None None None None
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SUBWFC ADDLW SUBLW ANDLW IORLW XORLW MOVLW RETLW CALL GOTO RETFIE RETURN HALT SLEEP CLRWDT ADDPCW BTFSC
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers f+(~W)+1+C [7:0], c=C, [7:0] W=k+W W=k-W W=k&W W=k|W W=k^W RETURN Push PC+1 GOTO PC=k GIE=1 Stop clock Stop Clear watch timer PC=PC+1+{6{W [7], [6:0]} [b]=0 [b]=1 Skip f[b]=0 None None None None None None None None None None None None None
BTFSS Skip f[b]=1 memory address (00h FFh). work register. literal field, constant data label
destination select: store result d=1: store result memory address select (0~7). (f): content memory address program counter
Power System
Address Name NETE NETF Content mean unknown unchanged) S_PCK ENVS SILB[1:0] ENLB ENBAND ENVDDA ENAGND ENVB LBOUT ENPUMP Reset State 00000000 00000000 00000000 uuuuuuuu
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2.1. Voltage Doublers
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
10uF 10uF
2.2~3.6V
VDDP
2.1.1. VDDA voltage regulator input. When ENPUMP=1, voltage doublers active. voltage about times VDDP. When ENPUMP=0, input voltage voltage regulator power supply. 2.1.2 Prevent FS9822 chip malfunction when VSSP instant voltage lower than VSS, necessary connect resistor between VSSP. 2.1.3. Voltage doublers operation frequency selected S_PCK. details section clock system.
VSSP
ENPUMP
Voltage Doublers
S_PCK
2.2. Voltage Regulator
VDDA
Voltage Regulator
ENVDDA
2.2.1. VDDA power supply voltage analog circuit driver. When ENVDDA set, voltage regulator will active, VDDA=3.6V. Otherwise VDDA external regulated power supply input. 2.2.2. voltage source from VDDA. When ENVS switch short.
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ENVS
2.3. Analog Bias Circuit
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
10nF
Analog Bias Circuit
ENVB
2.3.1. Before active analog block, must ENVB. When internal voltage doublers. must connected 10nF capacitor reducing voltage doublers noise.
2.4. Analog Common Voltage Generator
Analog Common Voltage Generator
AGND
ENAGND
2.4.1. AGND analog common voltage. When ENAGND=1, analog common voltage generator will active. AGND VDDA.
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2.5. Battery Comparator
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
320.8K
AIN4
1.2V
SILB[1:0]
LBOUT
120K
230K
ENLB
ENLB
2.5.1. When ENLB=1, battery comparator will active. 2.5.2. SILB [1:0]: Detect input select.
SILB [1:0] Detect Voltage VDD<
2.6. Bandgap Voltage Temperature Sensor
REFO Bandgap Voltage Reference Temperature Sensor
TEMPH Function Network TEMPL ENBAND
2.6.1. REFO temperature coefficient bandgap voltage reference output. When ENBAND=1, circuit will active. output voltage AGND about 1.18V. Typical temperature coefficient 100ppm/°C. 2.6.1. {TEMPH, TEMPL} proportion ambient temperature. select them input transfer digital code. (Typical 550uV±50uV/°C)
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Clock System
Address Name Content mean unknown unchanged) M5_CK M3_CK M2_CK S_CH2CK [1:0] S_CH1CK [1:0]
25pF 25pF
M7_CK
M6_CK
M1_CK S_BEEP
M0_CK S_PCK
Reset State 00000000 00000000
32.768kHz
Internal Oscillator Circuit
32.768kHz Crystal Oscillator Circuit
3.1. Oscillator State
Input M7_CK Oscillator State Internal External Disable Disable Enable Enable Enable Disable Disable Enable Enable Disable
Sleep
M6_CK
M3_CK M0_CK ECK/2 M1_CK MCK/4
3.2. Instruction Cycle
3.2.1 When M2_CK=0, different operation clock cycle from order maintain stable output. applications where resolution more than 13-bits necessary, M2_CK should zero.
XOUT
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
3.2.2 CPU's operation clock cycle change M0_CK, M1_CK, M2_CK, M3_CK change. Users must make sure that switching made only after oscillator's output stabilized. command should added after switching. MCK,
M2_CK
M1_CK
Instruction Cycle MCK/6.5 MCK/12.5 MCK/2 MCK/4
3.3. Sample Frequency
M1_CK sample Frequency (ADCF) MCK/25 MCK/50
3.4. Beeper Clock
M0_CK S_BEEP Beeper Clock CLK/250 CLK/375 ECK/8
3.5. Voltage Doublers Operation Frequency
M0_CK S_PCK Voltage Doublers Operation Frequency MCK/200 MCK/100 ECK/32
3.6. Chopper Operation Amplifier Input Control Signal
S_CH1(2)CK S_CH1(2)CK Chopper Control Signal CLK/500 CLK/1000
3.7. Timer Module Input Clock
M5_CK Timer Module input Clock TMCLK CLK/1000 ECK/32
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Dual 16bit Programmable Counter
Address Name INTE INTF2 INTE2 CTAH CTAL CTBH CTBL CTCON PT3MR Content mean unknown unchanged) CTIF CTIE CTA[15:8] CTA[7:0] CTB[15:8] CTB[7:0] MUXSEL[2:0] FQTMB PFOEN Reset State 00000000 00000000 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 0000000u 00000000
OVAB
Data
MAXSEL[1:0] Internal Oscillator Instruction clock External Oscillator (00) (01) (10) PFII (11) MUXSEL[2]=1 MUXSEL[2]=0 CTA_CLK
counter (CTA)
Overflow
Reset
PT3<3>/PFO
Pulse Width Measurement Control
PT3<2>/PFI
OVAB=0 OVAB=1
PFOEN
CTB_CLK FQTMB
counter (CTB)
Overflow
4.1. [15:0]: Counter [15:0]: Counter ((FQTMB (TON 0)), then only write CTBH will write into same time (CTBH->CTAH, CTBL->CTAL). Otherwise can't write into CTA. 4.2. MUXSEL [1:0]: clock source select multiplexer. Inverting PFI. 4.3. Counter/Timer Mode: FQTMB MUXSEL OVAB counter, preload register. Counter time (10000h-CTAI)/CLK.
Software CTA_CLK Software Clear
XXXX
FFF9
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
FFF9
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
FFFA
FFFB
FFFC
XXXX
FFF9 Software Write into (CTA same CTB)
FFFA Software Write into
CTIF When CTIE=1 Software Clear Software Clear
Counter/Timer Mode
4.4. Pulse Width Measurement Mode: FQTMB MUXSEL OVAB Pulse width CTA/CLK., counting overflow Pulse still high, will generate interrupt signal will counting again, then Pulse from high low, will stop count
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Software PFII
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
CTA_CLK
XXXX
0000 Software Write into (CTA same CTB)
0001
0002
0003
0004
0005
0006
0007
0008
0009
CTIF When CTIE=1
Pulse Width Measurement Mode
4.5. Frequency Measurement Mode: FQTMB MUXSEL OVAB Frequency measurement. OVAB Frequency measurement. Frequency (CTB-CTBI)/ (10000h-CTAI)
PFII
Software CTA_CLK
CTB_CLK
FQTMB
XXXX
FFEA
FFEB
FFEC
FFED
FFEE
FFEF
FFF0
FFF1
FFF2
FFF3
FFF4
FFF5
FFF6
FFF7
FFF8
FFF9
FFFA
FFFB
FFFC
FFFD
FFFE
FFFF
0000
XXXX
FFEA
FFEB
FFEC
FFED
FFEE
FFEF
FFF0
FFF1
FFF2
Software Write into (CTA same CTB)
CTIF When CTIE=1
Frequency Measurement Mode
bits Timer
Address Name INTF INTE TMOUT TMCON Content mean unknown unchanged) TMIF TMIE TMOUT [7:0] TMEN Reset State 00000000 00000000 00000000 1uuu0000
TRST
[2:0]
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
TMOUT[7:0] TMEN bits Counter TMCLK Frequency Divider TMCLK/4 Reset
Timer Interrupt Signal
TMRST
5.1. Write address 0Fh; will send pulse TRST reset 8-bit counter. Then read TMCON "1". 5.2. TMEN=1, 8-bit counter will enabled. TMEN=0, 8-bit counter will stop. 5.3. TMOUT [7:0] output 8-bit counter. read-only. 5.4. [2:0] selects timer interrupt source. selection codes follows:
interrupt source TMOUT[0] TMOUT[1] TMOUT[2] TMOUT[3] TMOUT[4] TMOUT[5] TMOUT[6] TMOUT[7] Time TMCLK=1024Hz (ECK/32) 1/128 sec. 1/64 sec. 1/32 sec. 1/16 sec. sec. sec. sec. sec.
Watch Timer
Address Name STATUS WDTCON WTDTEN Content mean unknown unchanged) Reset State 00u00uuu 0uuuu000
[2:0]
WDTEN
Watch Timer Oscillator
WDTA[7:0]
bits Counter1
Multiplex
bits Counter2
WDTOUT
WDTS[2:0] CLRWDT
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
6.1. WDTEN "1": enable watchdog timer oscillator. "0": watchdog timer function will disabled. WDTEN write only. 6.2. When Counter overflows, will send WDTOUT reset flag. 6.3. CLRWDT instruction will reset Counter 6.4. [2:0] selects Counter code selections follows, 111: WDTA [0], 110: WDTA [1], 101: WDTA [2], 100: WDTA [3], 011: WDTA [4], 010: WDTA [5], 001: WDTA [6], 000: WDTA [7].
Port
Address Name INTF INTE INTF2 INTE2 PT1EN PT1PU AIENB1 PT2EN PT2PU PT2MR PT3EN PT3PU PT3MR PT4EN PT4PU AIENB2 PT2OCB Content mean unknown unchanged) I2CIF E1IF E0IF I2CIE E1IE E0IE CTIF E3IF E2IF CTIE E3IE E2IE [7:0] PT1EN [7:0] PT1PU [7:0] AIENB[7:0] [7:0] PT2EN [7:0] PT2PU [7:0] PM2EN PM1EN E1M[1:0] E0M[1:0] [7:0] PT3EN [7:0] PT3PU [7:0] PFOEN E3M[1:0] E2M[1:0] [3:0] PT4EN [3:0] PT4PU [3:0] AIENB[11:8] PT2OC[4:3] Reset State 00000000 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu uuuu0000 uuuu0000 0000uuuu uuu11uuu
BZEN
ports with pull-up resistor enable control. PT1(~4)PU [N]="0": PT1(~4) without pull-up resistor, "1": PT1(~4) with pull-up resistor PT1(~4)EN ="0": PT1(~4) input port, "1": PT1(~4) output port (~4) data register port.
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
7.1. Digital Port with Analog input channel shared: PT1<0> PT1<7>, PT3<4> PT3<7>
PT3PU[7:4], PT1PU[7:0] Databus[7:0]
PT3[7:4], PT1[7:0] AR==PT3, Write LOAD PT3EN[7:4], PT1EN[7:0]
AIENB[11:0]
READ&AR==PT3,
AIN11~AIN0
7.1.1. AIENB] ="0", this port Analog input channel (AIN0 AIN11), "1": This port Digital port. 7.1.2 VDDA Regulator must enable first then AIN0~AIN7 will work normal, otherwise AIN0~AIN5 work abnormal parasitic diode which between AIN0~AIN7 VDDA active. When leakage current will happened. 7.1.3 want keep operation current sleep mode. AINENB=1 PT1, [7:4] floating pull down. PT2, [3:0], PT4, state.
7.2. Digital Port External Interrupt input PT2<0>, PT2<1>, PT3<0>, PT3<1>
PT2PU[1:0], PT3[1:0] Databus[7:0]
PT2[1:0], PT3[1:0] AR==PT2, Write LOAD PT2EN[1:0], PT3EN[1:0]
READ&AR==PT2,
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
7.2.1. PT2<0>/INT0, PT2<1>/INT1, PT3<0>/INT2, PT3<1>/INT3 external interrupt sources. Interrupt mode controlled E0(~3)M [1:0]="00": negative edge, "01": positive edge, "10"&"11": interrupt when change. 7.2.1. There Schmitt-trigger input.
7.3. Digital Port output PT2<2>, PT2<5>
PT2PU[2, Databus[7:0]
PT2[2, AR==PT2 Write LOAD PT2EN[2,
READ&AR==PT2
7.3.1. PT2<2> Schmitt-trigger input. PT2<5> not. 7.3.2. When EN="1" PT2EN [2(5)] ="1", PT2<2(5)> Output. 7.3.3. details section (Pulse Density Modulator) Module.
7.4. Digital Port serial port PT2<3>/SDA, PT2<4>/SCL
PT2PU[4:3] Databus[7:0] PT2OC[4:3] Open Drain Control PT2[4:3] AR==PT2 Write LOAD PT2EN[4:3]
READ&AR==PT2
7.4.1. When PT2OC [3(4)] ="1": [3(4)] open-drain;"0": [3(4)] normal digital port.
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
7.4.2. There Schmitt-trigger input. 7.4.3. details section module.
7.5. Digital Port Buzzer output PT2<7>
PT2PU[7] Databus[7:0]
PT2[7] AR==PT2 Write LOAD PT2EN[7]
READ&AR==PT2
7.5.1. PT2EN ="1" BZEN="1", buzzer output.
7.6. Digital Port Programmable Frequency Port PT3<2>/PFI, PT3<3>/PFO
PT3PU[3:2] Databus[7:0]
PT3[3:2] AR==PT3 Write LOAD PT3EN[3:2]
READ&AR==PT3
7.6.1. Schmitt-trigger input. 7.6.2. PT3EN ="1" PFOEN="1", output. 7.6.3. details section "Dual 16-bit programmable counter".
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
7.7. Digital Port with Schmitt-trigger input. PT4<0>, PT4<1>
PT4PU[1:0] Databus[7:0]
PT4[1:0] AR==PT4 Write LOAD PT4EN[1:0]
READ&AR==PT4
7.7.1. Schmitt-trigger input.
7.8. Digital Port PT2<6>, PT4<2>, PT4<3>
PT2PU[6], PT4PU[3:2] Databus[7:0]
PT2[6], PT4[3:2] AR==PT2, Write LOAD PT2EN[6], PT4[3:2]
READ&AR==PT2,
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
(Pulse Density Modulator) Module
Address Name PT2MR PMD1H PMD1L PMD2H PMD2L PMCON
PDM15 PDM14 PDM13 PDMO= (PDMD[x] PDMx) Example: PDMD=6000h PDMO x=0~15
PM2EN
Content mean unknown unchanged) PM1EN PMD1[15:8] PMD1[7:0] PMD2[15:8] PMD2[7:0] PDMEN PMCS[2:0]
Reset State 00000000 00000000 00000000 00000000 00000000 00000000
8.1. PMEN: Enable Module. When EN="1" PT2EN [2(5)] ="1", PT2<2(5)> Output. 8.2. PMCS: Select Input Frequency
PWCS Pulse Width 1/MCK 2/MCK 4/MCK 8/MCK 16/MCK 32/MCK 64/MCK 128/MCK
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(slave mode only)
Address Name INTF INTE I2CCON I2CSTA I2CADD I2CBUF
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
WCOL
I2COV
Content mean unknown unchanged) I2CIF I2CIE I2CEN I2CADD [7:0] I2CBUF [7:0]
Reset State 00000000 00000000 0001uuuu uu0000u0 00000000 00000000
Data
Write
Read
I2CBUF
PT2<4>/SCL
I2CSR
PT2<3>/SDA
Addr_Match
Match detect
I2CADD Set, Reset bits (I2CSTA Reg)
Start Stop detect
9.1. module implements standard specifications well 7-bit addressing. pins used data transfer. There PT2<4>/SCL pin, which clock, PT2<3>/SDA pin, which data. user must configure these pins open-drain through PTOCB [4:3]. I2CSR: Shift Register directly accessible. 9.2. I2CCON CONTROL REGISTER module. WCOL: Write collision detect. I2CBUF register written while still transmitting previous word. Must cleared software. collision. I2COV Receive overflow flag. byte received while I2CBUF still holding previous byte. I2COV don't care transmit mode. I2COV must cleared software either mode.
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
I2CEN functional enable. Enables serial port configures pins serial port pins. Disable serial port configures these pins port pins. both modes, when enabled, these pins must properly configured input output. release control. Enable clock. Holds clock (clock stretch) Note Used ensure data setup time. 9.3. I2CSTA STATUS REGISTER module Data/Address indicates that last byte received data indicates that last byte received address Stop bit. This cleared when module disabled (I2CEN cleared). Indicates that stop been detected last. Stop detected last. Start bit. This cleared when module disabled (I2CEN cleared). Indicates that start been detected last. Start detected last. Read/Write information. This holds information received following last address match. This only valid during transmission. users this software determine whether transmission reception progress. Read Write 9.4. I2CBUF BUFFER REGISTER module 9.5. I2CADD ADDRESS REGISTER module 9.6. Reception: When address byte clear address match occurs, I2CSTA register cleared. received address loaded into I2CBUF. When address byte overflow condition exists then acknowledges (ACK) pulse given. overflow condition defined either (I2CSTA<0>) I2COV (I2CCON<6>) set. I2CIF interrupt generated each data transfer byte. I2CIF must cleared software, I2CSTA register used determine status byte.
Receiving Address Receiving Data Receiving Data
I2CIF (INTF<3>)
Cleared software (I2CSTA<0>)
Master terminates transfer
I2CBUF read I2COV (I2CCON<6>) I2COV Because I2CBUF still full. sent.
Waveforms Reception
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
9.6. Transmission: When address byte address match occurs, I2CSTA register set. received address loaded into I2CBUF. pulse will sent ninth bit, held low. transmit data must loaded into I2CBUF register, which also loads I2CSR register. Then should enabled setting (I2CCON<4>). right data bits shifted falling edge input. This ensures that signal valid during high time. I2CIF interrupt generated each data transfer byte. I2CIF must cleared software, I2CSTA register used determine status byte. I2CIF falling edge ninth clock pulse. slave-transmitter, pulse from master-receiver latched rising edge ninth input pulse. line high (not ACK), then data transfer complete. slave then monitors another occurrence I2CSTA bit. line (ACK), transmit data must loaded into I2CBUF register, which also loads I2CSR register. Then should enabled setting (I2CCON<4>).
Receiving Address Transmitting Data
held while responds I2CIF
Data sampled
I2CIF (INTF<3>)
(I2CSTA<0>)
Cleared software I2CBUF written software
From I2CIF interrupt service routine
I2COV (I2CCON<6>) I2CBUF read
Waveforms Transmission
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Analog Function Network
Address Name INTF INTE ADOH ADOL ADCON NETA NETB NETC NETD Content mean unknown unchanged) ADIF ADIE S_CH2CK [1:0] S_CH1CK [1:0] [15:8] [7:0] ADRST [2:0] SINH[2:0] SFTA[2:0] SOP1N[1:0] SVRL[1:0] SVRH[1:0] ADG[1:0] ADEN SOP2P[2:0] OP1EN SOP1P[2:0] Reset State 00000000 00000000 00000000 00000000 00000000 uuuu0000 00000000 00000000 00000000 00000000
SINL[1:0] SOP2N[1:0] SREFO OP2EN
REFO
SREFO
SOP1P[2:0] AIN7 AIN6 AIN5 AIN4 AIN3 AIN2 OP1P AIN1 AIN0 SOP1N[1:0] AIN6 AIN5 OP1N AIN4 OP1O
OP1O
100K
S_CH1CK[1:0] OP1EN
VR1P
VR2P
AGND
SFTA[2]
SINH[2:0] OP2P OP2O AIN5 TEMPH FTIN OP1P OP1O
SFTA[1:0] AIN3 AIN2 FTIN SINL[1:0] TEMPL AIN3 AIN2 AIN1 OP2O
ADO[15:0] ADM[2:0] ADRST ADEN ADG[1:0]
SOP1P[2:0] AIN11 AIN10 AIN9 AIN8 AIN7 AIN6 OP2P AIN5 AIN4
SOP2N[1:0] AIN9 AIN8 OP2N AIN7 OP2O
S_CH2CK[1:0] OP2EN
SVRH[1:0] VR2P VR1P AIN3 AIN0 SVRL[1:0] VR2P AIN2 AIN1 AGND
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
10.1. Analog Digital Converter (ADC)
10.1.1. contains modulator digital comb filter. When ADRST=1, comb filter will enabled. When ADRST=0, comb filter will reset. ADEN=1 starts modulator. 10.1.2. output rate selected (N).
Output Rate ADCF/125 ADCF/250 ADCF/500 ADCF/1000 ADCF/2000 ADCF/4000 ADCF/8000 ADCF/8000
10.1.3. AZ=0 means that differential inputs (INH, INL); means that differential inputs (INL, INL). this mode measure offset. 10.1.4. [1:0] will input gain follows, 2/3, 1/3.
10.2. OPAMP: OP1,
10.2.1. OPAMP enable control signal. 10.2.2. S_CH1 [1:0] "3.6. Chopper Operation Amplifier Input Control Signal". input operation mode follows, +Offset, -Offset, CLK/500 chopper frequency, CLK/1000 Chopper frequency.
10.3. Analog Multiplex:
10.3.1. Pass Filter Input: SINH[2:0] Select OP1O OP1P TEMPH AIN5 OP2O OP2P
10.3.2. Negative Input: SINL[1:0] Select AIN1 AIN2 AIN3 TEMPL
10.3.3. Pass Filter Output, Positive Input: SFTA[1:0] Select FTIN AIN2 AIN3
10.3.4. External Filter Control: SFTA[2]=1, FTIN short; SFTA[2]=0, FTIN open. 10.3.5. Internal Reference Voltage Control: SREFO=1, REFO short; SREFO=0, REFO open. 10.3.6. Reference Voltage Negative Input: SVRL[1:0] Select
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AGID
AIN1
31/41
AIN2
VR2P
TD0310-0705 Ver.
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
10.3.7. Reference Voltage Positive Input: SVRH[1:0] Select 10.3.8. Positive Input: SOP1P[2:0] Select AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN0 AIN3 VR1P VR2P
10.3.9. Negative Input: SOP1N[1:0] Select 10.3.10. Positive Input: SOP2P[2:0] Select AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10 AIN11 OP1O AIN4 AIN5 AIN6
10.3.11. Negative Input: SOP2N[1:0] Select OP2O AIN7 AIN8 AIN9
Application Guide
used FS9823 with fully differential inputs fully differential reference voltage inputs. maximum output ±15625. conversion equation follows: Dout= 15625 (VIH-VIL+Vio) (VRH-VRL+Vro) ADC's positive input voltage, ADC's negative input voltage, ADC's offset input terminals, voltage positive input Reference Voltage, voltage negative input Reference Voltage, offset input terminals Reference Voltage. Where VRH-VRL+Vro>0. When (VIH-VIL+Vio) (VRH-VRL+Vro) Dout=15625. When (VIH-VIL+Vio) (VRH-VRL+Vro) Dout=-15625.
11.1. Output Format
read {ADOH,ADOL} ADC's 16-bit output. Note that output complement format, i.e., most significant (MSB) denotes negative number. example, {ADOH, ADOL} =E2F7h, then Dout= (not (E2F7h) -7433.
11.2. Linear Range.
close saturation when (VIH-VIL+Vio) (VRH-VRL+Vro) close good linearity range ±0.95.
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
11.3. Output Rate Settling Time
generally over-sampling ADC, i.e., every output results sampling times processed DSP. FS9823 sampling frequency decided M1_CK. ADCM decides send 16-bit output after sampling times interrupt signal every time changes output. fact, every output includes previous times sampling results. Generally speaking, inputs, reference voltage, ADG, switched, previous outputs normally stable ones, third output beyond stable.
11.4. Input Offset
Input Offset drifts with temperature common mode voltage inputs. When drifting slow, Doff= 15625 (Vio) (VRH-VRL+Vro) When measuring, Doff should deducted. relationships Doff with voltage inputs common mode reference voltage shown follows. 11.4.1. (VRH, AGND) =0.4V, VRL=AGND, VIH=VIL=VICM ADG=01
Doff VICM Counts -500 -1000
11.4.2.
(VRH, AGND) =0.5~1V, VRL=AGND, VIH=VIL=AGND ADG=01
Doff Reference Voltage 2000 1500 Counts 1000
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11.5. Gain
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
output deducted Doff Gain. Within operation range, changes Gain shown follows. results show that Gain does change changes. suggested values common mode voltages input reference voltage 1V~2V. 11.5.1. Gain VDD: (VRH, VRL) 1/3(REFO, AGND), (VIH, VIL) 1/6(REFO, AGND), VRL=VIL=AGND ADG=01 VDD=2.2V~3.6V
Gain 7827 7826 Counts 7825 7824 7823
11.5.2. Gain Voltage Inputs Common Mode: (VRH, VRL) =1/3(REFO, AGND), (VIH, VIL) =0.2V, VRL=AGND VICM=1/2(VIH+VIL) ADG=01
Gain VICM 8140 Counts 8120 8100 8080
11.5.3. Gain Voltage Reference Common Mode: (VRH, VRL) =0.4, (VIH, VIL) =1/6(REFO, AGND), VRCM=1/2(VRL+VRH) VIL=AGND ADG=01
Gain VRCM 7420 Counts 7400 7380 7360 7340
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11.6. Resolution
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
resolution mainly decided ADCM (ADC rate) reference voltage, results follows: 11.6.1. (VRH, VRL) =0.4V, (VIH, VIL) =0.2V, VRL=VIL=AGND.
Rolling counts
11.6.2. (VRH, VRL) =VR, (VIH, VIL) =1/2 VRL=VIL=AGND. ADM=101 Rolling counts 0.05
Noise Operation Amplifier Guide
input noise CMOS OPAMP generally much larger than Bipolar OPAMP. Moreover, flick noise (1/f noise) CMOS killer frequency small signal measurement. need input bias current Bipolar OPAMP causes that some transducers used. general, bipolar process good highly integrated ICs. FS9823 used special CMOS noise circuit design, under normal conditions, input noise controlled under 1uVpp (0.1Hz~1Hz). FS9823 good transducer applications because there need consider input bias current. Most input noise CMOS OPAMP comes from input differential amplification. S_CHCK switch differential amplification: positive Offset Voltage, negative Offset voltage. When using clock pulse switch input differential amplification, that called chopper mode. general, chopper frequency between KHz. Under chopper mode, input noise peak-to-peak voltage FS9823 less than 0.5uV (0.1Hz~1Hz). equivalent input current less than 100pA generated, effect switching.
12.1. Single Amplifier Application
Measurement small signal usually takes consideration drifting OPAMP offset voltage. Figure below, negative input connected AGND. also possible measure ADC's negative input deduct this value; order correct error caused Amplifier's offset voltage drifting. Because AGND provides current output applications, AIN1 used negative input measurement point avoid unnecessary voltage error. OPAMP input offset amplified amplifier then inputted ADC. much amplification cause OPAMP output move beyond linear operation range. Hence, under normal conditions, OPAMP amplification should less than times.
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FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
300k
AIN5 AIN2 AIN1
OP1O
FS9823
AGND
12.2. Differential Amplifier
Measurement differential signal often used bridge sensor applications. shown differential amplifier below, used power input bridge sensor, reference voltage also from after voltage division. When there small change output does change. Connecting AIN2 negative input adjust zero point bridge sensor. When starting chopper mode, amplification should less than times.
300k
AIN0
AIN5
SAIN2
Bridge sensor
OP1O
AIN3
300k
AIN2
AIN1
AIN1 AIN0
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Driver
Address Name LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCD9 LCD10 LCD11 LCD12 LCD13 LCD14 LCD15 LCD16 LCD17 LCD18 LCD19 LCD20 LCDENR
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Content mean unknown unchanged) SEG2 [3:0]] SEG1 [3:0] SEG4 [3:0] SEG3 [3:0] SEG6 [3:0] SEG5 [3:0] SEG8 [3:0] SEG7 [3:0] SEG10 [3:0] SEG9 [3:0] SEG12 [3:0] SEG11 [3:0] SEG14 [3:0] SEG13 [3:0] SEG16 [3:0] SEG15 [3:0] SEG18 [3:0] SEG17 [3:0] SEG20 [3:0] SEG19 [3:0] SEG22 [3:0] SEG21 [3:0] SEG24 [3:0] SEG23 [3:0] SEG26 [3:0] SEG25 [3:0] SEG28 [3:0] SEG27 [3:0] SEG30 [3:0] SEG29 [3:0] SEG32 [3:0] SEG31 [3:0] SEG34 [3:0] SEG33 [3:0] SEG36 [3:0] SEG35 [3:0] SEG38 [3:0] SEG37 [3:0] SEG40 [3:0] SEG39 [3:0] LCDCKS [1:0] LCDEN LEVEL LCD_DUTY[1:0]
Reset State uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu ENPMPL 00000000
13.1. LCDEN will start clock. LCD1~LCD20 display data area. 13.2. ENPMPL: enable charge pump. LEVEL: select bias, "0": bias, "1": bias. 13.3. LCDCKS [1:0] select frame frequency.
LCDCKS [1:0]
frame frequency(1/4 duty)
Input Frequecny/8 Input Frequecny/16 Input Frequecny/32 Input Frequecny/64
13.4. LCD_DUTY [1:0] select segment Duty cycle.
LCD_DUTY [1:0] General Output Port static frame frequency LCDCK LCDCK (4/2) LCDCK (4/3) LCDCK (4/4) bit3(7) COM4 Driving method bit2(6) bit1(5) COM2 COM3 COM2 COM3 COM2 bit0(4) COM1 COM1 COM1
13.5. Driving Methods There kinds driving methods selected LCD_DUTY [1:0] LEVEL driving waveforms driver below: VDD=3.0V
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duty, bias
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
duty, bias
4.5V 1.5V 4.5V 1.5V
COM1
COM2
COM3
COM4
segments COM1 side lighted
segments Frame Frame
duty, bias
1.5V
duty, bias
1.5V
COM1
COM2 COM3
COM4
segments COM1 side lighted
segments Frame Frame
Fortune Semiconductor TEL: +886-2-2809-4742 http://www.fsc.com.tw/ FAX: +886-2-2809-4874
38/41
TD0310-0705
Ver.
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
duty, bias
1.5V
static
1.5V
COM1
COM2
COM3
COM4
segments COM1 side lighted
segments Frame
Halt Sleep Modes
14.1. Halt Mode After executes Halt command, Program Counter (PC) Stops counting until interrupt command issued. avoid program errors caused Interrupt Return, suggested command after Halt guarantee program's normal execution. HALT 14.2. Sleep Mode After executes Sleep command, oscillators stop working until external interrupt command issued reset. avoid program errors caused Interrupt Return, suggested command after Sleep guarantee program's normal execution. Sleep make sure that consumes minimum power Sleep mode, necessary open power blocks analog circuits before issuing Sleep command, make sure Ports voltage levels. There exist parasitic diodes between VDDA analog input ports (see below Figure) When VDDA turned VDDA low, necessary keep AIN0~AIN11 Floating AINENB[11:0]=
AINx VDDA
recommended that users execute following program before issuing Sleep command: CLRF NETA CLRF NETB
Fortune Semiconductor TEL: +886-2-2809-4742 http://www.fsc.com.tw/ FAX: +886-2-2809-4874 39/41 TD0310-0705 Ver.
CLRF CLRF CLRF CLRF CLRF CLRF CLRF MOVLW MOVWF MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF CLRF MOVLW MOVWF CLRF CLRF CLRF MOVLW MOVWF SLEEP NETC NETD NETE NETF PT1PU PT1EN AINENB1 PT2PU 0FEh PT1EN 00Fh PT3EN AINENB2 PT3PU 0FFh PT3EN PT3PU INTF 081h INTE
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Analog Input
PT2[7:1] Output Low, PT2[0] Input /Pull
PT3[7:4] Analog Input
External Interrupt Enable
Fortune Semiconductor TEL: +886-2-2809-4742 http://www.fsc.com.tw/ FAX: +886-2-2809-4874
40/41
TD0310-0705
Ver.
Package Outline
FS9823
8-Bit with embedded program memory, 12-ch 14-Bit converter, noise amplifiers drivers
Fortune Semiconductor TEL: +886-2-2809-4742 http://www.fsc.com.tw/ FAX: +886-2-2809-4874
41/41
TD0310-0705
Ver.
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