8-Bit with embedded program memory, 6-ch 14-Bit converter, noise ampli
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
FS9932 Datasheet [V1.2]
Contents Page
DESCRIPTION.2
FEATURE APPLICATION. BLOCK DIAGRAM. PACKAGE ASSIGNMENT. DESCRIPTION. ELECTRONIC CHARACTERISTIC TYPICAL PERFORMANCE CHARACTERISTICS:. FUNCTION DESCRIPTION CORE POWER SYSTEM. CLOCK SYSTEM PORT BITS TIMER. (PULSE DENSITY MODULATOR) MODULE INPUT MULTIPLEX PASS FILTER CONTROL REGISTER APPLICATION GUIDE OPAMP CONTROL REGISTER NOISE OPERATION AMPLIFIER GUIDE DRIVER OUTPUT PORT RESET HALT SLEEP MODE
APPLICATION CIRCUIT PACKAGE OUTLINE
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Description
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
FS9932 high performance, cost CMOS 8-bit single chip microcontroller with embedded 2kx16 ROM, 6-channel 14-bit fully differential input analog digital converter, noise amplifier, driver. FS9932 best suited applications such cost body scale, barometer, hygrometer, etc.
Features
8-bit microcontroller, single word instructions. Embedded program memory, 128-byte data memory. operation voltage range from 2.4V 3.6V. Embedded 1.25 oscillator. External 32768Hz crystal oscillator (RTC) 4MHz oscillator (Mask options FS9932L 32768kHz FS9932H 4MHz). Operation current about 1.5mA; sleep mode current about 2uA. 6-layer hardware stacks. Interrupt sources (external: Input Port, internal: Timer, ADC). analog input channels
14-bit noise free with programmable output rate resolution. Embedded charge pump circuit (Voltage Doubler) voltage regulator (3.4V regulated output). Embedded bandgap voltage reference (typical 1.2V±50mV, 100ppm/°C). Internal silicon temperature sensor. noise (1uV peak-to-peak without chopper, 0.5uV peak-to-peak with chopper, 0.1Hz~1Hz) OPAMP with chopper controller. 10-bit bi-directional port including 1-bit buzzer output 1-bit output. driver peak-to-peak) 4-bit programmable output port. Watchdog timer. Package: dice form (52pin), 64-pin LQFP.
Application
Simple electronic scales: body scale, kitchen scale, pocket scale, etc. Baromemter Hygrometer Body meter Thermometer Other sensor transducer measurement application
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Block Diagram
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Driver Output port
Program Memory
Byte Data Memory
Voltage Doubler, Voltage Reglator, Common Generator, Bias Generator, Bandgap Reference Temperature Sensor
8-bit Core
Digital In/Out Port Exteranl Interrupt Input
Digital In/Out Port Buzzer Output Output Analog Input Multiplexer 8-bit Time Base Counter
Noise OPAMP
Analog Digital Converter
Watch Timer
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Configuration
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
COM4
SEG7
SEG10/PO6<0>
SEG11/PO6<1>
SEG8/PO5<0>
SEG9/PO5<1>
COM1
COM2
COM3
AGND
VDDA
VSSP
FS9932 LQFP
REFI
VDDP
REFO
OP1O
OP1N
XOUT
PT2<6>/PDM
PT1<2>/AD5
PT1<1>/AD4
PT1<0>/INT
PT2<7>/BZ WDTEN
PT1<7>
PT1<6>
PT1<5>
PT1<4>
PT1<3>
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Description
Name WDTEN PT2<7>/BZ PT2<6>/PDM P1<7>~P1<0> OP1N OP1O REFO REFI FT1, AD0~AD3 AGND SEG11~SEG8 SEG7~SEG0 COM4~COM1 VDDA VSSP VDDP XOUT
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
In/Out
6~13 24,25 26~29 33~36 37~44 45~48
Description Testing Mode Reset Watchdog Timer Enable Control Port Port Port Negative Power Supply (Ground) OPAMP Negative Input OPAMP Output Band Reference Output Reference Voltage Input Pre-Filter Capacitor Connection Analog Input Channel Analog Circuit Bias Current Input Analog Ground Segment Driver Output Output port Segment Driver Output Common Driver Output Voltage Source Analog Power Output Charge Pump Negative Power Supply Charge Pump Voltage Charge Pump Capacitor Positive Connection Charge Pump Capacitor Negative Connection Charge Pump Positive Power Supply Positive Power Supply 32768Hz 4MHz Oscillator Output 32768Hz 4MHz Oscillator Input Connection
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Electronic Characteristics
Absolute Maximum Ratings
Parameter Supply Voltage Ground Potential Applied Input/Output Voltage Ambient Operating Temperature Storage Temperature Rating -0.3 -0.3 VDD+0.3 +150 Unit
Characteristics (VDD=3VTa=25, Unless otherwise specified)
Symbol IDD1 Parameter Recommend Operation Power Voltage Supply Current1 Test Condition Units
IDD2
Supply Current2 Sleep Current Mode
Internal Oscillator Operation Power Block OPAMP 32.768kHz Operation Supply Sleep, enable
0.7xVDD 0.6xVDD
0.3xVDD 0.4xVDD ppm/
PT1, Reset PT1, Reset Digital Input Voltage Pull Current Vin=0 High Level Output Current VOH=0.9xVDD High Level Output Current VOL=0.1xVDD VDDA Analog Power KVCVDD Analog Power Supply Voltage Coefficient Voltage source Switch Resistor VREF Build Reference Voltage AGND KTCREF VREF Temperature Ta=0~50 Coefficient VLBAT Battery Detector S_LB [2:0]=011 Voltage VLCD Pk-Pk Driver Voltage FCK2 Internal oscillator Digital Input High Voltage
1.20 1.25
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Characteristics (VDD=3VTa=25, Unless otherwise specified)
Symbol VAIN VRFIN Parameter Test Condition Differential Input Range Reference Input Range (VRH,VRL), Gain=1 Resolution Linearity Error VRFIN=0.44V 0.25 Units Counts
-0.1
±15625
+0.1
OPAMP Characteristics (VDD=3VTa=25, Unless otherwise specified)
Symbol Parameter Input Offset Input Offset Voltage with Chopper Input Noise Peak Peak Voltage Input Noise Peak Peak Voltage with Chopper Input Bias Current Input Bias Current with Chopper Input Common Mode Range Output Voltage Range Maximum Capacitor Load Rs<100 Rs=100, 0.1Hz~1Hz Rs=100, 0.1Hz~1Hz Test Condition Units
µVpp µVpp
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Typical Performance Characteristics:
Internal Oscillator
Iout VDD=3V, CVGG=CAB=1uF Pump Clock= MCK/50 Pump Clock= MCK/200
1290 1280 1270 1260 1250 1240 1230 1220 1210 1200
Iout VDD=3V,CVGG=CAB=1uF, PCK=MCK/50
3.345 3.34 3.335 Degree 3.36 3.355 3.35 Temperature VDD=3V, CVGG=CAB=CVDDA=1uF, RL=1k
AGND Iout VDD=3V, AGND=1/2 VDDA, Iout=I(VDDA,AGND)
1.198 1.196 1.194 1.192 1.19 1.188 1.186 1.184 1.182
(REFO,AGND) Temperature VDD=3V, R(REFO,AGND)=50k
Degree
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Function Description
Core
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
1.1. Program Memory Organization
FS9932 11-bit program counter capable addressing program memory space. reset vector 0000h interrupt vector 0004h.
eset ector Program onter Interrupt ector
0000h
0004h
Stack evel Stack evel Stack evel Stack evel Stack evel Stack evel 07FFh
1.2. Data Memory Organization
data memory partitioned into three segments. segment with addresses 00h~07h system special registers, like indirect address, indirect address pointer, status register, working register, interrupt flag, interrupt control register. segment with addresses 08h~7Fh peripheral special registers, like ports, timer, ADC, signal conditional network control register, driver. segment with addresses 80h~FFh general data memory. Address
08h~7Fh 80h~FFh
Name
IND0 IND1 FSR0 FSR1 STATUS WORK INTF INTE WORK register TMIF TMIE contents FSR0 address data memory contents FSR1 address data memory Indirect data memory, address point Indirect data memory, address point
Content
ADIF ADIE
E0IF E0IE
Peripheral special registers General data Memory
IND0, IND1: indirect addressing mode address FSR0, FSR1: indirect addressing mode point
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Power Down Flag. Cleared writing power-on reset. sleep instruction Watch Time Flag. Cleared writing power-on reset. Watch Time Digit Carry Flag, ADDWF(C) SUBWF(C), this there carry from order resultant. Carry Flag (~Borrow) Zero Flag E0IF, E0IE: PT1.0 External Interrupt flag enable. ADIF, ADIE: Analog digital converter Interrupt flag enable. TMIF, TMIE: 8-bit Timer Interrupt flag enable. GIE: Global interrupt enable.
1.3. Peripheral special registers
Address Name TMOUT TMCON ADOH ADOL ADCON PT1EN PT1PU PT1MR PT2EN PT2PU PT2MR NETA NETB NETD NETF NETG NETH NETJ NETK PWDH PWDL PWCON LCD1 PT5O PT6O LCD6 LCD5 LCD4 LCD3 LCD2 LCDENR Content
M7_CK M6_CK M5_CK M4_CK M3_CK M2_CK M1_CK M0_CK S_CHCK [1:0] S_BEEP S_PCK TMOUT [7:0] TMEN [2:0] [15:8] [7:0] ADRST [2:0] [7:0] PT1EN [7:0] PT1PU [7:0] [1:0]
TRST
[2:0]
[7:6] PT2EN [7:6] PT2PU [7:6]
PWDE SOHM SINL [1:0] EN_VS
EN_VDDA
MODE SINH [2:0] SVRH EN_AGND S_AGND [1:0] EN_VB [1:0] ADEN OPEN SOP1P [2:0] SI_LB EN_LB S_LB [2:0] LBOUT PWMD [15:8] PWMD [7:0] PWEN PWCS [2:0] SEG0 [3:0] [1:0] [1:0] SEG10 [3:0] SEG8 [3:0] SEG6 [3:0] SEG4 [3:0] SEG2 [3:0] S_LCDO [1:0] [2:0] SVRL
EN_LCDB
SONE
EN_PUMP EN_BAND
SEG1 [3:0]
SEG11 [3:0] SEG9 [3:0] SEG7 [3:0] SEG5 [3:0] SEG3 [3:0] LCDCKS [1:0] LCDEN
Index
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1.4. Instruction
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
INSTRUCTION
CLRF ADDWF INCF INCFSZ DECF DECFSZ SUBWF COMF MOVWF MOVFW ADDWFC ANDWF IORWF XORWF SUBWFC ADDLW SUBLW ANDLW IORLW XORLW MOVLW RETLW CALL GOTO RETFIE RETURN HALT SLEEP CLRWDT ADDPCW BTFSC BTFSS
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OPERATION
operation d=f+W d=f+1 d=f+1 skip d=f-1 d=f-1 skip d=f-W d=~f d=f+W+C d=f&W d=f|W d=f^W [7:0]=f [7:0], d=f-W- (~C) [7:0], c=C, [7:0] W=k+W W=k-W W=k&W W=k|W W=k^W RETURN Push PC+1 GOTO PC=k GIE=1 Stop clock Stop Clear watch timer PC=PC+1+{6{W [7], [6:0]} [b]=0 [b]=1 Skip f[b]=0 Skip f[b]=1
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CYLCE
FLAG
None None None None None None None None None None None None None None None None None None
TD0305-2601 Ver.
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
memory address FFh). work register. literal field, constant data label destination select: store result d=1: store result memory address select (0~7). (f): content memory address program counter
Power System
Address Name NETF NETJ NETK Content
EN_LCDB EN_PUMP
EN_VS
EN_VDDA EN_BAND
EN_AGND S_AGND [1:0] EN_VB SI_LB EN_LB S_LB [2:0] LBOUT
2.1. Voltage Doubler
10uF 10uF
EN_PUMP
2.1.1. When EN_PUMP=1, voltage doubler enabled. voltage about times VDD. When EN_PUMP=0, input voltage voltage regulator power supply. 2.1.2. Voltage doubler operation frequency selected S_PCK. details described section "clock system". 2.1.3 Typical values 1uF~10uF. large load current, larger capacitors should used reduce output voltage ripple. polarity capacitor used should connected negative terminal capacitor, positive terminal.
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Voltage Doubler
S_PCK
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2.2. Voltage Regulator
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
VDDA
Voltage Regulator
EN_VDDA
2.2.1. VDDA power supply voltage analog circuit driver. When EN_VDDA set, voltage regulator will enabled. Otherwise VDDA used external regulated power supply input.
typical capacitance 1uF~10uF. large load current, large capacitor should used increase output voltage stability.
2.3. Analog Bias Circuit
10nF
2.3.1. Prior enabling analog block, EN_VB must set. When internal voltage doubler used, 10nF capacitor must connected between reducing voltage doubler's noise.
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Analog Bias Circuit
EN_VS
EN_VB
13/37 TD0305-2601 Ver.
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
2.4. Analog Common Voltage Generator
Analog Common Voltage Generator
AGND
EN_AGND S_AGND[1:0]
2.4.1. AGND analog common voltage. When EN_AGND=1, analog common voltage generator enabled. 2.4.2. S_AGND: select AGND Voltage. general, mode VDDA used.
S_AGND [1:0] AGND Voltage VDDA VDDA VDDA VDDA
2.5. Battery Comparator
Mux2
100k
1.33V
LBOUT
SI_LB
S_LB[2:0]
EN_LB
2.5.1. When EN_LB=1, battery comparator enabled. 2.5.2. When SI_LB=0, OPAMP input VDD. Otherwise OPAMP input external (PT1.1). 2.5.3. S_LB [2:0] used select resistance
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
104k 124k 134k 149k 164k 184k Battery Voltage
S_LB [2:0]
2.6. Bandgap Voltage Temperature Sensor
REFO Bandgap Voltage Reference Temperature Sensor
TEMPH Function Network TEMPL EN_BAND
2.6.1. REFO temperature coefficient bandgap voltage reference output. When EN_BAND=1, circuit enabled. output voltage AGND about 1.2V. Typical temperature coefficient 100ppm/°C. 2.6.2. {TEMPH, TEMPL} proportional ambient temperature. They connected input converted digital numbers (typical 530uV±50uV/°C)
2.7. Bias Circuit
Bias Circuit
2.7.1. output voltages Bias Circuit. voltages about RLCD, RLCD RLCD. When EN_LCDB=1, circuit enabled.
VDDA
RLCD V3=RLCD V2=2/3 *RLCD V1=1/3 *RLCD Driver EN_LCDB
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Clock System
Address Name
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Content
M7_CK M6_CK M5_CK M4_CK
25pF
M2_CK S_CHCK [1:0]
10M/1M 25pF
M1_CK S_BEEP
M0_CK S_PCK
32.768kHz/4MHz
1.25 Internal Oscillator Circuit
MUX2(M4_CK)
32.768kHz/4MHz Crystal Oscillator Circuit
3.1. Oscillator State
Input M7_CK Oscillator State Disable Disable Enable Enable Enable Disable Disable Enable Disable Disable
Sleep
M6_CK
External oscillator 32768Hz crystal 1~4MHz crystal/ceramic, shown following Figures. order Mask Code please FS9932L_XXX 32768Hz crystal FS9932H_XXX 1~4MHz crystal/ceramic
25pF 32.768kHz Crystal 25pF 1M~4M Crystal/Ceramic XOUT
XOUT
FS9932L_XXX
FS9932H_XXX
XOUT
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
When using FS9932F_ICE Chip, there sets external pins Oscillator Circuit: XIN1 XOUT1 32768Hz crystal XIN2 XOUT2 1~4MHz crystal/ceramic. unused set, external circuits should removed pins XIN1 XIN2) should connected VDD. When external oscillator disabled then restarted, oscillator need wait period time before start. typical waiting time 32768Hz crystal oscillator about When disabling oscillator, necessary make sure that oscillator disabled during operation clock cycle. M4_CK="0", MCK=CK2; M4_CK="1", MCK=CK3/2.
3.2. Instruction Cycle
M2_CK M1_CK M0_CK Instruction Cycle CK3/8 MCK/4 MCK/8 MCK/12.5 MCK/25
When M2_CK=0, different operation clock cycle from order maintain stable output. applications where resolution more than 13-bits necessary, M2_CK should zero. CPU's operation clock cycle change M0_CK,M1_CK,M2_CK,M4_CK change. Users must make sure that switching made only after oscillator's output stabilized. command should added after switching. MCK,2
3.3. Sample Frequency
M1_CK sample Frequency (ADCF) MCK/50 MCK/25
sampling frequency should between 40kHz 80kHz order better characteristics.
3.4. Beeper Clock
M0_CK S_BEEP Beeper Clock MCK/500 MCK/750 CK3/8
3.5. Voltage Doublers Operation Frequency
M0_CK S_PCK Voltage Doubler's Operation Frequency MCK/50 MCK/200 CK3/32
3.6. Chopper Operation Amplifier Input Control Signal
S_CHCK S_CHCK Chopper Control Signal MCK/1000
17/37 TD0305-2601 Ver.
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
MCK/2000
3.7. Timer Module Input Clock
M5_CK Timer Module input Clock TMCLK MCK/2000 CK3/32
Port
4.1.
Address Name INTF INTE PT1EN PT1PU PT1MR Content
[7:0] PT1EN [7:0] PT1PU [7:0] [1:0] E0IF E0IE
4.1.1. port with pull-up resistor enable control. 4.1.2. input port when PT1EN ="0", output port when PT1EN[N] "1"; system reset "0". 4.1.3. When PT1PU [N]="0", pull-up resistor; When PT1PU[N]="1", pull-up resistor; system reset "0". 4.1.4. used external interrupt source. Interrupt mode controlled [1:0]: "00" negative edge, "01" positive edge, "10"&"11"for interrupt during other time. 4.1.5. Schmitt-trigger input. 4.1.6. PT1.1 channel "AD4", PT1.2 channel "AD5".
PT1PU[7:0] Databus[7:0]
AR==20h Write LOAD
PT1[7:0]
PT1EN[7:0]
READ&AR==20h
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4.2.
Address Name PT2EN PT2PU PT2MR
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Content
[7:6] PT2EN [7:6] PT2PU [7:6] PWDE
4.2.1. port with pull-up resistor enable control. 4.2.2. When PT2EN ="0", input port; When PT2EN[N]= "1", output port. system reset "0". 4.2.3. When PT2EN [7]="1", used buzzer output. BPE="1". 4.2.4. When PWDE="1" PT2EN [6]="1", PT2.6 Output.
PT2PU[7:6] Databus[7:0]
AR==24h Write LOAD
PT2[7:6]
PT2EN[7:6]
READ&AR==24h
Timer
Address Name INTF INTE TMOUT TMCON Content
TRST TMIE TMIF TMOUT [7:0] TMEN
[2:0]
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
TMOUT[7:0] TMEN bits Counter TMCLK Frequency Divider TMCLK/4 Reset
Timer Interrupt Signal
TMRST
5.1. After writing address 0Dh, will send pulse TRST reset 8-bit counter. Then read "1". 5.2. When TMEN=1, 8-bit counter enabled. When TMEN=0, 8-bit counter stops. 5.3. [2:0] selects timer interrupt source. selection codes follows: TMOUT [0], TMOUT [1], TMOUT [2], TMOUT [3], TMOUT [4], TMOUT [5], TMOUT [6], TMOUT [7]. 5.4. TMOUT [7:0] output 8-bit counter. read-only.
(Pulse Density Modulator) Module
Address Name PWDH PWDL PWCON
PDM15 PDM14 PDM13 PDMO= (PDMD[x] PDMx) Example: PDMD=6000h PDMO x=0~15
Content
PDMD [15:8] PDMD [7:0] PDEN
PDCS [2:0]
6.1. PDEN: Enable Module
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
6.2. PDCS: Select Input Frequency
PDCS Pulse Width 1/MCK 2/MCK 4/MCK 8/MCK 16/MCK 32/MCK 64/MCK 128/MCK
Input Multiplexer Pass Filter
Address Name NETA NETB NETD Content
SOHM SINL [1:0] MODE SINH [2:0] [2:0] SVRL SVRH
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
REFO
REFI
AGND
100k
SOHM REFO<1>
MODE MODE
SINH<2:0 AD5<111> TEMPH<110> AGND<101> AGND<100> OP1P<011> VRL<010> VRH<001> FTIN OP1O<000> SFTA<2> SFTA<1:0 AD3<11> AD0<10> FTIN<01> FT2<00> SINL<1:0 AD1<11> TEMPL<01> AD3<10> AGND<00>
REFI<0>
ADEN ADRST <1:0>
SVRH AD0<1> REFI<0>
SVRL AD3<1> AGND<0>
Pre-Filter: input signal sampled ADC. When input signal noise with frequency higher than sampling frequency, noise generates frequency noises through sampling circuit. Hence recommended pass input signal through pass filter, order stable output. FS9932 internal 100K resistor, which construction pass filter through parallel connection with external capacitor between pins FT2. capacitance normally between 10nF 50nF. Please note that larger capacitance cause much time delay input signal switching. SFT<2> decides input signal passes pass filter. SFTA<1:0> decides whether ADC's input through pass filter, direct input, through AD0. Input Multiplexers: positive negative input terminals reference voltages selected analog multiplexers status specified users. ones also SINH<2:0>, SFTA<1:0>. input OP1P terminal SINH multiplexer selected SOP!P<2:0>. When measuring internal temperature, positive terminal should connected TEMPH, negative connected TEMPL. reference voltage fixed around 0.4V. Voltage Source: When MODE=1, used voltage source. voltage selected SOHM REFO REFI voltage. output current less than 500uA.
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Control Register
Address Name INTF INTE ADOH ADOL ADCON NETG
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Content
[15:8] [7:0] ADRST [1:0] ADIF ADIE
[2:0] ADEN
{ADOH,ADOL}
INVRH
8.1. (analog digital converter) contains modulator digital comb filter. When ADRST=1, comb filter will enabled. When ADRST=0, comb filter will reset. ADEN=1 starts modulator. 8.2. output rate selected (N).
Output Rate ADCF/125 ADCF/250 ADCF/500 ADCF/1000 ADCF/2000 ADCF/4000 ADCF/8000 ADCF/8000
8.3. AZ=0 means that ADC's differential inputs (VIH, VIL); means that differential inputs (VIL, VIL). this mode measure offset. 8.4. [1:0] will ADC's input gain follows: 2/3, 1/3.
Application Guide
used FS9932 with fully differential inputs fully differential reference voltage inputs. maximum output ±15625. conversion equation follows: Dout= 15625 (VIH-VIL+Vio) (VRH-VRL+Vro) ADC's positive input voltage, ADC's negative input voltage, ADC's offset input terminals, voltage positive input Reference Voltage, voltage negative input
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Reference Voltage, offset input terminals Reference Voltage. Where VRH-VRL+Vro>0. When (VIH-VIL+Vio) (VRH-VRL+Vro) Dout=15625. When (VIH-VIL+Vio) (VRH-VRL+Vro) Dout=-15625.
9.1. Output Format
read {ADOH,ADOL} ADC's 16-bit output. Note that output complement format, i.e., most significant (MSB) denotes negative number. example, {ADOH,ADOL}=E2F7h, then Dout= (not(E2F7h)+1)= -7433.
9.2. Linear Range.
close saturation when (VIH-VIL+Vio) (VRH-VRL+Vro) close good linearity range ±0.95.
9.3. Output Rate Settling Time
generally over-sampling ADC, i.e., every output results sampling times processed DSP. FS9932 sampling frequency decided M1_CK. ADCM decides send 16-bit output after sampling times, interrupt signal every time changes output. fact, every output includes previous times sampling results. Generally speaking, input, reference voltage, ADG, switched, previous outputs normally stable ones, third output beyond stable.
9.4. ADCOffset
Input Offset drifts with temperature common mode voltage inputs. When drifting slow, Doff= 15625 (Vio) (VRH-VRL+Vro) When measuring, Doff should deducted. relationships Doff with voltage inputs common mode reference voltage shown follows. 9.4.1. (VRH,AGND)=0.4V, VRL=AGND, VIH=VIL=VICM ADG=01
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Doff VICM
Counts -500 -1000
9.4.2.
(VRH,AGND)=0.5~1V, VRL=AGND, VIH=VIL=AGND ADG=01
Doff Reference Voltage 2000 1500 Counts 1000
9.5. Gain
output deducted Doff Gain. Within operation range, changes Gain shown follows. results show that Gain does change changes. suggested values common mode voltages input reference voltage 1V~2V. 9.5.1. Gain VDD: (VRH,VRL)= 1/3(REFO,AGND), (VIH,VIL)= 1/6(REFO,AGND) VRL=VIL=AGND ADG=01 VDD=2.2V~3.6V
Gain 7827 7826 Counts 7825 7824 7823
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
9.5.2. Gain Voltage Inputs Common Mode: (VRH,VRL)=1/3(REFO,AGND), (VIH,VIL)=0.2V, VRL=AGND VICM=1/2(VIH+VIL) ADG=01
Gain VICM 8140 Counts 8120 8100 8080
9.5.3. Gain Voltage Reference Common Mode: (VRH,VRL)=0.4, (VIH,VIL)=1/6(REFO,AGND), VRCM=1/2(VRL+VRH) VIL=AGND ADG=01
Gain VRCM 7420 Counts 7400 7380 7360 7340
9.6. Resolution
resolution mainly decided ADCM(ADC rate) reference voltage, results follows: 9.6.1. (VRH,VRL)=0.4V,(VIH,VIL)=0.2V, VRL=VIL=AGND.
Rolling counts
9.6.2. (VRH,VRL)=VR,(VIH,VIL)=1/2 VRL=VIL=AGND. ADM=101 Rolling counts 0.05
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OPAMP Control Register
Address Name NETH
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Content
SONE OPEN S_CHCK [1:0] SOP1P [2:0]
OP1N
OP1O
SONE
SOP1P<2:0 AD1<111> AGND<110> AD4<101> AD5<100> AD0<011> AD2<010> AD3<001> AGND <000> OP1P
OP1EN
SCHCK[1:0]
10.1. ENOP OPAMP enable control signal. 10.2. When SONE=1, output negative input OPAMP short, OPAMP becomes unit-gain buffer. 10.3. S_CHCK [1:0] "3.6. Chopper Operation Amplifier Input Control Signal". input operation mode follows: +Offset, -Offset, MCK/1000 chopper frequency, MCK/2000 Chopper frequency.
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Noise Operation Amplifier Guide
input noise CMOS OPAMP generally much larger than Bipolar OPAMP. Moreover, flick noise(1/f noise) CMOS killer frequency small signal measurement. need input bias current Bipolar OPAMP causes that some transducers used. general, Bipolar process good highly integrated ICs. FS9932used special CMOS noise circuit design, under normal conditions, input noise controlled under 1uVpp(0.1Hz~1Hz). FS9932 good transducer applications because there need consider input bias current. Most input noise CMOS OPAMP comes from input differential amplification. S_CHCK switch differential amplification: positive Offset Voltage, negative Offset voltage. when using clock pulse switch input differential amplification, that called chopper mode. general, chopper frequency between 1kHz 2KHz. Under chopper mode, input noise peak-to-peak voltage FS9932 less than 0.5uV (0.1Hz~1Hz). equivalent input current less than 100pA generated, effect switching.
11.1. Single Amplifier Application
Measurement small signal usually takes consideration drifting OPAMP offset voltage. Figure below, negative input connected AGND. also possible measure ADC's negative input deduct this value, order correct error caused Amplifier's offset voltage drifting. Because AGND provides current output applications, used negative input measurement point avoid unnecessary voltage error. OPAMP input offset amplified amplifier then inputted ADC. much amplification cause OPAMP output move beyond linear operation range. Hence, under normal conditions, OPAMP amplification should less than times.
300k
OP1N
OP1O
FS9932
AGND
11.2. Differential Amplifier
Measurement differential signal often used bridge sensor applications. shown differential amplifier below, used power input bridge sensor, reference voltage also from after
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
voltage division. When there small change output does change. Connecting negative input adjust zero point bridge sensor. When starting chopper mode, amplification should less than times.
300k
REFI
OP1N
SAD1
Bridge sensor
OP1O
300k
REFI
Driver Output Port
Address Name LCD1 PT5O PT6O LCD6 LCD5 LCD4 LCD3 LCD2 LCDENR Content
SEG1 [3:0] SEG0 [3:0] [1:0] [1:0] SEG11 [3:0] SEG9 [3:0] SEG7 [3:0] SEG5 [3:0] SEG3 [3:0] LCDCKS [1:0] LCDEN SEG10 [3:0] SEG8 [3:0] SEG6 [3:0] SEG4 [3:0] SEG2 [3:0] S_LCDO [1:0]
12.1. Common Driver Waveform
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
RLCD RLCD
COM1
RLCD RLCD RLCD
COM2
RLCD RLCD RLCD
COM3
RLCD RLCD RLCD
COM4
RLCD
Frame Frequency
Common Driver Waveform
12.2. LCDEN starts clock. LCD1~LCD6 display data area. 12.3. LCDCKS [1:0] select frame frequency. input frequency, "3.7. Module Input Clock"
LCDCKS [1:0]
frame frequency
Input Frequency/8 Input Frequency/16 Input Frequency/32 Input Frequency/64
12.4. S_LCDO [1:0] select segment output general output port.
S_LCDO [0]=1 S_LCDO [1]=1 General Output Port SEG8~SEG9 SEG10~SEG11
Reset
FS9932 three reset signals they external pin, voltage reset(LVR), watchdog time reset. When resetting, CPU's Program Counter (PC) reset After reset, starts working. following table shows CPU's internal register status after reset.
Address Name FSR0 FSR1 STATUS WORK INTF INTE External Reset
uuuuuuuu uuuuuuuu 00000000 uuuuuuuu u0000000 u0000000 00000000 uuuu0000
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Reset
uuuuuuuu uuuuuuuu uuuu1uuu uuuuuuuu u0000000 u0000000 00000000 uuuu0000
TD0305-2601 Ver.
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TMOUT TMCON ADOH ADOL ADCON PT1EN PT1PU PT1MR PT2EN PT2PU PT2MR NETA NETB NETD NETF NETG NETH NETJ NETK PWDH PWDL PWCON LCD1 PT5O PT6O LCD6 LCD5 LCD4 LCD3 LCD2 LCDENR
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
00000000 u0000000 00000000 00000000 uuuu0000 uuuuuuuu 00000000 00000000 00000000 uuuuuuuu 00uuuuuu 00uuuuuu 00uuuuuu 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 00000000 00000000 u0000000 00000000 00000000 uuuu0000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu 00000000
Note: means unknown unchanged
13.1.
External
When Low, Reset status. external circuit shown follows. When changes from "low" "high", Reset signal will generated bring back normal operation condition.
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
100k 0.1uF Operation
Reset Circuit
Reset Timing
13.2. voltage reset
avoid putting abnormal power status that makes unable reset causes operating abnormally, FS9932 contains voltage reset circuit. When FS9932 less than LVR, enters reset status.
13.3.
Watchdog time reset
Content
[2:0]
Address Name STATUS TMCON
WDTEN
Watch Timer Oscillator
WDTA[7:0]
bits Counter1
Multiplex
bits Counter2
WDTOUT
WDTS[2:0] CLRWDT
When starting watch timer, necessary connect WDTEN VDD. Otherwise, connect VSS. When using CLRWDT instruction, Counter reset. clock input Watch timer comes from independent oscillator. Watch time selected WTS, shown following Table. When Watch time happens, enters reset status
Halt Sleep Modes
14.1. Halt Mode After executes Halt command, Program Counter(PC) Stops counting until interrupt command issued. avoid program errors caused Interrupt Return, suggested command after Halt guarantee program's normal execution. HALT
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
14.2. Sleep Mode After executes Sleep command, oscillators stop working until external interrupt command issued reset. avoid program errors caused Interrupt Return, suggested command after Sleep guarantee program's normal execution. Sleep make sure that consumes minimum power Sleep mode, necessary open power blocks analog circuits before issuing Sleep command, make sure Ports voltage levels. There exist parasitic diodes between VDDA analog input ports (see below Figure) When VDDA turned VDDA low, necessary keep AD0~AD3 Floating voltage, AD4/PT1.1, AD5/PT1.2 Output Low.
AD4/PT1.1 AD5/PT1.2 VDDA
recommended that users execute following program before issuing Sleep command: CLRF NETA CLRF NETB CLRF NETD CLRF NETF CLRF NETG CLRF NETH CLRF NETJ CLRF PT2PU MOVLW 0FFh MOVWF PT2EN CLRF Output MOVLW MOVWF PT1PU MOVLW 0FEh MOVWF PT1EN CLRF PT1[7:1] Output Low, PT1[0] Input /Pull CLRF INTF MOVLW 081h External Interrupt Enable MOVWF INTE SLEEP
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Application Circuit
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 COM4 SEG7 SEG10/PO6<0> SEG11/PO6<1> SEG8/PO5<0> SEG9/PO5<1>
COM1
COM2
COM3
AGND
10nF
0.1uF
VDDA
10uF
VSSP
10uF
FS9932 LQFP
27nF
REFI
VDDP
REFO
OP1O
300k
OP1N
XOUT
PT2<6>/PDM
PT1<2>/AD5
PT1<1>/AD4
PT1<0>/INT
PT2<7>/BZ WDTEN
PT1<7>
PT1<6>
PT1<5>
PT1<4>
PT1<3>
100k 0.1uF
REFI
SAD1
Bridge sensor
300k
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Package Outline Dimensions
LQFP64: plastic profile quad flat package; leads; body x1.4
index
(A3)
detail
scale
DIMENSIONS origlinal dimensions)
UNIT max. 1.60 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09
0.75 0.45
10.1
10.1
12.15 12.15 11.85 11.85
0.12 0.075
1.45 1.05
1.45 1.05
Note: 1.Plastic metal protrusions 0.25 maximum side included.
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TD0305-2601
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FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Diagram Layout
(0,0) ning 90um Chip 2.000mm 2.042mm
hould conne
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Coordinate
FS9932
8-Bit with embedded program memory, 6-ch 14-Bit converter, noise amplifier, driver
Name [mm] 0.072 0.072 WDTEN 0.072 PT2<7> 0.072 PT2<6> 0.072 PT1<7> 0.072 PT1<6> 0.072 PT1<5> 0.072 PT1<4> 0.072 PT1<3> 0.072 PT1<2> 0.072 PT1<1> 0.072 PT1<0> 0.072 0.117 OP1N 0.241 OP1O 0.361 REFO 0.481 REFI 0.601 0.721 0.841 0.961 1.081 1.201 1.321 1.441 AGND 1.561
[mm] 1.910 1.790 1.670 1.458 1.338 1.218 1.098 0.978 0.858 0.738 0.618 0.497 0.377 0.075 0.075 0.075 0.075 0.075 0.075 0.075 0.075 0.075 0.075 0.075 0.075 0.075
Name SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM4 COM3 COM2 COM1 VDDA VSSP VDDP XOUT
[mm] 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.927 1.575 1.456 1.336 1.216 1.096 0.976 0.856 0.736 0.616 0.491
[mm] 0.078 0.198 0.318 0.438 0.558 0.678 0.798 0.918 1.038 1.158 1.278 1.398 1.518 1.638 1.758 1.878 1.970 1.970 1.970 1.970 1.970 1.970 1.970 1.970 1.970 1.970
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