8-Bit with embedded program memory, 8-ch 14-Bit converter, noise ampli
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
FS9912 Datasheet [V3.0]
DESCRIPTION FEATURE
FS9912 BLOCK DIAGRAM PACKAGE ASSIGNMENT DESCRIPTION. ELECTRONIC CHARACTERISTIC FUNCTION DESCRIPTION. CORE. PORT PORT BITS TIMER DUAL 24-BIT PROGRAMMABLE COUNTER POWER SYSTEM MEASUREMENT PART BLOCK DIAGRAM. ANALOG MULTIPLEX NOISE OPAMP DRIVER WATCH TIMER SPECIAL REGISTER EXTERNAL RESET(POWER RESET) RESET STATE APPLICATION NOTES
PACKAGE OUTLINE
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Description
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Ver.
FS9912 high performance, cost CMOS 8-bit single chip microcontroller with embedded 4kx16 bits ROM, 8-channel 14-bit fully differential input analog digital converter, noise amplifier, driver. FS9912 best suited applications such cost, high performance digital thermometer, thermometer, scale, baromemter, hygrometer.
Feature
iii. 8-bit microcontroller, single word instructions Embedded program memory, 128-byte data memory Voltage operation ranges from 2.4V 3.6V, 4MHz crystal oscillator Operation current less than 2mA, sleep mode current about (LVR disable). voltage reset(LVR) function mask option. FS9912R_xxx enable, FS9912_XXX disable. 8-level deep hardware stacks Interrupt sources (external: internal: 8-channel 14-bit (±400mV input range, ±2LSB linearity error) with 40Hz output rate Embedded charge pumper voltage regulator regulated output) Embedded bandgap voltage reference (typical 1.2V±50mV, 100ppm/°C) noise (1uV without chopper, 0.5uV with chopper, 0.1Hz~1Hz) OPAMPs with chopper controller 16-bit bidirectional port buzzer output Dual 24-bit programmable timers driver Vpp) Watchdog timer Package: dice form, 64-pin LQFP.
vii. viii.
xii. xiii. xiv. xvi.
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
FS9912 Block Diagram
Driver
Program Memory
Byte Data Memory
Charge Pumper, Voltage Reglator, Bias Generator Bandgap Reference
8-bit Core
Digital In/Out Port Exteranl Interrupt Input
Digital In/out Port Buzzer Output Analog Input Multiplexer 8-bit Time Base Counter
Noise OPAMP Dual 24-bits Event Counter
Analog Digital Converter
Watchdog Timer
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Package Assignment
SEG9 SEG8 SEG7 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 COM1 COM2 SEG10 COM3 COM4 SEG6 SEG5
OP1N
OP1O
SEG4
REFO
SEG3
REFI
SEG2
SEG1
RLCD
VDDA
FS9912 LQFP
WDTEN
XOUT
AGND
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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
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P2.1
P2.2
P2.3
P2.4
P2.5
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P2.6
P2.7
Ver.
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Diagram Layout
(0,0)
opening 90um Chip size 2.112mm 2.740mm
Substrate should connected
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Coordinate
Name P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 XOUT WDTEN VDDA RLCD SEG1 SEG2 SEG3 SEG4 SEG5
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
[mm] 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 2.035 1.885 1.745 1.620 1.495 1.370 1.245 1.120 0.995 0.870 0.745 0.620 0.495 0.370 0.230 0.082
[mm] 0.385 0.525 0.665 0.790 0.915 1.040 1.165 1.290 1.415 1.540 1.665 1.790 1.915 2.040 2.180 2.320 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663 2.663
Name SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 COM4 COM3 COM2 COM1 OP1N OP1O REFO REFI AGND
[mm] 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.225 0.365 0.490 0.615 0.740 0.865 0.990 1.115 1.240 1.365 1.490 1.615 1.740 1.880 2.035
[mm] 2.320 2.180 2.040 1.915 1.790 1.665 1.540 1.415 1.290 1.165 1.040 0.915 0.790 0.665 0.525 0.385 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077 0.077
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Description
Name In/Out Description Positive Power Supply Negative Power Supply AGND Analog Ground Charge Pump Capacitor Negative Connection Charge Pump Capacitor Positive Connection Charge Pump Voltage VDDA Analog Power Output RLCD Bias Voltage Input 4MHz Oscillator Input XOUT 4MHz Oscillator Output P1.0~P1.7 Port P2.0~P2.7 9~16 Port SEG1~SEG16 28~43 Segment Driver Output COM1~COM4 47~44 Common Driver Output AD0~AD7 62~55 Analog Input Channel REFO Bandgap Reference Output REFI Reference Voltage Input OP1N OPAMP Negative Input OP1O OPAMP Output FT1, 54,53 Pre-Filter Capacitor Connection Analog Circuit Bias Current Input Reset Testing Mode WDTEN Watchdog Timer Enable Control
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Electronic Characteristic
Absolute Maximum Ratings
Parameter Supply Voltage Ground Potential Applied Input/Output Voltage Ambient Operating Temperature Storage Temperature Soldering Temperature, Time Rating -0.3 -0.3 VDD+0.3 +150 260°C, Unit
Characteristic (Unless otherwise specified VDD=3VTa=25)
Symbol IPO1 IPO2 AGND VDDA VREF VCREF TCREF VLBAT FLCD VLCD Parameter Recommend Operation Power Voltage Supply Current Power-off Supply Current Power-off Supply Current Digital Input High Voltage Digital Input Voltage Pull Current Vin=0 High Level Output Current VOH=0.9xVDD High Level Output Current VOL=0.1xVDD Analog Ground Voltage Analog Power Build Reference Voltage AGND Build Reference Voltage VDD=2.4~3.6 Supply Voltage Coefficient Build Reference Voltage Ta=0~50 Temperature Coefficient Battery Detector Voltage Frame Frequency Pk-Pk Driver Voltage Test Condition Units +2000 ppm/V ppm/
CPU, Power Off, disable Power Off, enable VDD-0.
VDD/2 1.20 -2000
Characteristic (Unless otherwise specified VDD=3VTa=25)
Symbol VAIN VRFIN Parameter Test Condition Differential Input Range Reference Input Range Resolution Linearity Error VRFIN=0.44V Input Offset Voltage VRFIN=0.44V
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AGND0.4 0.25 -0.1
Units AGND+ Counts ±15625 +0.1
TD00308-2901
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Ver.
With Zero Cancellation
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver VAIN=0
OPAMP Characteristic (Unless otherwise specified VDD=3VTa=25)
Symbol Parameter Input Offset Input Offset Voltage with Zero Cancellation Rs<100 Test Condition Units
Input Offset Voltage with Chopper Input Offset Drift with Zero Cancellation Input Reference Noise Input Reference Noise with Chopper Input Bias Current Input Bias Current with Chopper Input Common Mode Range Output Voltage Range Chopper Clock Frequency Capacitor Load
Rs<100 -20<TA<+50 Rs=100, 0.1Hz~1Hz Rs=100, 0.1Hz~1Hz
µVpp µVpp
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Thermometer Application Circuit
8888
SEG9 SEG8 SEG7 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 COM1 REFO OP1O OP1N COM2 SEG10 COM3 COM4 SEG6 SEG5
SEG4 SEG3
REFI
SEG2
SEG1
Rref 700k
RLCD
VDDA
Thermister
FS9912 LQFP
2.2n
OP1O VIN+
Analog Digital Converter
VINVR+ VRAGND
2.2n
2.4V~3.6V
WDTEN
Thermopile
REFI
XOUT
AGND
4MHz
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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
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P2.3
P2.4
P2.5
P2.6
P2.7
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Scale (Load Cell) Application Circuit
8888
SEG9 SEG8 SEG7 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 COM1 OP1N COM2 SEG10 COM3 COM4 SEG6 SEG5
OP1O
SEG4
REFO
SEG3
REFI REFI SEG2
REFI
SEG1
VDDA
RLCD
VDDA
Load Cell
FS9912 LQFP
OP1O VIN+
3.3V Regulator
2.2n 3.6V
Analog Digital Converter
VINVR+
WDTEN
REFI
XOUT
AGND
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P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6 VDDA
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Converter Circuit Reference
AGND
converter
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Function Description
Core
Address Name Content
IND0 IND1 FSR0 FSR1 STATUS WORK INTF INTE
contents FSR0 address data memory contents FSR1 address data memory Indirect data memory, address point Indirect data memory, address point WORK register TMIF PCIF ADIF E1IF E0IF TMIE PCIE ADIE E1IE E0IE
IND0, IND1: indirect addressing mode address FSR0, FSR1: indirect addressing mode point
iii. Power Down Flag. Cleared writing power-on reset. sleep instruction Watch Time Flag. Cleared writing power-on reset. Watch Time Carry Flag
Zero Flag vii. E0IF, E0IE: PT1.0 external interrupt flag enable. viii. E1IF, E1IE: PT1.1 external interrupt flag enable. ADIF, ADIE: Analog digital converter interrupt flag enable. PCIF, PCIE: Program counter interrupt flag enable.
TMIF, TMIE: 8-bit Timer interrupt flag enable. xii. GIE: Global interrupt enable.
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Port
Address Name
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Content
020H 021H 022H 023H
PT1EN PT1PU PT1MR
PT1PU[7:0] Databus[7:0]
[7:0] PT1EN [7:0] PT1PU [7:0] E1M1 E1M0 E0M1 E0M0
AR==20h Write LOAD
PT1[7:0]
PT1EN[7:0]
READ&AR==20h
port with pull-up resistor enable control. PT1EN input port, output port, system reset iii. PT1PU [N]=0: without pull-up resistor, with pull-up resistor, system reset external interrupt sources. Interrupt mode controlled E1M, E0M. negative edge, positive edge, 10&11: interrupt when change. Schmitt-trigger input
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Port
Address Name
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Content
024H 025H 026H 027H
PT2EN PT2PU PT2MR
Databus[7:0]
BPE2
BPE1
PT2PU[7:0]
[7:0] PT2EN [7:0] PT2PU [7:0] OPC1 OPC0
PMPS
AR==24h Write LOAD
PT2[7:0]
PT2EN[7:0]
READ&AR==24h
iii.
ports with pull-up resistor enable control. PT2EN input port, output port, system reset BPE2 PT2EN [7]=1: buzzer output. BPE1=1 PT2EN [6]=1: inverter buzzer output. BPS=1: buzzer frequency=4kHz, BPS=0 buzzer frequency=2.7kHz.
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bits Timer
Address Name
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Content
00CH 00DH
TMOUT TMOUT [7:0] TMCON TRST WTS2 WTS1 WTS0 TMEN INS2
INS1
INS0
TMEN
TMOUT[7:0] bits Counter
Timer Interrupt Signal
128Hz Input
Reset
TRST
Write address 0Dh, will send pulse TRST reset 8-bit counter. Then read "1". TMEN=1, 8-bit counter will enabled. TMEN=0, 8-bit counter will stop. [2:0] selects timer interrupt source. selection codes follows, 000: TMOUT [0], TMOUT [1], 010: TMOUT [2], 011: TMOUT [3], 100: TMOUT [4], 101: TMOUT [5], 110: TMOUT [6], 111: TMOUT [7]. TMOUT [7:0] output 8-bit counter. read-only.
iii.
Dual 24-bit Programmable Counter
Address Name Content
014H 015H 016H 017H 018H 019H 01AH
CTAH CTAM CTAL CTBH CTBM CTBL FQCON
[23:16] [15:8] [7:0] [23:16] [15:8] [7:0] LOAD FCM1 FCM0 FCRST
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
FCRST FCM=10 Out=1 else Out=~Stop
Load
Load P1.2
STOP
Start
CTA=FFFFFFh
FCMODE=10 Out=CTA Overflow else Out=Stop
Program Counter Interrupt Signal
FCRST
Start
DCK(1MHz)
Databus[7:0] Enable CTA[7:0]
8-bit counter
reset
Multiplex
Multiplex
16-bit Counter with Load
CTA[23:8]
FCRST
GT[2:0]
FCM=10 Out=P1.2 else FCM=01&Start=1 Out=P1.2 else FCM=00&Start=1 Out=1 else Out=0 FCM=00 Out=P1.2 else Out=
Write
Enable CTB[7:0] CTB[7]
Load
Databus[7:0]
8-bit counter
reset
Multiplex
16-bit Counter with Load
CTB[23:8]
FCRST
Write
Under modes FCM=00 Load=1 load data into [23:8] simultaneously When Load=0 FCRST=1, will start counting after first positive edge signal from input PT1.2. counters will stop counting until overflows after first positive edge signal from input PT1.2, then system will send interrupt signal. Therefore, count cycles PT1.2 input signal calculate high-resolution frequency duty cycle frequency input signal following calculation approach. Under mode FSM=10, start counting when FCRST=1. counters will stop counting until overflows, then system will send interrupt signal. calculating flows methods described follows: Frequency Measurement Mode: FCM=00 iii. Load=1, FCRST=0 Write [23:8] initial value CTAI. [2:0] select length counter CTA. GT=000 sets [23:8] 16-bit counter clock input; [23:0] 24-bit counter. GT=111 sets [23:8] 16-bit counter clock input; {CTA [23:8], CTA[0]} 17-bit counter. Gate Time (1000000h-CTAI 256) GT=000 LOAD=0, FCRST=1, P1.2 frequency starts measuring. Wait till positive edge P1.2, then Start=1 start counting.
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vii. viii.
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Wait till overflows next positive edge P1.2, then Start=0 stop counting. When receives interrupt signal, will read CTB. Here reference clock counter, input clock counter Frequency P1.2 is1MHz CTB/(CTA+CTAI). next measurement.
Duty Cycle Measurement Mode: FCM=01 iii. Load=1, FCRST=0 Write [23:8] initial value CTAI. [2:0] select length counter CTA. GT=000 sets [23:8] 16-bit counter clock input; [23:0] 24-bit counter. GT=111 sets [23:8] 16-bit counter clock input; {CTA [23:8], [0]} 17-bit counter. Gate Time (1000000h-CTAI 256) GT=000 LOAD=0, FCRST=1, P1.2 frequency starts measuring. Wait till positive edge P1.2, then Start=1 start counting. Wait till overflows next positive edge P1.2, then Start=0 stop counting. When receives interrupt signal, will read CTB. Here reference clock counter, counts when P1.2=1. duty cycle P1.2 100% CTB/(CTA+CTAI). next measurement.
vii. viii.
Timer Mode: FCM=10 iii. Load=1, FCRST=0 Write [23:8] initial value CTAI. [2:0] select length counter CTA. GT=000 sets [23:8] 16-bit counter clock input; [23:0] 24-bit counter. GT=111 sets [23:8] 16-bit counter clock input; {CTA [23:8], [0]} 17-bit counter. Gate Time (1000000h-CTAI 256) GT=000 When overflows, then send interrupt signal CPU. receives interrupt signal, then
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Power System
Address Name
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Content LBCEN BNDEN LCDEN
100k
02CH 02DH
NETD PUMPEN
REGEN GNDEN BIASEN
VDDA
RLCD
REFO
Analog Common Generator Voltage Doubler REGEN PUMPEN Pump Clock LCDEN VC3,VC2,VC1 Driver) Voltage Regulator Bias
Bandgap Voltage Reference
Battery Compararor
BNDEN
LBCEN
AGND
GNDEN
10nF 100k
Bias Circuit
BIASEN Bias(to Analog Circuit)
BIASEN=1 will start bias circuit analog circuit. When power reset, BIASEN GNDEN=1 will start internal analog common generator circuit, AGND voltage about (vdd, vss)/2.
iii. PUMPEN=1 will start voltage doubler circuit, voltage about 2VDD. PMPS (PT2MR [0]) will voltage doubler operation frequency: 2.7kHz,
10kHz.
REGEN=1 will start internal voltage regulator. VDDA voltage about
LCDEN=1 will start driver bias circuit. bias voltages RLCD, 2/3RLCD,
1/3RLCD, respectively.
vii. BNDEN=1 will start internal bandgap voltage reference. output voltage (REFO,
AGND) about 1.2V.
viii. LBCEN=1 will start battery check comparator. comparator inputs
REFO respectively, battery check voltage about 2.4V.
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Measurement Part Block Diagram
AGND REFI AGND ENOP ADINH ADO[15:0] SONE=1 SONE=0 OP1N OP1O
SOP1P=111 SOP1P=110 SOP1P=101 SOP1P=100 SOP1P=011 SOP1P=010 OP1P
Analog Digital Converter
ADINL ADCGB[1:0] ADEN ADRST
SOP1P=001 SOP1P=000
SINH=111 SINH=110 SINH=101 SFTA=1 FTIN SFT=00 SFT=01 SFT=10 SFT=11 SINL=11 SINL=10 SINL=01 SINL=00 AGND REFI SVRH=1 SVRH=0 SVRL=1 SVRL=0 AGND
OP1P OP1O
SINH=100 SINH=011 SINH=010 SINH=001 SINH=000
Address Name Content
010H ADOH [15:8] 011H ADOL [7:0] 013H ADCON ADRST 02BH NETC ADG1 ADG0 ADEN (analog digital converter) contains modulator digital comb filter. When
ADRST=1, comb filter will enabled. When ADRST=0, comb filter will reset. ADEN=1 starts modulator.
output. maximum value 3D09h minimum C2F7h (-3D09h).
FFFF means (-0001).
iii. output rate 40Hz. When output data updated, interrupt signal
sent CPU. ADIE=1, then ADIF
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FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
AZ=0 means that differential inputs (INH,INL); means that
differential inputs (INL,INL). this mode measure offset.
ADCGB [1:0] will input gain follows, 2/3, 1/3.
Analog Multiplex
Address 029H 02AH Name NETA NETB SINL1 SVRH SINL0 SVRL SINH2 Content SINH1 ENOP SINH0 SONE SOP1P2 SOP1P1 SOP1P0 SFTA SFT1 SFT0
OP1P: Positive Input SOP1O
Select
AGND
FTIN: Pass Filter Input SINH
Select
OP1O
OP1P
ADINL: Negative Input SINL
Select
AGND
ADINH: Filter Output, Positive Input [1:0]
Select
FTIN
VRH: Reference Voltage Positive Input SVRH
Select
REFI
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Ver.
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
VRL: Reference Voltage Negative Input SVRL
Select
AGND
External Filter Control: SFTA=0: FTIN open. SFTA=1: FTIN short.
Noise OPAMP
Address Name Content
027H 02AH
PT2MR NETB
BPE2, SVRH
BPE1 SVRL
ENOP
OPC1 SONE
OPC0 SFTA
SFT1
PMPS SFT0
ENOP OPAMP enable control signal SONE=1 output negative input OPAMP short OPAMP unit gain buffer. iii. input operation mode follows, +Offset, -Offset, 2KHz chopper frequency, 1KHz Chopper frequency.
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Driver 030H 031H 032H 033H 034H 035H 036H 037H 038H
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
LCD1 LCD2 LCD3 LCD4 LCD5 LCD6 LCD7 LCD8 LCDEN
SEG1 [3:0], SEG2 [3:0] SEG3 [3:0], SEG4 [3:0] SEG5 [3:0], SEG6 [3:0] SEG7 [3:0], SEG8 [3:0] SEG9 [3:0], SEG10 [3:0] SEG11 [3:0], SEG12 [3:0] SEG13 [3:0], SEG14 [3:0] SEG15 [3:0], SEG16 [3:0] LCDEN
Common Driver Waveform
RLCD RLCD
COM1
RLCD RLCD RLCD
COM2
RLCD RLCD RLCD
COM3
RLCD RLCD RLCD
COM4
RLCD
32Hz
Common Driver Waveform
iii.
LCDEN will start clock. LCD1~LCD8 display data area.
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Watch timer
Address Name
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Content
00DH
STATUS TMCON TRST, WTS2 WTS1 WTS0 TMEN INS2 INS1 INS0
WDTEN
Watch Timer Oscillator
WDTA[7:0]
bits Counter1
Multiplex
bits Counter2
WDTOUT
WDTS[2:0] CLRWDT
WDTEN external input pin. connected then starts watchdog timer oscillator. floated connected VSS, watchdog timer function will disabled. When Counter overflows, will send WDTOUT reset flag. iii. CLRWDT instruction will reset Counter [2:0] selects Counter code selections follows, 000: WDTA [0], 001: WDTA [1], 010: WDTA [2], 011: WDTA [3], 100: WDTA [4], 101: WDTA [5], 110: WDTA [6], 111: WDTA [7].
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TD00308-2901
Ver.
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Special Register External Reset(Power Reset) Reset State
Register Name Address External reset reset Register Name Address External reset reset Register Name Address External reset reset Register Name Address External reset reset Register Name Address External reset reset Register Name Address External reset reset Register Name FSR0 uuuuuuuu uuuuuuuu 00000000 uuuuuuuu PT2PU 00000000 uuuuuuuu NETC 00000000 00000000 CTAH 014h 00000000 00000000 FQCON 00000000 00000000 LCD6 FSR1 uuuuuuuu uuuuuuuu PT1EN 00000000 uuuuuuuu PT2MR 00000000 uuuuuuuu NETD 00000000 00000000 CTAM 015h 00000000 00000000 LCD1 uuuuuuuu uuuuuuuu LCD7 STATUS 00000000 uuuu1uuu PT1PU 00000000 uuuu1uuu TMOUT 00000000 00000000 00000000 00000000 CTAL 016h 00000000 00000000 LCD2 uuuuuuuu uuuuuuuu LCD8 uuuuuuuu uuuuuuuu WORK uuuuuuuu uuuuuuuu PT1MR 00000000 uuuuuuuu TMCON 10000000 10000000 ADOH 00000000 00000000 CTBH 017h 00000000 00000000 LCD3 uuuuuuuu uuuuuuuu LCDEN uuuuuuuu uuuuuuuu INTF 00000000 00000000 00000000 uuuuuuuu NETA 00000000 00000000 ADOL 00000000 00000000 CTBM 018h 00000000 00000000 LCD4 uuuuuuuu uuuuuuuu INTE 00000000 00000000 PT2EN 00000000 uuuuuuuu NETB 00000000 00000000 ADCON 00000000 00000000 CTBL 019h 00000000 00000000 LCD5 uuuuuuuu uuuuuuuu
Address External reset uuuuuuuu uuuuuuuu reset uuuuuuuu uuuuuuuu mean unknown unchanged
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TD00308-2901
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Application Notes
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
Instruction (Reference Document:"FS991x_CPU")
INSTRUCTION OPERATION CYLCE FLAG
CLRF ADDWF INCF INCFSZ DECF DECFSZ SUBWF COMF MOVWF MOVFW ADDWFC ANDWF IORWF XORWF SUBWFC ADDLW SUBLW ANDLW IORLW XORLW MOVLW RETLW CALL GOTO RETFIE RETURN HALT SLEEP CLRWDT ADDPCW BTFSC
operation d=f+W d=f+1 d=f+1 skip d=f-1 d=f-1 skip d=f-W d=~f d=f+W+C d=f&W d=f|W d=f^W C,d[7:0]=f[7:0],C d=f-W-C d[7:0],c=C,f[7:0] W=k+W W=k-W W=k&W W=k|W W=k^W RETURN push PC+1 GOTO PC=k GIE=1 stop clock stop Clear watch timer PC=PC+1+{6{W[7],W[6:0]} f[b]=0 f[b]=1 skip f[b]=0
26/28
None None None None None None None None None None None None None None None None None
TD00308-2901
Fortune Semiconductor +886-2-2809-4742 http://www.fsc.com.tw FAX: +886-2-2809-4874
Ver.
BTFSS
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
skip f[b]=1
None
memory address FFh) work register literal field constant data label destination select store result d=1: store result memory address select(0~7) M(f): content memory address program counter
HALT SLEEP Commands Please make sure interrupt flags cleared before running SLEEP; "NOP" command must follow HALT SLEEP commands. Example: MAIN: HALT GOTO MAIN MAIN_SLEEP: CLRF INTF SLEEP GOTO SYSINI VDDA Regulator VDDA Regulator uses Bias Circuit bias current, while Bias Circuit uses VDDA power. According test far, when VDD<2.7V, easy Start problem cause VDDA unable start strongly recommend customer doing following setup when start VDDA Regulator. This setup make VDDA have Diode Connection start VDDA Regulator Example: MOVLW 10001111B MOVWF NETD MOVLW 00100000B MOVWF NETA MOVLW 00000101B MOVWF NETB CALL DELAY10ms Customer must know FS9912_ICE test operating current chip, test actually operating current chip sleep current corresponding custom specification. Reference Document: "FS9912_ICE Manual_V2.1" page5.
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TD00308-2901
Ver.
Package Outline
FS9912 Preliminary
8-Bit with embedded program memory, 8-ch 14-Bit converter, noise amplifier, driver
LQFP64: plastic profile quad flat package; leads; body x1.4
index
(A3)
detail
scale
DIMENSIONS origlinal dimensions)
UNIT max. 1.60 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09
0.75 0.45
10.1
10.1
12.15 12.15 11.85 11.85
0.12 0.075
1.45 1.05
1.45 1.05
Note: 1.Plastic metal protrusions 0.25 maximum side included.
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TD00308-2901
Ver.
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