WM8400 Wolfson AudioPlusHi-Fi Audio CODEC Power Management Unit M
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WM8400 highly integrated audio CODEC power management unit which provides cost-effective companion solution mobile multimedia applications. Stereo 24-bit sigma-delta ADCs DACs provide hi-fi quality audio recording playback, with flexible digital audio interface supporting most commonly-used data formats clocking schemes. integrated low-power FLL, alternative interface support provide additional flexibility. ultra-low power audio CODEC complemented with powerful speaker driver, which operate class modes. leakage, high PSRR pop/click suppression enable direct battery connection speaker supply. Multiple microphone line inputs (mono, stereo, single-ended differential) supported. programmable high-pass filter provided remove frequency noise from input signal. Four headphone drivers support fully differential headset drive, providing excellent crosstalk performance bass response, maximising stereo effects, allowing removal large expensive headphone capacitors. WM8400 incorporates programmable DC-DC stepdown (Buck) converters four low-dropout (LDO) regulators. startup sequence default voltages DC-DC converters LDOs selectable; regulators software programmable. DC-DCs, LDO1 LDO2 intended power sub-system, whilst remaining LDOs specifically designed power on-chip audio CODEC. WM8400 supplied 6x6mm 105-ball package, ideal portable systems. WM8400 forms part Wolfson AudioPlusseries audio power management solutions.
WM8400
Wolfson AudioPlusHi-Fi Audio CODEC Power Management Unit Mobile Multimedia
FEATURES
93dB (`A' weighted), -84dB 48kHz, 3.0V 93dB (`A' weighted), -82dB 44.1kHz, 3.0V Microphone interface four differential microphones) Speaker driver into speaker <0.1% 80dB PSRR 217Hz <1uA leakage with direct battery connection Software-selectable class mode Filterless connection supported Pop/Click suppression Headphone speaker drivers 40mW output power into 3.3V Fully differential capless modes supported Pop/Click suppression Mono stereo differential line outputs On-chip provides flexible clocking scheme Sample rates: 11.025, 22.05, 44.1, 48kHz Powerful GPIO functions software-programmable DC-DC buck converters software-programmable regulators 250mA) selectable start-up sequence default voltages Ultra-low power consumption analogue voice call 13mW playback headphones 105-ball 6x6mm package
APPLICATIONS
Multimedia feature-rich mobile handsets PDAs Co-processor companion multimedia processors Digital Photo Frames
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Copyright ©2009 Wolfson Microelectronics
WM8400 BLOCK DIAGRAM
Pre-Production
LDO1VDD LDO1VSEL LDO1OUT
LDO2VDD LDO2VSEL LDO2OUT
CORE
DC1VDD DC1FB DC1LX DC1VSEL DC1GND PSEQ1 PSEQ2 PSEQ3 PSEQ4 LINE
DC2VDD DC2FB DC2LX DC2VSEL DC2GND
MEMORY PERIPH.
LDO3VDD
CODEC SUPPLIES
LDO4VDD LDO3OUT LDO4OUT DCVDD HPVDD AVDD
I2CVDD
Codec core Codec core
HOST INTERFACES
DC1EN DC2EN LDO1EN LDO2EN NPDN HSLEEP MSLEEP NIRQ PWRGOOD HBVDD MBVDD MCLK FLLVDD
BUCK DCDC-1 POWER CONTROL STARTUP SEQUENCER
BUCK DCDC-2
LDO-1
LDO-2
LDO-3
LDO-4
Interface
MODE SCLK SDIN NCSADDR VINT
CONTROL INTERFACE
Codec core
INTERNAL REGULATOR UVLO
THERMAL SHUTDOWN
RESET GENERATOR
RSTTRIG CDELAY NRST
IREF CLOCK GENERATOR
Codec core Class driver
RIREF I2S2VDD
WM8400
GPIOs INTERFACE
PRIMARY AUDIO INTERFACE
I2S1VDD BCLK
ADCLRC/GPIO1 ADCDAT DACLRC DACDAT
DIGITAL AUDIO INTERFACE
GPIO2/MCLK2 GPIO3/BCLK2 GPIO4/DACLRC2 GPIO5/DACDAT2 GPIO6/ADCLRCB
SECONDARY AUDIO INTERFACE
(Rx)
LIN4/RXN RIN4/RXP LIN3/GPI7 LIN2 OUT3 OUT4 ROUT LIN1 STEREO MICROPHONE INTERFACE INPUT MIXERS RIN1
DIGITAL FILTERS HI-FI VOICE HIGH PASS FILTER VOLUME DIGITAL FILTERS DIGITAL SIDETONE VOLUME VOLUME
LOUT
SPEAKER
MICROPHONES RADIO LINE-IN
OUTPUT MIXERS
HEADPHONE DRIVERS
HPGND
HEADSET
SPKP SPKN
CLASS D/AB SPEAKER DRIVER
SPKVDD SPKGND
LOUDSPEAKER
(Tx)
RIN2 RIN3/GPI8
Current Detect RECORD
LINE DRIVERS
MICBIAS VMID
LOUDSPEAKER
AGND
April 2009,
Pre-Production
WM8400 TABLE CONTENTS
DESCRIPTION FEATURES.1 APPLICATIONS BLOCK DIAGRAM TABLE CONTENTS CONFIGURATION.5 ORDERING INFORMATION DESCRIPTION TYPICAL CONNECTIONS THERMAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS.10 RECOMMENDED OPERATING CONDITIONS SPEAKER POWER DE-RATING CURVE.11 ELECTRICAL CHARACTERISTICS
REGULATOR ELECTRICAL CHARACTERISTICS DC-DC CONVERTER ELECTRICAL CHARACTERISTICS
TYPICAL POWER CONSUMPTION
LIN2 RIN2 ADC. LON/LOP RON/ROP LOUT/ROUT SPEAKER. POWER STATES
TYPICAL PERFORMANCE DATA.29
SPEAKER DRIVER PERFORMANCE HEADPHONE DRIVER PERFORMANCE. PSRR PERFORMANCE.
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING. AUDIO INTERFACE TIMING MASTER MODE AUDIO INTERFACE TIMING SLAVE MODE AUDIO INTERFACE TIMING MODE CONTROL INTERFACE TIMING 2-WIRE MODE CONTROL INTERFACE TIMING 3-WIRE MODE
CODEC POWER RESET CIRCUIT CONTROL INTERFACE.39 CLOCKING SAMPLE RATES AUDIO CODEC SUBSYSTEM
INTRODUCTION. AUDIO SIGNAL PATHS. ENABLING AUDIO CODEC INPUT SIGNAL PATH. ANALOGUE DIGITAL CONVERTER (ADC) DIGITAL MIXING DIGITAL ANALOGUE CONVERTER (DAC) OUTPUT SIGNAL PATH. ANALOGUE OUTPUTS GENERAL PURPOSE INPUT/OUTPUT DIGITAL AUDIO INTERFACE. DIGITAL AUDIO INTERFACE CONTROL
April 2009,
WM8400
Pre-Production
AUDIO CODEC POWER MANAGEMENT
POWER MANAGEMENT SUBSYSTEM .134
INTRODUCTION. POWER SEQUENCING CONTROL. POWER MANAGEMENT OPERATING MODES CONFIGURING DC-DC CONVERTERS REGULATORS. DC-DC CONVERTER OPERATION REGULATOR OPERATION. CURRENT REFERENCE. BATTERY MONITORING UNDERVOLTAGE LOCK-OUT (UVLO)
INTERRUPT EVENTS .150 TEMPERATURE SENSING .153 DEVICE SHUTDOWN .154 CHIP RESET .156
HARDWARE RESET SOFTWARE RESET.
REGISTER MAP.157
REGISTER BITS ADDRESS
DIGITAL FILTER CHARACTERISTICS .194
FILTER RESPONSES HIGH PASS FILTER RESPONSES FILTER RESPONSES DE-EMPHASIS FILTER RESPONSES
APPLICATIONS INFORMATION .198
RECOMMENDED EXTERNAL COMPONENTS. LAYOUT CONSIDERATIONS.
PACKAGE DIMENSIONS .207 IMPORTANT NOTICE .208
ADDRESS:.
April 2009,
Pre-Production
WM8400
CONFIGURATION
ORDERING INFORMATION
ORDER CODE WM8400GEB/V WM8400GEB/RV Note: Reel quantity 2,200 TEMPERATURE RANGE -40°C +85°C -40°C +85°C PACKAGE 105-ball (Pb-free) 105-ball (Pb-free, tape reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC
April 2009,
WM8400 C11, A11, NAME ADCDAT ADCLRC/GPIO1 AGND AVDD BCLK CDELAY DACDAT DACLRC DC1EN DC1FB DC1GND DC1LX DC1LX DC1VDD DC1VSEL DC2EN DC2FB DC2GND DC2LX DC2LX DC2VDD DC2VSEL DCVDD FLLVDD TYPE Digital Output Digital Input Output Supply Supply Digital Input Output Analogue Output Digital Input Digital Input Output Digital Input Analogue Input Supply Analogue Input/Output Analogue Input/Output Supply Analogue Input Digital Input Analogue Input Supply Analogue Input/Output Analogue Input/Output Supply Analogue Input Supply Connect Supply Supply DESCRIPTION digital audio data output Audio interface left/right clock GPIO Analogue ground (return path AVDD) Analogue supply Audio interface clock Converter start-up time (external capacitor) digital audio data input Audio interface left right clock Enable DC-DC1 Feedback DCDC1 DC-DC1 ground (return path DC-DC1) Connection DCDC1 Inductor Connection DCDC1 Inductor Power input DC-DC1 Startup voltage select DC-DC1 Enable DC-DC2 Feedback DCDC2 DC-DC2 ground (return path DC-DC2) Connection DCDC2 Inductor Connection DCDC2 Inductor Power input DC-DC2 Startup voltage select DC-DC2 Digital Core Supply Connect Supply Ground
Pre-Production
DOMAIN I2S1VDD I2S1VDD
I2S1VDD I2S1VDD I2S1VDD HBVDD DC1VDD DC1VDD DC1VDD VINT HBVDD DC2VDD DC2VDD DC2VDD VINT
GPIO2/MCLK2 GPIO3/BCLK2 GPIO4/DACLRC2 GPIO5/DACDAT2 GPIO6/ADCLRCB HBVDD HPGND HPVDD HSLEEP I2CVDD I2S1VDD I2S2VDD LDO1EN LDO1OUT LDO1VDD LDO1VSEL LDO2EN LDO2OUT LDO2VDD LDO2VSEL LDO3OUT
Digital Input Output Digital Input Output Digital Input Output Digital Input Output Digital Input Output Supply Supply Supply Digital Input Supply Supply Supply Digital Input Analogue Output Supply Analogue Input Digital Input Analogue Output Supply Analogue Input Analogue Output
Alternative MCLK GPIO Alternative BCLK GPIO Alternative DACLRC GPIO Alternative DACDAT GPIO Inverted ADCLRC GPIO Power supply Host Buffer interface Headphone ground (return path HPVDD) Headphone supply Sleep Host Buffer interface Power supply control (I2C) interface Power supply primary digital audio (I2S) interface Power supply secondary digital audio (I2S) interface Enable Power Output from Supply Startup voltage select Enable Power Output from Supply Startup voltage select Power Output from
I2S2VDD I2S2VDD I2S2VDD I2S2VDD I2S2VDD
HBVDD
HBVDD LDO1VDD VINT HBVDD LDO2VDD VINT LDO3VDD April 2009,
Pre-Production NAME LDO3VDD LDO4OUT LDO4VDD LIN1 LIN2 LIN3 LIN4 LINE LOUT MBVDD MCLK MICBIAS MODE MSLEEP NCSADDR NIRQ NPDN NRST OUT3 OUT4 PSEQ1 PSEQ2 PSEQ3 PSEQ4 PWRGOOD RIN1 RIN2 RIN3 RIN4 RIREF ROUT RSTTRIG SCLK SDIN SPKGND SPKN SPKP SPKVDD VINT VMID Supply Analogue Output Supply Analogue Input Analogue Input Analogue Input Digital Input Analogue Input Supply Analogue Output Analogue Output Analogue Output Supply Digital Input Analogue Output Digital Input Digital Input Digital Input Digital Output Digital Input Digital Output Analogue Output Analogue Output Digital Output Digital Output Digital Output Digital Output Digital Output Analogue Input Analogue Input Analogue Input Digital Input Analogue Input Analogue Input Analogue Output Analogue Output Analogue Output Digital Input Digital Input Digital Input Output Supply Analogue Output Analogue Output Supply Analogue Output Analogue Output TYPE Supply Power Output from Supply Left input negative diff input Left line input positive diff input Left line input negative diff input button detect Left line input differential Mono diff Main battery input line Differential Left Line (-)ve Differential Left Line (+)ve Left headphone output Power supply interface Master clock input Microphone bias Selects 2-wire 3/4-wire control Sleep interface 3-wire chip select 2-wire address select Interrupt output (active low) Power down (active low) Reset output (active low) Inverted left headphone output Mono inverted output Inverted right headphone output Mono noninverted output Power Sequencing Output Power Sequencing Output Power Sequencing Output Power Sequencing Output Power Good Signal Right input negative diff input Right line input positive diff input Right line input negative diff input button detect Right line input differential Mono diff Bias Current (external resistor) Differential Right Line (-)ve Differential Right Line (+)ve Right headphone output Trigger input reset timer Control interface clock input (2/3-wire) Control interface data input 2-wire acknowledge Speaker ground (return path SPKVDD) Speaker negative output Speaker positive output Speaker supply Decoupling point internal supply CODEC midrail reference voltage
WM8400
DOMAIN LDO4VDD AVDD AVDD AVDD AVDD AVDD AVDD HPVDD I2S1VDD AVDD I2CVDD MBVDD I2CVDD MBVDD HBVDD MBVDD HPVDD HPVDD LINE LINE LINE LINE HBVDD AVDD AVDD AVDD AVDD AVDD AVDD HPVDD HBVDD I2CVDD I2CVDD SPKVDD SPKVDD
AVDD
Note: Digital input pins have Schmitt trigger input buffers 3.3V tolerant.
April 2009,
WM8400 TYPICAL CONNECTIONS
Pre-Production
play record
MSLEEP, NIRQ, NRST
output drivers
PWRGOOD, HSLEEP
April 2009,
Pre-Production
WM8400
THERMAL CHARACTERISTICS
Thermal analysis must performed intended application prevent WM8400 from exceeding maximum junction temperature. Several contributing factors affect thermal performance most notably physical properties mechanical enclosure, location device relation surrounding components number layers. Connecting central balls through thermal vias into large ground plane will heat extraction. Three main heat transfer paths exist surrounding illustrated below: Package (radiation). Package bottom (radiation). Package leads (conduction).
temperature rise given power dissipated device. thermal resistance from junction ambient temperature therefore measure heat transfer from surrounding air. WM8400, 46°C/W
junction temperature given ambient temperature.
worst case conditions when WM8400 operating high ambient temperature, with supply voltage, high duty cycle high output current. Under such conditions, possible that heat dissipated could exceed maximum junction temperature device. Care must taken avoid this situation. example calculation junction temperature given below. 0.98W (example figure) 46°C/W 45.08°C 85°C (example figure) 130.08°C
minimum maximum operating junction temperatures WM8400 quoted "Absolute Maximum Ratings" section. maximum recommended operating junction temperature 125°C. Therefore, junction temperature above example exceeds operating limits WM8400, recommended sustained operation.
April 2009,
WM8400 ABSOLUTE MAXIMUM RATINGS
Pre-Production
Absolute Maximum Ratings stress ratings only. Permanent damage device caused continuously operating beyond these limits. Device functional operating limits guaranteed performance specifications given under Electrical Characteristics test conditions specified. Sensitive Device. This device manufactured CMOS process. therefore generically susceptible damage from excessive static voltages. Proper precautions must taken during handling storage this device. Wolfson tests package types according IPC/JEDEC J-STD-020B Moisture Sensitivity determine acceptable storage conditions prior surface mount assembly. These levels are: MSL1 unlimited floor life <30°C Relative Humidity. normally stored moisture barrier bag. MSL2 storage year <30°C Relative Humidity. Supplied moisture barrier bag. MSL3 storage hours <30°C Relative Humidity. Supplied moisture barrier bag. Moisture Sensitivity Level each package type specified Ordering Information. CONDITION Supply voltages: MBVDD, HBVDD, I2CVDD, I2S1VDD, I2S2VDD, FLLVDD, HPVDD, AVDD, DCVDD Supply voltages: LINE, DC1VDD, DC2VDD, LDO1VDD, LDO2VDD, LDO3VDD, LDO4VDD, SPKVDD Voltage range digital inputs -0.3V -0.3V 0.3V +4.5V HBVDD 0.3V MBVDD 0.3V I2CVDD 0.3V I2S1VDD 0.3V I2S2VDD 0.3V AVDD 0.3V FLLVDD 0.3V LINE 0.3V HPVDD 0.3V
Voltage range analogue inputs
AGND 0.3V 0.3V HPGND 0.3V
Junction temperature, Storage temperature after soldering Analogue, digital speaker grounds must always within 0.3V each other.
I2CVDD Maximum voltage limit should never exceeded duration time.
April 2009,
Pre-Production
WM8400
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital core supply range Digital interfaces supply range Analogue supplies range SYMBOL DCVDD HBVDD, MBVDD, I2CVDD, I2S1VDD, I2S2VDD LINE LDO1VDD, LDO2VDD, LDO3VDD, LDO4VDD DC1VDD, DC2VDD Analogue supplies range Speaker supply range Ground Ambient temperature, Junction temperature, Notes Analogue, digital speaker grounds must always within 0.3V each other. digital analogue supplies completely independent from each other (i.e. internally connected). DCVDD must less than equal AVDD. DCVDD must less than equal MBVDD, I2S1VDD I2S2VDD. AVDD must less than equal SPKVDD. HPVDD must equal AVDD SPKVDD must high enough support peak output voltage when using DCGAIN ACGAIN functions, avoid output waveform clipping. Peak output voltage AVDD*(DCGAIN+ACGAIN)/2. minimum LINE voltage starting WM8400 also determined programmable threshold. "Battery Monitoring Undervoltage Lock-Out (UVLO)". LDOnVDD DCnVDD must high enough support required output voltage from respective regulator converter. "Electrical Characteristics". AVDD, FLLVDD, HPVDD, SPKVDD GND, AGND, HPGND, SPKGND 1.71 1.71 +125 UNIT
Junction temperature function ambient temperature device operating conditions. ambient temperature limits junction temperature limits must both observed. "Thermal Characteristics".
SPEAKER POWER DE-RATING CURVE
speaker driver been designed drive maximum into 8ohm class mode, 0.5W into class mode. These figures based operation room temperature operation higher temperatures please refer power de-rating curve below. Under circumstances should recommended maximum powers junction temperature device exceeded.
Figure Speaker Power De-Rating Curve
April 2009,
WM8400 ELECTRICAL CHARACTERISTICS
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Maximum Full-Scale Input Signal Level Note This changes proportion AVDD. FullScale level typically AVDD/3.3Vrms Note When mixing input outputs line inputs total signal must exceed values shown here. TEST CONDITIONS Single-ended input LIN1, LIN3, RIN1 RIN3, output INMIXL INMIXR Differential input LIN1/LIN2, LIN3/LIN4, RIN1/RIN2 RIN3/RIN4, output INMIXL INMIXR Differential input single-ended inputs LIN1/LIN3 RIN1/RIN3, output DIFFINL DIFFINR 0.909 -0.829
Pre-Production
UNIT Vrms
Analogue Input Maximum Signal Levels (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4)
0.909 -0.829
Vrms
0.909 -0.829
Vrms
Maximum Full-Scale Line Input Signal Level Note This changes proportion AVDD. FullScale level typically AVDD/3.3Vrms Note When mixing line inputs, input outputs outputs total signal must exceed values shown here.
Line input LIN2, LIN4, RIN2 RIN4 INMIXL INMIXR
0.909 -0.829
Vrms
Line input LIN2 RIN2 SPKMIX
0.909 -0.829
Vrms
Line input LIN3 RIN3 LOMIX ROMIX
0.909 -0.829
Vrms
Differential mono line input RXP/RXN RXVOICE
LIN4/RXN
RXVOICE
RIN4/RXP
AINLMUX AINRMUX
0.909 -0.829
Vrms
Differential mono line input RXP/RXN differential output OUT3/OUT4
0.909 -0.829
Vrms
April 2009,
Pre-Production
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Input Resistance Note: this will seen parallel with resistance other enabled input paths from same TEST CONDITIONS LIN1, LIN3, RIN1 RIN3 (PGA Gain -16.5dB) LIN1, LIN3, RIN1 RIN3 (PGA Gain 0dB) LIN1, LIN3, RIN1 RIN3 (PGA Gain +30dB) LIN2, LIN4, RIN2 RIN4 (Constant gains) UNIT
Analogue Input Impedances (LIN1, LIN2, LIN3, LIN4, RIN1, RIN2, RIN3, RIN4)
Line Input Resistance Note: this will seen parallel with resistance other enabled input paths from same
LIN2 RIN2 INMIXL INMIXR (-12dB) LIN2 RIN2 INMIXL INMIXR (0dB) LIN2 RIN2 INMIXL INMIXR (+6dB) LIN2 RIN2 SPKMIX (SPKATTN 0dB) LIN2 RIN2 SPKMIX (SPKATTN -12dB) LIN3 RIN3 LOMIX ROMIX (0dB) LIN3 RIN3 LOMIX ROMIX (-21dB) RXVOICE AINLMUX AINRMUX (Gain +6dB) RXVOICE AINLMUX AINRMUX (Gain 0dB) RXVOICE AINLMUX AINRMUX (Gain -12dB) RXVOICE AINLMUX AINRMUX (Gain +6dB) RXVOICE AINLMUX AINRMUX (Gain 0dB) RXVOICE AINLMUX AINRMUX (Gain -12dB) LIN4 OUT3 RIN4 OUT4 (Gain -6dB) LIN4 OUT3 RIN4 OUT4 (Gain 0dB)
Input Capacitance
analogue input pins
April 2009,
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER equivalent input noise Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute Attenuation Guaranteed monotonic output mixers (directly) output mixers (via AINLMUX AINRMUX) Common Mode Rejection Ratio (1kHz input) Single differential mode, gain +30dB Single differential mode, gain Single differential mode, gain -16.5dB Differential input DIFFINL DIFFINR LIN1/LIN3 RIN1/RIN3, gain Received Voice (RXP-RXN) Differential Single-Ended Converter RXVOICE Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute Attenuation Fixed Gain Mute Attenuation Input Mixers INMIXL INMIXR Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Minimum Programmable Gain Maximum Programmable Gain Programmable Gain Step Size Mute attenuation Outputs INMIXL INMIXR Outputs INMIXL INMIXR Outputs INMIXL INMIXR Line Inputs Record path INMIXL INMIXR Line Inputs Record path INMIXL INMIXR Line Inputs Record path INMIXL INMIXR AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE AINLMODE AINRMODE TEST CONDITIONS 20kHz, +30dB gain -16.5
Pre-Production
UNIT
Input Programmable Gain Amplifiers (PGAs) LIN12, LIN34, RIN12 RIN34
Output Differential Single Ended Converters DIFFINL DIFFINR
April 2009,
Pre-Production
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Input Path Performance (A-weighted) (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) Crosstalk (L/R) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) (A-weighted) (-1dBFS input) THD+N (-1dBFS input) Input PGAs INMIXL INMIXR, AVDD 2.7V Input PGAs DIFFINL DIFFINR, AVDD 3.0V Input PGAs DIFFINL DIFFINR, AVDD 2.7V RXP-RXN RXVOICE, AVDD 3.0V RXP-RXN RXVOICE, AVDD 2.7V Line inputs INMIXL INMIXR, AVDD 3.0V Line inputs INMIXL INMIXR, AVDD 2.7V Record path (DACs ADCs INMIXL INMIXR), AVDD 3.0V Record path (DACs ADCs INMIXL INMIXR), AVDD 2.7V Input PGAs INMIXL INMIXR, AVDD 3.0V TEST CONDITIONS UNIT
April 2009,
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER (A-weighted) THD+N Crosstalk (L/R) AVDD PSRR (217Hz) (A-weighted) THD+N (A-weighted) THD+N Crosstalk (L/R) AVDD PSRR (217Hz) Offset Load (A-weighted) THD+N Minimum Line Resistance Maximum Line Capacitance (A-weighted) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=5mW) THD+N (PO=5mW) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) LOUT, ROUT, RL=16, AVDD=HPVDD= 2.7V
DACL DACR
Pre-Production
TEST CONDITIONS singleended line out, 0dBFS input, AVDD 3.0V
-100
UNIT
Output Path (Line Outputs 50pF Load, Headphone Outputs Load, Speaker Output Load)
singleended line out, 0dBFS input, AVDD 2.7V differential line out, 0dBFS input, AVDD 3.0V
-100
differential line out, 0dBFS input, AVDD 2.7V LOP, LON, ROP, LOP, LON, ROP, LOUT ROUT, RL=32, AVDD=HPVDD= 3.0V
AC-Coupled Headphone Outputs -100
LOUT ROUT, RL=32, AVDD=HPVDD= 2.7V LOUT ROUT, RL=16, AVDD=HPVDD= 3.0V
AC-Coupled Headphone Outputs
LOUT ROUT
-100
LOMIX ROMIX
RLOAD 16Ohm
April 2009,
Pre-Production Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) Crosstalk (L/R) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Offset Load (A-weighted) (PO=5mW) THD+N (PO=5mW) LOUT/OUT3 ROUT/OUT4, RL=32, AVDD=HPVDD= 2.7V LOUT, ROUT, OUT3, OUT4 Speaker Output (Direct) AVDD=3.0V, SPKVDD=5V, class controlled using volume, ACGAIN=DCGA IN=1.67 Speaker Output (Direct) AVDD=3.0V, SPKVDD=5V, class controlled using volume LOUT/OUT3 ROUT/OUT4, RL=32, AVDD=HPVDD= 3.0V TEST CONDITIONS Fully Differential Headphone Outputs -100
WM8400
UNIT
Minimum Headphone Resistance (A-weighted) (PO=0.5W) THD+N (PO=0.5W) (PO=0.9W) THD+N (PO=0.9W) SPKVDD PSRR(217Hz) (A-weighted) (PO=0.2W) THD+N (PO=0.2W) (PO=0.45W) THD+N (PO=0.45W) SPKVDD PSRR(217Hz) Offset Load
April 2009,
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER (A-weighted) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Offset Load (A-weighted) (PO=5mW) THD+N (PO=5mW) Differential Input RXP/RXN Differential Output OUT3/OUT4, AVDD=HPVDD= 3.0V Differential Input RXP/RXN Differential Output OUT3/OUT4, AVDD=HPVDD= 2.7V RXVOICE LOMIX ROMIX Headphone Outputs, AVDD=HPVDD= 3.0V RXVOICE LOMIX ROMIX Headphone Outputs, AVDD=HPVDD= 2.7V Line Input SPKMIX, AVDD=3.0V, SPKVDD=5V, ACGAIN= DCGAIN=1.67, Class Mode TEST CONDITIONS
Pre-Production
UNIT
Bypass Path Performance (Line Outputs 50pF load, Headphone Outputs load, Speaker Output load)
(A-weighted) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) (A-weighted) (PO=5mW) THD+N (PO=5mW)
(A-weighted) (PO=0.5W) THD+N (PO=0.5W) (PO=0.9W) THD+N (PO=0.9W) AVDD PSRR (217Hz) SPKVDD PSRR(217Hz) (A-weighted) (PO=0.5W) THD+N (PO=0.5W) AVDD PSRR (217Hz) SPKVDD PSRR(217Hz) Offset Load
Line Input SPKMIX, AVDD=3.0V, SPKVDD=5V, Class Mode
April 2009,
Pre-Production Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER (A-weighted) (0dB output) THD+N (0dB output) AVDD PSRR (217Hz) Offset Load (A-weighted) (0dB output) THD+N (0dB output) (A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Crosstalk (L/R) (A-weighted) (PO=5mW) THD+N (PO=5mW) Input LOMIX ROMIX LOUT ROUT, RL=16, AVDD=HPVDD= 2.7V Line Input Headphones LOMIX ROMIX, RL=16, AVDD=HPVDD= 3.0V Input Differential Line Out, AVDD=2.7V Input LOMIX ROMIX LOUT ROUT, RL=16, AVDD=HPVDD= 3.0V Input Differential Line Out, AVDD=3.0V TEST CONDITIONS
WM8400
UNIT
(A-weighted) (PO=20mW) THD+N (PO=20mW) (PO=5mW) THD+N (PO=5mW) AVDD PSRR (217Hz) HPVDD PSRR (217Hz) Crosstalk (L/R) (A-weighted) (PO=5mW) THD+N (PO=5mW)
Line Input Headphones LOMIX ROMIX, RL=16, AVDD=HPVDD= 2.7V
April 2009,
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Multi-Path Channel Separation Headset Voice Call: DAC/Headset Voice Separation 1kHz 0dBFS playback LOUT ROUT; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output Headset Voice Call: DAC/Speaker Voice Separation 1kHz 0dBFS playback speaker, output; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output Voice Call: Voice Voice Separation fs=8kHz DAC, DAC_SB_FILT=1; -5dBFS differential mono output from DACs OUT3/OUT4; Quiescent input input (Gain=+12dB) INMIXL INMIXR; Measure crosstalk output Speakerphone Voice Call: DAC/Speaker Separation fs=8kHz DAC, DAC_SB_FILT=1; 0dBFS output speaker output); record from input (Gain=+30dB); Measure crosstalk output Speaker Voice Call: Voice Voice Separation
LIN1 RIN1
Pre-Production
TEST CONDITIONS
UNIT
LOAD
+12dB
LIN12 RIN12 (Single-ended differential mode)
LOPMIX ROPMIX
1kHz Full scale differential input RXP/RXN, output OUT3/OUT4; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output
LIN2 RIN2
Quiescent input
LIN4/RXN
OUT3MIX
OUT3
Full scale input
RIN4/RXP
LOAD
OUT4
OUT4MIX
April 2009,
Pre-Production Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Headset Voice Call: Voice Voice Separation 1kHz full scale differential input RXP/RXN RXVOICE LOMIX ROMIX, output LOUT ROUT; Quiescent input LIN12 RIN12 (Gain=+12dB), differential output LOP/LON ROP/RON; Measure crosstalk LOP/LON ROP/RON output Stereo Line Record Playback: DAC/Headset Separation -5dBFS input DACs, playback LOUT ROUT1; record from line input; Measure crosstalk output TEST CONDITIONS
WM8400
UNIT
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Analogue Reference Levels VMID Midrail Reference Voltage VREF Buffered Reference Voltage Microphone Bias Bias Voltage load current MBSEL=0 load current MBSEL=1 Bias Current Source Output Noise Density AVDD PSRR (217Hz) 1kHz 20kHz 100mV pk-pk @217Hz AVDD nV/Hz AVDD/2 AVDD/2 TEST CONDITIONS UNIT
April 2009,
WM8400
Test Conditions DCVDD 1.8V, HBVDD MBVDD I2CVDD I2S1VDD I2S2VDD AVDD HPVDD 3.0V, SPKVDD +25oC, 1kHz signal, 44.1kHz, gain 0dB, 24-bit audio data unless otherwise stated. PARAMETER Digital Input Output Input HIGH Level 0.7xHBVDD 0.7x MBVDD 0.7x I2CVDD 0.7x I2S1VDD 0.7x I2S2VDD TEST CONDITIONS
Pre-Production
UNIT
Input Level
0.3xHBVDD 0.3x MBVDD 0.3x I2CVDD 0.3x I2S1VDD 0.3x I2S2VDD IOL=1mA 0.9xHBVDD 0.9x MBVDD 0.9x I2CVDD 0.9x I2S1VDD 0.9x I2S2VDD 0.1xHBVDD 0.1x MBVDD 0.1x I2CVDD 0.1x I2S1VDD 0.1x I2S2VDD -0.9 22000
Output HIGH Level
Output Level
IOH=-1mA
Input capacitance Input leakage Input Frequency Lock time GPIO Clock output duty cycle (Integer OPCLKDIV) SYSCLK=MCLK; OPCLKDIV=0000 SYSCLK=MCLK; OPCLKDIV=1000 SYSCLK=FLL output; OPCLKDIV=0000 SYSCLK=FLL output; OPCLKDIV=1000 Clock output duty cycle (Non-integer OPCLKDIV) SYSCLK=MCLK; OPCLKDIV=0100 SYSCLK=FLL output; OPCLKDIV=0100 Interrupt response time accessory button detect Input de-bounced Input de-bounced TOCLKSEL=1 Input de-bounced
Clock Periods
fSYSCLK fSYSCLK
fSYSCLK fSYSCLK
April 2009,
Pre-Production
WM8400
REGULATOR ELECTRICAL CHARACTERISTICS
Test Conditions 3.7V, Vout 1.8V, 25oC unless otherwise stated. PARAMETER Regulators Active Mode Input Voltage Output Voltage (see notes) Regulation accuracy Dropout voltage Maximum Load current Quiescent current Leakage current Power supply rejection ratio Regulators Current Switch Mode resistance Notes supply voltage, connected LDO1VDD, LDO2VDD, LDO3VDD LDO4VDD LDOs1-4 respectively. addition limits noted above, maximum output voltage, Vout, also function input voltage. This function dropout voltage applicable operating conditions. 3.7V, <250mA load 1kHz, Vout 1.8v, 25mA load 100Hz, Vout 1.8v, 25mA load Iout Iout 150mA, Vout 1.8V Iout 150mA, Vout 1.8V load TEST CONDITIONS UNIT
April 2009,
WM8400
DC-DC CONVERTER ELECTRICAL CHARACTERISTICS
Test Conditions 3.7V, Vout 1.8V, 25oC unless otherwise stated. PARAMETER DC-DC Converters Input Voltage Output Voltage (see notes) Output Voltage accuracy (Vin 3.7V, Vout 0.85V 3.4V) Line regulation (Vin 2.7V 5.5V; Vout 1.8V) Load Regulation Maximum Load Current (see notes) Active Mode; 0.5A Standby Mode; 0.1A Hibernate/LDO Mode; Active Mode; 0.5A Standby Mode; 0.1A Hibernate/LDO Mode; Output current Active Mode Standby Mode Hibernate/LDO Mode Quiescent current Active Mode Standby Mode Hibernate/LDO Mode Shutdown current P-channel Resistance (RDSP) N-channel Resistance (RDSN) P-channel leakage current N-channel leakage current Switching frequency Notes 3.7V, Output 100mA 3.7V, Output 100mA 3.7V, DCnLX 3.7V, DCnLX 3.7V 0.85 -1.5%, +4.5% ±0.5% ±0.5% ±0.2% ±0.5% 0.01 0.25 2.048 TEST CONDITIONS
Pre-Production
UNIT
DC-DC converter supply voltage, connected DC1VDD DC2VDD respectively. addition limits noted above, maximum output voltage, Vout, also function input voltage. This function P-channel Resistance (RDSP) N-channel Resistance (RDSN) applicable operating conditions. DCnLX DC-DC converter output DC1LX DC2LX respectively. maximum output current achievable subject current limit particular converter being appropriately, also junction temperature device.
April 2009,
Pre-Production
WM8400
TYPICAL POWER CONSUMPTION
data contained within this section based upon following test voltage conditions:
Voltages SPKVDD 3.7000 Speaker) HPVDD 3.00 AVDD 3.00 I2S1VDD 1.80 DCVDD 1.80 I2CVDD 1.80 FLLVDD 3.00 HBVDD 1.80 VLINE 3.70
LIN2 RIN2
LIN2/RIN2 Stereo Record Slave 44.1k
SPKVDD Current (mA) 0.0001 HPVDD Current (mA) 0.0001 AVDD Current (mA) 4.0230 I2S1VDD Current (mA) 0.0496 DCVDD Current (mA) 2.7910 I2CVDD Current (mA) -0.0002 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 17.1831 Total Power With VLINE, HBVDD (mW) 17.7456
LIN2/RIN2 Stereo Record Slave,
SPKVDD Current (mA) 0.0000 HPVDD Current (mA) 0.0001 AVDD Current (mA) 3.8270 I2S1VDD Current (mA) 0.0104 DCVDD Current (mA) 0.5180 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 12.4328 Total Power With VLINE, HBVDD (mW) 12.9953
LIN2/RIN2 Stereo Record Slave, Quiescent, 44.1k
SPKVDD Current (mA) -0.0001 HPVDD Current (mA) 0.0002 AVDD Current (mA) 3.9980 I2S1VDD Current (mA) 0.0336 DCVDD Current (mA) 2.7600 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 17.0239 Total Power With VLINE, HBVDD (mW) 17.5864
LIN2/RIN2 Stereo Record Slave, Quiescent,
SPKVDD Current (mA) -0.0004 HPVDD Current (mA) 0.0000 AVDD Current (mA) 3.8020 I2S1VDD Current (mA) 0.0075 DCVDD Current (mA) 0.5100 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 12.3392 Total Power With VLINE, HBVDD (mW) 12.9017
LIN2/RIN2 Stereo Record Master, 44.1k
SPKVDD Current (mA) -0.0001 HPVDD Current (mA) 0.0001 AVDD Current (mA) 4.0230 I2S1VDD Current (mA) 0.2610 DCVDD Current (mA) 2.8130 I2CVDD Current (mA) 0.0001 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 17.6033 Total Power With VLINE, HBVDD (mW) 18.1658
LIN2/RIN2 Stereo Record Master,
SPKVDD Current (mA) 0.0000 HPVDD Current (mA) 0.0001 AVDD Current (mA) 3.8280 I2S1VDD Current (mA) 0.0487 DCVDD Current (mA) 0.5220 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 12.5119 Total Power With VLINE, HBVDD (mW) 13.0745
LIN2/RIN2 Stereo Record Master FLL, 44.1k
SPKVDD Current (mA) 0.0001 HPVDD Current (mA) 0.0002 AVDD Current (mA) 4.0250 I2S1VDD Current (mA) 0.2600 DCVDD Current (mA) 5.1370 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.4010 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 22.9936 Total Power With VLINE, HBVDD (mW) 23.5560
LIN2/RIN2 Stereo Record Master FLL,
SPKVDD Current (mA) -0.0002 HPVDD Current (mA) 0.0003 AVDD Current (mA) 3.9600 I2S1VDD Current (mA) 0.1860 DCVDD Current (mA) 5.1360 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.4270 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 22.7424 Total Power With VLINE, HBVDD (mW) 23.3048
April 2009,
WM8400
LON/LOP RON/ROP
LON/LOP RON/ROP Slave 44.1k,
SPKVDD Current (mA) -0.0001 HPVDD Current (mA) 0.4610 AVDD Current (mA) 3.9350 I2S1VDD Current (mA) 0.0121 DCVDD Current (mA) 2.6930 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 18.0576
Pre-Production
Total Power With VLINE, HBVDD (mW) 18.6201
LON/LOP RON/ROP Slave
SPKVDD Current (mA) -0.0001 HPVDD Current (mA) 0.4600 AVDD Current (mA) 3.8080 I2S1VDD Current (mA) 0.0022 DCVDD Current (mA) 0.5060 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 13.7193 Total Power With VLINE, HBVDD (mW) 14.2819
LON/LOP RON/ROP Master 44.1k,
SPKVDD Current (mA) -0.0002 HPVDD Current (mA) 0.4610 AVDD Current (mA) 3.9350 I2S1VDD Current (mA) 0.2230 DCVDD Current (mA) 2.7150 I2CVDD Current (mA) 0.0001 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 18.4774 Total Power With VLINE, HBVDD (mW) 19.0398
LON/LOP RON/ROP Master
SPKVDD Current (mA) -0.0001 HPVDD Current (mA) 0.4610 AVDD Current (mA) 3.8090 I2S1VDD Current (mA) 0.0410 DCVDD Current (mA) 0.5090 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 13.8006 Total Power With VLINE, HBVDD (mW) 14.3631
LON/LOP RON/ROP Master 44.1k,
SPKVDD Current (mA) 0.0000 HPVDD Current (mA) 0.4610 AVDD Current (mA) 3.9340 I2S1VDD Current (mA) 0.2220 DCVDD Current (mA) 5.0230 I2CVDD Current (mA) -0.0001 FLLVDD Current (mA) 0.3990 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 23.8233 Total Power With VLINE, HBVDD (mW) 24.3857
LON/LOP RON/ROP Master
SPKVDD Current (mA) -0.0002 HPVDD Current (mA) 0.4610 AVDD Current (mA) 3.8920 I2S1VDD Current (mA) 0.1580 DCVDD Current (mA) 4.9930 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.4240 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 23.6036 Total Power With VLINE, HBVDD (mW) 24.1661
LOUT/ROUT
LOUT/ROUT Slave 44.1k,
SPKVDD Current (mA) -0.0001 HPVDD Current (mA) 11.272 AVDD Current (mA) 2.9020 I2S1VDD Current (mA) 0.0117 DCVDD Current (mA) 2.6940 I2CVDD Current (mA) 0.0001 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 47.3929 Total Power With VLINE, HBVDD (mW) 47.9555
LOUT/ROUT Slave 44.1k, 0.1mW
SPKVDD Current (mA) 0.0001 HPVDD Current (mA) 1.8270 AVDD Current (mA) 2.8980 I2S1VDD Current (mA) 0.0121 DCVDD Current (mA) 2.6930 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 19.0448 Total Power With VLINE, HBVDD (mW) 19.6072
LOUT/ROUT Slave 44.1k, Quiescent
SPKVDD Current (mA) -0.0002 HPVDD Current (mA) 0.4640 AVDD Current (mA) 2.8880 I2S1VDD Current (mA) 0.0115 DCVDD Current (mA) 2.7360 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 15.0022 Total Power With VLINE, HBVDD (mW) 15.5647
April 2009,
Pre-Production LOUT/ROUT Slave
SPKVDD Current (mA) 0.0000 HPVDD Current (mA) 11.274 AVDD Current (mA) 2.7750 I2S1VDD Current (mA) 0.0023 DCVDD Current (mA) 0.5050 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 43.0603
WM8400
Total Power With VLINE, HBVDD (mW) 43.6230
LOUT/ROUT Slave 0.1mW
SPKVDD Current (mA) 0.0000 HPVDD Current (mA) 1.8270 AVDD Current (mA) 2.7710 I2S1VDD Current (mA) 0.0023 DCVDD Current (mA) 0.5050 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 14.7072 Total Power With VLINE, HBVDD (mW) 15.2697
LOUT/ROUT Slave Quiescent
SPKVDD Current (mA) 0.0000 HPVDD Current (mA) 0.5540 AVDD Current (mA) 2.7530 I2S1VDD Current (mA) 0.0021 DCVDD Current (mA) 0.5050 I2CVDD Current (mA) 0.0001 FLLVDD Current (mA) 0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1520 Total Power Without VLINE, HBVDD (mW) 10.8342 Total Power With VLINE, HBVDD (mW) 11.3967
SPEAKER
Class Speaker Slave 44.1k,
SPKVDD Current (mA) 290.7670 HPVDD Current (mA) 0.0001 AVDD Current (mA) 1.6890 I2S1VDD Current (mA) 0.0120 DCVDD Current (mA) 1.7880 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1530 Total Power Without VLINE, HBVDD (mW) 1462.1424 Total Power With VLINE, HBVDD (mW) 1462.7086
Class Speaker Slave 44.1k,
SPKVDD Current (mA) 286.8830 HPVDD Current (mA) 0.0001 AVDD Current (mA) 2.2590 I2S1VDD Current (mA) 0.0120 DCVDD Current (mA) 1.7940 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1530 Total Power Without VLINE, HBVDD (mW) 1444.4432 Total Power With VLINE, HBVDD (mW) 1445.0094
Class Speaker Slave 44.1k, 22µH
SPKVDD Current (mA) 256.8060 HPVDD Current (mA) 0.0002 AVDD Current (mA) 1.7120 I2S1VDD Current (mA) 0.0116 DCVDD Current (mA) 1.7570 I2CVDD Current (mA) 0.0001 FLLVDD Current (mA) -0.0001 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1530 Total Power Without VLINE, HBVDD (mW) 1292.3503 Total Power With VLINE, HBVDD (mW) 1292.9165
Class Speaker Slave 44.1k, 22µH Quiescent
SPKVDD Current (mA) 3.9450 HPVDD Current (mA) 0.0000 AVDD Current (mA) 1.7110 I2S1VDD Current (mA) 0.0113 DCVDD Current (mA) 1.7680 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1530 Total Power Without VLINE, HBVDD (mW) 28.0610 Total Power With VLINE, HBVDD (mW) 28.6271
Class Speaker Slave 44.1k, 22µH
SPKVDD Current (mA) 213.1460 HPVDD Current (mA) 0.0001 AVDD Current (mA) 2.2250 I2S1VDD Current (mA) 0.0116 DCVDD Current (mA) 1.7660 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0000 VLINE Current (mA) 0.1530 Total Power Without VLINE, HBVDD (mW) 1075.6050 Total Power With VLINE, HBVDD (mW) 1076.1712
Class Speaker Slave 44.1k, 22µH Quiescent
SPKVDD Current (mA) 6.5820 HPVDD Current (mA) 0.0002 AVDD Current (mA) 2.2560 I2S1VDD Current (mA) 0.0114 DCVDD Current (mA) 1.7860 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) -0.0001 VLINE Current (mA) 0.1530 Total Power Without VLINE, HBVDD (mW) 42.9140 Total Power With VLINE, HBVDD (mW) 43.4802
April 2009,
WM8400
POWER STATES
Device Default, Clocks
SPKVDD Current (mA) 0.0001 HPVDD Current (mA) 0.0004 AVDD Current (mA) 0.0078 I2S1VDD Current (mA) 0.0002 DCVDD Current (mA) 0.0003 I2CVDD Current (mA) 0.0003 FLLVDD Current (mA) 0.0003 HBVDD Current (mA) 0.0003 VLINE Current (mA) 0.1512 Total Power Without VLINE, HBVDD (mW) 0.0274
Pre-Production
Total Power With VLINE, HBVDD (mW) 0.5875
Device Default, Clocks Applied
SPKVDD Current (mA) 0.0003 HPVDD Current (mA) 0.0004 AVDD Current (mA) 0.0076 I2S1VDD Current (mA) 0.0112 DCVDD Current (mA) 0.0002 I2CVDD Current (mA) 0.0001 FLLVDD Current (mA) 0.0002 HBVDD Current (mA) 0.0002 VLINE Current (mA) 0.1512 Total Power Without VLINE, HBVDD (mW) 0.0463 Total Power With VLINE, HBVDD (mW) 0.6062
CODEC Soft Shutdown (CODEC_SOFTSD Table Enabling Audio CODEC)
SPKVDD Current (mA) 0.0003 HPVDD Current (mA) 0.0003 AVDD Current (mA) 0.0075 I2S1VDD Current (mA) 0.0003 DCVDD Current (mA) -0.0001 I2CVDD Current (mA) 0.0000 FLLVDD Current (mA) 0.0000 HBVDD Current (mA) 0.0001 VLINE Current (mA) 0.1512 Total Power Without VLINE, HBVDD (mW) 0.0252 Total Power With VLINE, HBVDD (mW) 0.5848
April 2009,
Pre-Production
WM8400
TYPICAL PERFORMANCE DATA
SPEAKER DRIVER PERFORMANCE
Typical THD+N performance Speaker Driver shown below Class mode Class mode. Data provided five typical SPKVDD voltages. Load Frequency 1kHz Note that recommended operate Class mode above Class mode above 0.5W high thermal dissipation.
THD+N Output Power (Class Mode)
THD+N (dBV) Output Power (mW) 1000 1200 1400 1600 SPKVDD=5.0V SPKVDD=4.2V SPKVDD=3.9V SPKVDD=3.6V SPKVDD=3.3V
THD+N Output Power (Class Mode)
THD+N (dBV) Output Power (mW) 1000 1200 1400
SPKVDD=5.0V SPKVDD=4.2V SPKVDD=3.9V SPKVDD=3.6V SPKVDD=3.3V
1600
HEADPHONE DRIVER PERFORMANCE
Typical THD+N performance Headphone Drivers shown below single-ended configuration (LOUT ROUT) configuration (LOUT/OUT3 ROUT/OUT4). Data provided four typical HPVDD voltages, together with appropriate VSEL value. Load Frequency 1kHz
THD+N Output (Single-Ended, 32Ohm)
THD+N (dBV) -100 Output HPVDD=3.6V VSEL=11 HPVDD=3.3V VSEL=11 HPVDD=3.0V VSEL=11 HPVDD=2.7V VSEL=01
THD+N Output (BTL, 32Ohm)
THD+N (dBV) Output
DD=3.6V VSEL=11 DD=3.3V VSEL=11 DD=3.0V VSEL=11 DD=2.7V VSEL=01
April 2009,
WM8400
PSRR PERFORMANCE
PSRR performance typical audio paths illustrated graphs below.
PSRR SPKVDD
PSRR (dB) LIN2 (Class LIN2 (Class LIN2 (Class LIN2 (Class 3.3V SPKVDD 5.0V SPKVDD 3.3V SPKVDD 5.0V SPKVDD Frequency (kHz) LIN2 class AB/D
Pre-Production
PSRR HPVDD
PSRR (dB) OUT3/4 3.3V HPVDD OPMIX LOUT/ROUT 3.3V HPVDD (kHz) Various Paths
PSRR AVDD
PSRR (dB) quency (kHz) LIN2 (Class 3.3V AVDD LIN2 (Class 3.3V AVDD OPMIX/OPGA (Class 3.3V AVDD LIN2 clas AB/D
PSRR AVDD
PSRR (dB) OPMIX LOUT/ROUT 3.3V AVDD OPMIX LOUT/ROUT 3.3V AVDD (additional 10uF VMID) OPMIX LOUT/ROUT 3.3V AVDD (VMIDMODE=10) OPMIX LOUT/ROUT 3.3V AVDD (kHz) LROUT OPMIX
PSRR AVDD
PSRR (dB) OPMIX/OPGA OUT3/4 3.3V AVDD OUT3/4 3.3V AVDD Frequency OUT3/4
PSRR AVDD
PSRR (dB) IPMIX 3.3V AVDD IN1PGA IPMIX 3.3V AVDD Freque
Line-In
PSRR AVDD
PSRR (dB) IN1PGA LOP/ROP 3.3V AVDD quency
Line-In Line-Out
PSRR MICBIAS
PSRR (dB) MICBIAS MBSEL MICBIAS MBSEL Freque MBSEL=0/1
April 2009,
Pre-Production
WM8400
SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
MCLK MCLK2)
MCLKY MCLKL
MCLKH
Figure System Clock Timing Requirements
Test Conditions DCVDD=1.8V, SPKVDD=5V, GND=AGND=SPKGND=0V, TA=+25 Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK MCLK2 cycle time MCLK MCLK2 duty cycle TMCLKY TMCLKH/TMCLKL 60:40 40:60 SYMBOL CONDITIONS UNIT
April 2009,
WM8400
AUDIO INTERFACE TIMING MASTER MODE
Pre-Production
Figure Digital Audio Data Timing Master Mode (see Control Interface)
Test Conditions DCVDD=1.8V, SPKVDD=5V, GND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information ADCLRC/ DACLRC DACLRC2) propagation delay from BCLK BCLK2) falling edge ADCDAT propagation delay from BCLK falling edge DACDAT DACDAT2) setup time BCLK rising edge DACDAT DACDAT2) hold time from BCLK rising edge ADCLRC ADCLRCB delay tDDA tDST tDHT tDLRCB SYMBOL UNIT
April 2009,
Pre-Production
WM8400
AUDIO INTERFACE TIMING SLAVE MODE
Figure Digital Audio Data Timing Slave Mode
Test Conditions DCVDD=1.8V, SPKVDD=5V, GND=AGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information BCLK BCLK2) cycle time BCLK BCLK2) pulse width high BCLK BCLK2) pulse width ADCLRC/ DACLRC DACLRC2) set-up time BCLK BCLK2) rising edge ADCLRC/ DACLRC DACLRC2) hold time from BCLK BCLK2) rising edge DACDAT DACDAT2) hold time from BCLK BCLK2) rising edge ADCDAT propagation delay from BCLK falling edge DACDAT DACDAT2) set-up time BCLK BCLK2) rising edge ADCLRC ADCLRCB delay Note: BCLK BCLK2) period should always greater than equal MCLK MCLK2) period. tBCY tBCH tBCL tLRSU tLRH tDLRCB SYMBOL UNIT
April 2009,
WM8400
AUDIO INTERFACE TIMING MODE
Pre-Production
mode, important that devices attempt drive ADCDAT simultaneously. timing WM8400 ADCDAT tri-stating start data transmission described Figure table below.
Figure Digital Audio Data Timing Mode
Test Conditions SPKVDD=5V, GND=AGND=SPKGND=0V, TA=+25oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Timing Information ADCDAT setup time from BCLK falling edge ADCDAT release time from BCLK falling edge DCVDD 3.6V DCVDD 1.8V DCVDD 3.6V DCVDD 1.8V CONDITIONS UNIT
April 2009,
Pre-Production
WM8400
CONTROL INTERFACE TIMING 2-WIRE MODE
2-wire mode selected connecting MODE low.
SDIN SCLK
Figure Control Interface Timing 2-Wire Serial Control Mode
Test Conditions DCVDD=1.8V, SPKVDD=5V, GND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width spikes that will suppressed SYMBOL UNIT
April 2009,
WM8400
CONTROL INTERFACE TIMING 3-WIRE MODE
3-wire mode selected connecting MODE high.
Pre-Production
Figure Control Interface Timing 3-Wire Serial Control Mode (Write Cycle)
SCLK
SDOUT
Figure Control Interface Timing 3-Wire Serial Control Mode (Read Cycle)
Test Conditions DCVDD=1.8V, SPKVDD=5V, GND=AGND=HPGND=SPKGND=0V, TA=+25oC, Slave Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information falling edge SCLK rising edge SCLK rising edge rising edge SCLK pulse cycle time SCLK pulse width SCLK pulse width high SDIN SCLK set-up time SDIN SCLK hold time Pulse width spikes that will suppressed SCLK falling edge SDOUT transition tCSU tCHO tSCY tSCL tSCH tDSU tDHO SYMBOL UNIT
April 2009,
Pre-Production
WM8400
CODEC POWER RESET CIRCUIT
Figure Internal Power Reset Circuit Schematic
WM8400 includes internal CODEC Power-On-Reset Circuit, shown Figure which used reset CODEC digital logic into default state after power CODEC circuit powered from AVDD monitors DCVDD. asserts PORB AVDD DCVDD below minimum threshold. typical application, DCVDD supplied from integrated Regulators.
Figure Typical CODEC Power Sequence where AVDD Powered before DCVDD
Figure shows typical power-up sequence where AVDD comes first. When AVDD goes above minimum threshold, Vpora, there enough voltage circuit guarantee PORB asserted chip held reset. this condition, writes control interface ignored. After AVDD reached full supply level, DCVDD rises Vpord_on PORB released high registers their default state writes control interface take place. power down, where AVDD falls first, PORB asserted whenever AVDD drops below minimum threshold Vpora_off.
April 2009,
WM8400
Pre-Production
Figure Typical Power Sequence where DCVDD Powered before AVDD
Figure shows typical power-up sequence where DCVDD comes first. First assumed that DCVDD already specified operating voltage. When AVDD goes above minimum threshold, Vpora, there enough voltage circuit guarantee PORB asserted chip held reset. this condition, writes control interface ignored. When AVDD rises Vpora_on, PORB released high registers their default state writes control interface take place. power down, where DCVDD falls first, PORB asserted whenever DCVDD drops below minimum threshold Vpord_off. SYMBOL Vpora Vpora_on Vpora_off Vpord_on Vpord_off 1.65 0.92 UNIT
Table Typical Operation (simulated values)
Notes: AVDD DCVDD suffer brown-out (i.e. drop below minimum recommended operating level below Vpora_off Vpord_off) then chip will reset will resume normal operation when voltage back recommended level again. chip will enter reset power down when AVDD DCVDD falls below Vpora_off Vpord_off. This important supply turned frequently power management system. minimum tpor period maintained even DCVDD AVDD have zero rise time. This specification guaranteed design rather than test.
April 2009,
Pre-Production
WM8400
CONTROL INTERFACE
WM8400 controlled writing control registers. Readback available certain registers, including device power management registers some GPIO status bits. control interface operate either 2-wire 3-wire control interface, with additional variants detailed below: 2-wire open-drain 3-wire push open drain
Readback provided bi-directional SDIN 2-wire 3-wire modes.
CONTROL INTERFACE POWER DOMAIN
Operation Control Interface requires appropriate power supply connected I2CVDD power domain. This supply referenced GND. operating range this supply detailed "Recommended Operating Conditions" section. shared application with other devices, I2CVDD must supplied Wolfson device times active.
SELECTION CONTROL MODE
MODE determines 2-wire 3-wire mode shown Table MODE High INTERFACE FORMAT wire wire
Table Control Interface Mode Selection
2-WIRE SERIAL CONTROL MODE
WM8400 controlled writing registers through 2-wire serial control interface. control word consists bits. first bits (B23 B16) address bits that select which control register accessed. remaining bits (B15 data bits, corresponding bits each control register. Many devices controlled same bus, each device unique 7-bit address (this same 8-bit address each register WM8400). default device address 0011000 (0x30h) WM8400 operates slave device only. controller indicates start data transfer with high transition SDIN while SCLK remains high. This indicates that device address data will follow. devices 2-wire respond start condition shift next eight bits SDIN (7-bit address Read/Write bit, first). device address received matches address WM8400, then WM8400 responds pulling SDIN next clock pulse (ACK). address recognised when operating write only mode, WM8400 returns idle condition wait start condition valid address. WM8400 supports multitude read write operations, which are: Single write Single read Multiple write using auto-increment Multiple read using auto-increment
April 2009,
WM8400
TERMINOLOGY Table Terminology ReadNotWrite DESCRIPTION Start Condition Repeated start Acknowledge Stop Condition Write Read
Pre-Production These modes shown section below. Terminology used following figures:
Figure 2-Wire Serial Control Interface (single write)
Device
Index
Device
MSByte Data
LSByte Data
Figure 2-Wire Serial Control Interface (single read)
Figure 2-Wire Serial Control Interface (multiple write using auto-increment)
Figure 2-Wire Serial Control Interface (multiple read using auto-increment)
2-wire mode, WM8400 possible device addresses, which selected using NCSADDR pin. NCSADDR STATE High DEVICE ADDRESS 0011000 30h) 0011010 34h)
Table 2-Wire Control Interface Address Selection
April 2009,
Pre-Production
WM8400
Auto-increment mode only supported when enabled setting AUTOINC register bit. Alert Response Address protocol supported WM8400 when ARA_ENA register set. This function enables controller poll multiple devices simultaneously order respond Interrupt events efficiently. WM8400 device address used this protocol described Table
REGISTER ADDRESS (4Bh)
LABEL AUTOINC
DEFAULT
DESCRIPTION Enable Auto-Increment function (2-wire mode) Disabled Enabled Enable Alert Response Address function (2-wire mode) Disabled Enabled
ARA_ENA
Table 2-Wire Control Interface Configuration
3-WIRE SERIAL CONTROL MODE
WM8400 controlled writing registers through 3-wire serial control interface. control word consists bits. first read/write (R/W), which followed address bits that determine which control register accessed. remaining bits (B15 data bits, corresponding bits each control register. 3-wire control mode, SPI_CFG register used select between push opendrain modes, described Table below. REGISTER ADDRESS (4Bh) LABEL SPI_CFG DEFAULT DESCRIPTION 3-wire Read mode configuration CMOS output Open-drain
Table 3-Wire Control Interface Configuration
3-wire mode, every rising edge SCLK clocks data from SDIN pin. rising edge NCSADDR latches complete control word consisting last bits. Write operations (R/W=0), SDIN bits driven controlling device. Read operations (R/W=1), SDIN driven controlling device clock register address, after which WM8400 drives SDIN output applicable data bits. 3-wire control mode timing illustrated Figure
Figure 3-Wire Serial Control Interface
April 2009,
WM8400 CLOCKING SAMPLE RATES
Pre-Production
internal clocks ADCs, DACs, core functions, digital audio interface Class switching amplifier derived from common internal clock source, SYSCLK. This clock enabled register SYSCLK_ENA. Note that many analogue audio circuits WM8400 operated without SYSCLK enabled. SYSCLK either derived directly from MCLK, generated from Frequency Locked Loop (FLL) using external reference. Many commonly-used audio sample rates derived directly from typical MCLK frequencies; provides additional flexibility generate wide range SYSCLK frequencies from available external reference. alternative MCLK input selected GPIO2/MCLK2 pin. clock configurations must before enabling playback avoid glitches. sample rates independently selectable, relative SYSCLK, using ADC_CLKDIV DAC_CLKDIV. These fields must according required sampling frequency depending selected clocking mode (AIF_LRCLKRATE). master mode, BCLK also derived from SYSCLK programmable division BCLK_DIV. case where ADCs DACs operating different sample rates, BCLK must according whichever faster rate. ADCLRC DACLRC signals automatically match sample rates; these must configured using ADCLRC_RATE DACLRC_RATE described under "Digital Audio Interface Control". clock (OPCLK) derived from SYSCLK output GPIO pins provide clocking other parts system. This clock enabled OPCLK_ENA frequency OPCLKDIV. slow clock (TOCLK) derived from SYSCLK used de-bounce button/accessory detect inputs, timeout period volume updates when zero-cross detect used. This clock enabled TOCLK_ENA frequency TOCLK_RATE. Class switching amplifier requires clock; default, this derived from SYSCLK programmable divider DCLKDIV. Alternatively, Class amplifier clock derived from WM8400 internal 600kHz clock. (This clock associated with DC-DC converters.) Table Table show clocking sample rate controls MCLK input, BCLK output master mode), ADCs, DACs, class outputs GPIO clock output. overall clocking scheme WM8400 illustrated Figure
MCLK_INV MCLK_SRC SYSCLK_ENA DAC_SDMCLK_RATE
MCLK GPIO2/MCLK2
fREF ADCLRC DACLRC
FLL_CLK_SRC
fOUT
SYSCLK_SRC
MCLKDIV[1:0]
SYSCLK
DAC_CLKDIV2:0] SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK Reserved
64fs SYSCLK/4
256fs
DAC_CLKDIV [2:0]
GPIO6/ADCLRCB
MCLKDIV[1:0] MCLK Reserved MCLK Reserved
MCLK MCLK2 MCLK_SRC selects master clock source (MCLK MCLK2/GPIO2 pin) FLL_CLK_SRC selects input reference oscillator SYSCLK internal clocks derived from SYSCLK. SYSCLK derived directly from MCLK, MCLK2 from output programmable divide option (MCLKDIV). SAMPLE RATE sample rate ADC_CLKDIV (Master slave mode). RATE ADCLRC master mode derived from BCLK controlled ADCLRC_RATE. SAMPLE RATE sample rate DAC_CLKDIV (Master slave mode). RATE DACLRC master mode derived from BCLK controlled DACLRC_RATE. BCLK RATE BCLK rate BCLK_DIV master mode. When operate different sample rates master slave mode), BCLK rate should high enough support higher sample rates. OPCLK RATE GPIO Clock output frequency OPCLKDIV. CLASS SWITCHING RATE Class switching derived from internal 600kHz clock from SYSCLK. When SYSCLK selected, frequency DCLKDIV should between 700kHz 800kHz best performance. TOCLK_RATE slow clock used button/accessory detect de-bounce volume update timeouts (when zero-cross detect enabled). frequency this slow clock TOCLK_RATE. Other Sample Rate Controls DEEMP configures de-emphasis filter chosen sample rate.
ADC_CLKDIV[2:0] SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK Reserved
64fs
256fs
ADC_CLKDIV [2:0]
OPCLKDIV[3:0] 0000 SYSCLK 0001 SYSCLK 0010 SYSCLK 0011 SYSCLK 0100 SYSCLK 0101 SYSCLK 0110 SYSCLK 0111 SYSCLK 1000 SYSCLK 1001 1111 Reserved
OPCLK_ENA
GPIO Clock Output
OPCLKDIV
ADCLRCB
BCLK_DIV[3:0] 0000 SYSCLK 0001 SYSCLK 0010 SYSCLK 0011 SYSCLK 0100 SYSCLK 0101 SYSCLK 0110 SYSCLK 0111 SYSCLK 1000 SYSCLK 1001 SYSCLK 1010 SYSCLK 1011 SYSCLK 1100 SYSCLK 1101 SYSCLK 1110 SYSCLK 1111 SYSCLK
BCLKDIV [3:0]
MASTER MODE CLOCK OUTPUTS
ADCLRC DACLRC, DACLRC2 BCLK, BCLK2
DACLRC_RATE ADCLRC_RATE [10:0] [10:0]
Timeout De-Bounce Clock
TOCLK_ENA DCLKDIV[2:0] SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK
f/221 f/219
TOCLK_RATE
Button/accessory detect de-bounce, Volume update timeout
DCLKDIV
SYSCLK 600kHz Class Switching Clock
CLASSD_CLK_SEL
Figure CODEC Clocking Scheme
April 2009,
Pre-Production
WM8400
SYSCLK CONTROL
MCLK_SRC used select MCLK source. source either MCLK GPIO2/MCLK2. selected source also inverted setting register MCLK_INV. Note that recommended change control MCLK_INV while WM8400 processing data this lead clock glitches signal clicks. SYSCLK_SRC used select source SYSCLK. source either selected MCLK source output. selected source divided SYSCLK pre-divider MCLK_DIV generate SYSCLK. selected source also adjusted MCLK_DIV divider. These register fields described Table "FLL" more details Frequency Locked Loop clock generator. WM8400 supports glitch-free MCLK SYSCLK source selection. When both clock sources running MCLK_SRC SYSCLK_SRC modified select these clocks, glitch-free clock transition will take place. de-glitching circuit will ensure that minimum pulse width will less than pulse width faster clock sources. When initial clock source disabled before changing clock source, CLK_FORCE must also used force clock source transition take place. this case, glitch-free operation cannot guaranteed. SYSCLK enabled register SYSCLK_ENA. REGISTER ADDRESS (02h) LABEL SYSCLK_ENA (rw) MCLK_SRC DEFAULT DESCRIPTION SYSCLK enable disabled enabled MCLK Source Select MCLK GPIO2/MCLK2 SYSCLK Source Select MCLK MCLK2 MCLK_SRC=1) output Forces Clock Source Selection Existing SYSCLK source (MCLK, MCLK2 output) must active when changing clock source. Allows existing MCLK source disabled before changing clock source. SYSCLK Pre-divider. Clock source (MCLK, MCLK2 output) will divided this value generate SYSCLK. Divide SYSCLK Reserved Divide SYSCLK Reserved MCLK Invert Master clock (MCLK MCLK2) inverted Master clock (MCLK MCLK2) inverted
(08h)
SYSCLK_SRC
CLK_FORCE
12:11
MCLK_DIV [1:0]
MCLK_INV
Table MCLK SYSCLK Control
SAMPLE RATES
sample rates independently selectable, relative SYSCLK, setting register fields ADC_CLKDIV DAC_CLKDIV. These fields must according SYSCLK frequency, according selected clocking mode.
April 2009,
WM8400
Pre-Production clocking modes provided Normal Mode (AIF_LRCLKRATE allows selection commonly used sample rates from typical audio system clocking frequencies (eg. 12.288MHz); Mode (AIF_LRCLKRATE allows many these sample rates generated from 12MHz clock. Depending available clock sources, mode used save power supporting 44.1kHz operation without recourse FLL. AIF_LRCLKRATE field must described Table ensure correct operation internal functions according SYSCLK ratio. Table describes available sample rates using four different common MCLK frequencies. Normal mode, programmable division ADC_CLKDIV must ensure that clock generated DSP. DAC_CLKDIV must ensure that clock generated DSP. mode, programmable division ADC_CLKDIV must ensure that clock generated DSP. DAC_CLKDIV must ensure that clock generated DSP. Note that mode, sample rates match exactly with commonly used sample rates (e.g. 44.118 instead 44.100 kHz). most, difference less than 0.5%. Data recorded 44.100 sample rate replayed 44.118 will experience slight (sub 0.5%) pitch shift result this difference. Note also that mode cannot used generate 48kHz samples rate from 12MHz MCLK; should used this case. sample rate modes (eg. 8kHz voice), liable degraded typical 64fs clocking rate used (see Figure 17). this case, possible improve raising clocking rate setting DAC_SDMCLK_RATE register field, causing clocking rate equal SYSCLK/4. DAC_CLKDIV field must still described above derive correct clock DSP. 8kHz voice applications, systems where SYSCLK 256fs 272fs when applicable), setting DAC_SDMCLK_RATE will result performance being improved. Note that setting DAC_SDMCLK_RATE will result increase power consumption. REGISTER ADDRESS (08h) LABEL ADC_CLKDIV [2:0] DEFAULT 000b DESCRIPTION Sample Rate Divider SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK 111= Reserved Sample Rate Divider SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK 111= Reserved clocking rate Normal operation (64fs) SYSCLK/4 LRCLK Rate Normal mode (256 mode (272
DAC_CLKDIV [2:0]
000b
(0Bh)
DAC_SDMCLK_ RATE AIF_LRCLKRATE
Table Sample Rate Control
April 2009,
Pre-Production
WM8400
SYSCLK SAMPLE RATE DIVIDER SYSCLK SYSCLK SYSCLK 12.288 SYSCLK SYSCLK SYSCLK SYSCLK Reserved SYSCLK SYSCLK SYSCLK 11.2896 SYSCLK SYSCLK SYSCLK SYSCLK Reserved SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK Reserved SYSCLK SYSCLK SYSCLK 2.048 SYSCLK SYSCLK SYSCLK SYSCLK Reserved Table Sample Rates Normal Mode (256 Mode (272 Normal Mode (256 Normal Mode (256 CLOCKING MODE SAMPLE RATE used Reserved 44.1 used 22.05 used 11.025 8.018 used Reserved 44.118 used 22.059 used 11.029 8.021 used Reserved used used used used used used Reserved
April 2009,
WM8400
BCLK CONTROL
Pre-Production
Master Mode, BCLK derived from SYSCLK programmable division BCLK_DIV, described Table BCLK_DIV must appropriate value ensure that there sufficient BCLK cycles transfer complete data words from ADCs DACs. Slave Mode, BCLK generated externally appears input CODEC. host device must provide sufficient BCLK cycles transfer complete data words ADCs DACs. Note that, although different sample rates, they will normally share same clock BCLK. case where different sample rates used, BCLK frequency should according higher rates. Note that possible independent clocks when using Dual Audio Interface capability "Digital Audio Interface". REGISTER ADDRESS (07h) LABEL BCLK_DIV [3:0] DEFAULT 0100b DESCRIPTION BCLK Frequency (Master Mode) 0000 SYSCLK 0001 SYSCLK 0010 SYSCLK 0011 SYSCLK 0100 SYSCLK 0101 SYSCLK 0110 SYSCLK 0111 SYSCLK 1000 SYSCLK 1001 SYSCLK 1010 SYSCLK 1011 SYSCLK 1100 SYSCLK 1101 SYSCLK 1110 SYSCLK 1111 SYSCL:K
Table BCLK Control
OPCLK CONTROL
clock output (OPCLK) derived from SYSCLK output GPIO1 GPIO6. This clock enabled register OPCLK_ENA, frequency controlled OPCLKDIV. This output this clock also dependent upon GPIO register settings described under "General Purpose Input/Output". REGISTER ADDRESS (07h) 12:9 LABEL OPCLKDIV [3:0] DEFAULT 0000b DESCRIPTION GPIO Output Clock Divider 0000 SYSCLK 0001 SYSCLK 0010 SYSCLK 0011 SYSCLK 0100 SYSCLK 0101 SYSCLK 0110 SYSCLK 0111 SYSCLK 1000 SYSCLK 1001 1111 Reserved GPIO Clock Output Enable disabled enabled
(03h)
OPCLK_ENA (rw)
Table OPCLK Control
April 2009,
Pre-Production
WM8400
CLASS SWITCHING CLOCK
Class switching clock derived either from SYSCLK directly from WM8400 internal 600kHz oscillator. source selected CLASSD_CLK_SEL. When SYSCLK used Class clock source, clock rate determined register field DCLKDIV described Table This clock should between 700kHz 800kHz optimum performance. class switching clock should disabled when speaker output active, this will prevent speaker outputs from functioning. class switching clock frequency should altered while speaker output active this generate audible click. REGISTER ADDRESS (07h) LABEL DCLKDIV [2:0] DEFAULT 111b DESCRIPTION Class Clock Divider SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK SYSCLK Class Clock Source Derived from SYSCLK (via DCLKDIV) 600kHz oscillator
(23h)
CLASSD_CLK_
Table DCLK Control
TOCLK CONTROL
slow clock (TOCLK) derived from SYSCLK enable input de-bouncing volume update timeout functions. This clock enabled register TOCLK_ENA, frequency controlled TOCLK_RATE, described Table REGISTER ADDRESS (07h) LABEL TOCLK_RATE DEFAULT DESCRIPTION Timeout Clock Rate (Selects clock used volume update timeout GPIO input debounce) SYSCLK (Slower Response) SYSCLK (Faster Response) Timeout Clock Enable (This clock required volume update timeout GPIO input de-bounce) disabled enabled
TOCLK_ENA
Table TOCLK Control
April 2009,
WM8400
MODE
Pre-Production
possible reduce power consumption WM8400 disabling some applications. such application when SYSCLK generated from 12MHz clock source. Setting AIF_LRCLKRATE described earlier (see "ADC Sample Rates") allows approximate sample rate close 44.1kHz generated with additional power consumption. this configuration, SYSCLK must driven directly from MCLK MCLK2) disabling FLL. This achieved setting SYSCLK_SRC=0, FLL_ENA=0 FLL_OSC_ENA=0. REGISTER ADDRESS (0Bh) LABEL AIF_LRCLKRATE DEFAULT DESCRIPTION LRCLK Rate Normal mode (256 mode (272
Table Mode Control
FREQUENCY LOCKED LOOP (FLL)
integrated used generate SYSCLK from wide variety different reference sources frequencies. either MCLK DACLRC input reference, which high frequency (eg. 12.288MHz) frequency (eg. 32,768kHz) reference. tolerant jitter used generate stable SYSCLK from less stable input signal. characteristics summarised "Electrical Characteristics". analogue digital portions enabled independently FLL_OSC_ENA FLL_ENA. When initialising FLL, analogue circuit must enabled first setting FLL_OSC_ENA. digital circuit then enabled next register write later. When changing settings, recommended that digital circuit disabled FLL_ENA then re-enabled after other register settings have been updated. When changing input reference frequency FREF, recommended that reset setting FLL_ENA field FLL_CTRL_RATE controls internal functions within FLL; recommended that only default setting used this parameter. FLL_TRK_GAIN controls internal loop gain should recommended value. output frequency directly determined from FLL_FRATIO, FLL_OUTDIV real number represented FLL_N FLL_K. field FLL_N integer (LSB FLL_K fractional portion number (MSB 0.5). fractional portion only valid when enabled field FLL_FRAC. recommended that FLL_FRAC enabled times. frequency determined according following equation: FOUT (FVCO FLL_OUTDIV) FVCO (FREF FLL_FRATIO)
FVCO must range 90-100 MHz. value FLL_OUTDIV should selected follows according desired output FOUT. OUTPUT FREQUENCY FOUT 2.8125 3.125 5.625 6.25 11.25 12.5 22.5 Table Choice FLL_OUTDIV FLL_OUTDIV (divide (divide (divide (divide
Note that output frequencies that within ranges quoted above cannot guaranteed across full range device operating temperatures.
April 2009,
Pre-Production
WM8400
Once FVCO been determined, value FLL_FRATIO should selected accordance with recommendations Table value then determined using equation above. FLL_REF_FREQ should described Table best performance, Fractional Mode should always used. Therefore, calculations yield integer value N.K, then recommended adjust FLL_FRATIO order obtain noninteger value N.K. also recommended best audio performance, that high input clocks frequencies (above 1MHz), used. register fields that control described Table Example settings variety reference frequencies output frequencies shown Table REGISTER ADDRESS (03h) Power Management LABEL FLL_ENA DEFAULT DESCRIPTION Digital enable disabled enabled FLL_OSC_ENA must enabled before enabling FLL_ENA. order important. (3Ch) Control FLL_REF_FREQ frequency reference locking Lock achieved after clks (Recommended Reference clock 48kHz) Lock achieved after clks (Recommended Reference clock 48kHz) Clock source MCLK LRCLK LRCLK GPIO6 Fractional enable Integer Mode Fractional Mode recommended cases FLL_OSC_ENA Analogue enable disabled enabled FLL_OSC_ENA must enabled before enabling FLL_ENA. order important. FLL_CTRL_RAT [2:0] Frequency control block FVCO (Recommended value) FVCO FVCO FVCO FVCO FVCO Recommended that these changed from default. FLL_FRATIO [4:0] CLK_VCO divided this integer, valid from recommended high freq reference recommended freq reference Fractional multiply CLK_REF April 2009,
11:10
FLL_CLK_SRC [1:0]
FLL_FRAC
(3Dh) Control
15:0
FLL_K[15:0]
WM8400
REGISTER ADDRESS (3Eh) Control (3Fh) Control LABEL FLL_N[9:0] FLL_TRK_GAIN [3:0] DEFAULT
Pre-Production DESCRIPTION Integer multiply CLK_REF Gain applied error 0000 (Recommended value) 0001 0010 0011 0100 0101 0110 0111 1000 Recommended that these changed from default. FLL_OUTDIV [2:0] FOUT clock divider FVCO FVCO FVCO (best performance) FVCO FVCO Reserved Reserved Reserved
Table Register
POWER DOMAIN
Operation requires appropriate power supply connected FLLVDD power domain. This supply referenced AGND. operating range this supply detailed "Recommended Operating Conditions" section.
EXAMPLE CALCULATION
generate 12.288 output (FOUT) from 12.000 reference clock (FREF): Determine FLL_OUTDIV required output frequency given Table 15:For FOUT 12.288 MHz, FLL_OUTDIV (divide Calculate FVCO given FLL_OUTDIV:FVCO FOUT FLL_OUTDIV 12.288 98.304 Calculate required FLL_FRATIO given FREF FVCO.:N.K FLL_FRATIO FVCO FREF 8.192 Determine FLL_REF_FREQ given FREF given Table 16:For FREF 12MHz, FLL_REF_FREQ Determine FLL_FRATIO given Table 16:For High Frequency Reference, FLL_FRATIO Calculate given FLL_FRATIO:N.K 8.192 8.192 Determine FLL_N FLL_K from integer fractional portions N.K:FLL_N FLL_K 0.192 FLL_FRAC according whether fractional mode required:FLL_K 0.192, fractional mode required; FLL_FRAC April 2009,
Pre-Production
WM8400
EXAMPLE SETTINGS
Table provides example settings generating common SYSCLK frequencies from variety high frequency reference inputs.
FREF 32.000 32.000 32.768 32.768 32.768 11.3636 12.000 12.000 12.288 12.288 13.000 13.000 19.200 19.200
FOUT 12.288 11.2896 12.288 11.288576 11.2896 12.288 12.368544 12.288 11.289597 12.288 11.2896 12.287990 11.289606 12.287988 11.289588
FVCO 98.304 90.3168 98.304 90.308608 90.3168 98.304 98.948354 98.3040 90.3168 98.304 90.3168 98.3040 90.3168 98.3040 90.3168
FLL_N (1B6h) (160h) (1ACh) (158h) (158h) (124h) (008h) (008h) (007h) (002h) (007h) (007h) (006h) (005h) (004h)
FLL_K 0.857143 (DB6Eh) (CCCCh) 0.571429 (9249 0.500000 (8000 0.53125 (8800h) 0.571429 (9249 0.707483 (B51Dh) 0.192 (3127h) 0.526398 (86C2h) 0.666667 (AAABh) 0.35 (599Ah) 0.56184 (8FD5h) 0.94745 (F28Ch) 0.119995 (1EB8h) 0.703995 (B439h)
FLL_ FRATIO
FLL_OUTDIV (divide (divide (divide (divide (divide (divide (divide (divide (divide (divide (divide (divide (divide (divide (divide
FLL_ FRAC
FLL_REF_ FREQ
Table Example Settings
April 2009,
WM8400 AUDIO CODEC SUBSYSTEM
INTRODUCTION
Pre-Production
WM8400 incorporates power, high quality audio CODEC which designed interface with wide range processors analogue components. Eight highly flexible analogue inputs allow interfacing four microphone inputs plus multiple stereo mono line inputs (single-ended differential). Connections external voice CODEC, radio, melody line input, handset headset fully supported. Signal routing output mixers within CODEC been designed maximum flexibility support wide variety usage modes. analogue output drivers integrated, including high power, high quality speaker driver, capable providing class mode 0.5W class mode into BTL. Four headphone drivers provided, supporting speakers stereo headsets. Fully differential headphone drive supported excellent crosstalk performance removing need large expensive headphone capacitors. Four line outputs available voice output voice CODEC, interfacing additional speaker driver single-ended fully differential line output. outputs have integrated click suppression. speaker supply been designed with leakage high PSRR, support direct connection Lithium battery. gain settings allow output signal levels maximised number AVDD SPKVDD combinations. Internal signal routing amplifier configurations have been optimised provide lowest possible power consumption number common usage scenarios such voice calls music playback. stereo ADCs DACs hi-fi quality using 24-bit, low-order oversampling architecture deliver optimum performance. flexible clocking arrangement supports mixed sample rates, while integrated ultra-low power provides additional flexibility. high pass filter available path removing offsets suppressing frequency noise such mechanical vibration wind noise. digital mixing path from provides sidetone enhanced quality during voice calls. Pop-free soft mute un-mute available. WM8400 highly flexible digital audio interface, supporting number protocols, including I2S, DSP, MSB-First left/right justified, operate master slave modes. operation supported mode. A-law µ-law companding also supported. Time division multiplexing (TDM) available allow multiple devices stream data simultaneously same bus, saving space power. Alternative interface pins provided allow connection additional processor. SYSCLK (system clock) provides clocking ADCs, DACs, core, class outputs digital audio interface. SYSCLK derived directly from MCLK integrated FLL, providing flexibility support wide range clocking schemes. MCLK frequencies typically used portable systems supported sample rates between 8kHz 48kHz. switching clock class speaker drivers derived from SYSCLK else provided oscillator within WM8400. (Best speaker driver performance achieved when this clock synchronous with audio clocks.) additional master clock input provided, support operation alternative clock domain, selectable de-glitch circuit. Versatile GPIO functionality provided, with support seven button/accessory detect inputs with interrupt status readback flexible de-bouncing options, clock output, alternative MCLK input, ADCLRC inversion simultaneous streaming data separate processors logic logic control additional external circuitry. Unused circuit blocks within CODEC disabled software save power, while leakage currents extend standby time portable battery-powered applications.
April 2009,
LONMUTE LROPGALON LLOPGALON LOPMUTE LR12LOP LL12LOP LOATTN
VMID 0/-6dB
Left Differential Line
LON_ENA
Pre-Production
LOPLON
LLOPGALOP LDBVOL[2:0]
-12dB +6dB VMID
LIN12VOL[4:0] LL4BVOL[2:0]
-12dB +6dB
LOP_ENA OUT3MUTE LI4O3 LOPGAVOL[6:0]
+6dB
LINPUT1
LR12LOVOL[2:0] -21dB LR12LO L12MNBST
+30dB Pass MUTE
-16.5dB +30dB
DIS_LLINE
LIN12MUTE
Left Output Mixer
LPGAO3 OUT3_ENA DIS_OUT3 LOUTVOL[6:0]
+6dB VMID 0/-6dB
LMN1 L12MNB LL12LOVOL[2:0] -21dB LL12LO LLI3LOVOL[2:0] -21dB LLI3LO LOPGA_ENA LRBLOVOL[2:0] -21dB LRBLO LOMIX_ENA Pass VMID VMID
LIN12VOL[4:0] LI2BVOL[2:0]
-12dB +6dB
OUT3ATTN
OUT3 Class Headphone Driver OUT3
-16.5dB +30dB
LMP2
AUDIO SIGNAL PATHS
LINPUT2
L34MNBST +30dB L34MNB LDLO AINL_ENA LLBLOVOL[2:0] -21dB LLBLO
LMP2
LIN12_ENA
Left Boost Diff_2_single
BVMID
VMID
Left Line
LIN34VOL[4:0]
VMID
ADCL_ENA ADCHPD DACL_ENA LI2SPK LB2SPK DACL_VOL[7:0] LDSPK LOPGASPK ROPGASPK DAC_MONO RI2SPK ADCR_DAC_ SVOL[3:0] DACR_VOL[7:0] RLI3ROVOL[2:0] -21dB RLI3RO
Pass 0/-6dB/-12dB VMID
Figure WM8400 Audio Signal Paths
HIGH PASS FILTER (3Hz 300Hz)
LINPUT3
LR4BVOL[2:0]
-12dB +6dB
-16.5dB +30dB
LIN34MUTE AINLMODE[1:0] ADCL_VOL[7:0] LRI3LOVOL[2:0] -21dB LRI3RO SPKVOL[1:0]
Single Ended Mixer Diff with gain (Linput4 Rinput4) Diff Single Ended convertor (Balanced line Input Input
Left Class Headphone Driver
LOUT_ENA DIS_LOUT
LMN3
LIN34VOL[4:0] ADC_TO_DACL[1:0]
-16.5dB +30dB
LMP4
LINPUT4
RDBVOL[2:0]
-12dB +6dB BVMID
LMP4 ADCL_DAC_ SVOL[3:0] RDSPK
LIN34_ENA
BVMID
VMID
Left Line
RIN12VOL[4:0] RL4BVOL[2:0]
-12dB +6dB
SPK_ENA CDMODE SPKOPEN_P SPKOPEN_N SPK_ANTIPOP_EN
RINPUT1
-16.5dB +30dB
ClassD
SPK_P SPK_N
ClassAB
RIN12MUTE
RMN1 ADC_TO_DACR[1:0]
RB2SPK VMID SPK_MIX_ENA
SYSCLK Derived RCOSC Derived
RIN12VOL[4:0] RI2BVOL[2:0]
-12dB +6dB
R12MNBST +30dB R12MNB
-16.5dB +30dB
RMP2
Mono Class AB/D Speaker Driver
CLASSD_CLK_SEL VMID
RINPUT2
RLBROVOL[2:0] -21dB RLBRO ADCR_VOL[7:0] RDRO RRBROVOL[2:0] -21dB RRBRO
VMID
RMP2
RIN12_ENA
Right Boost Diff_2_single
BVMID
VMID
Left Line
R34MNBST +30dB R34MNB AINR_ENA
VMID
ROUTVOL[6:0]
+6dB
RIN34VOL[4:0] RR4BVOL[2:0]
-12dB +6dB
ADCR_ENA ADCHPD DACR_ENA ROMIX_ENA
RINPUT3
AINRMODE[1:0]
-16.5dB +30dB
HIGH PASS FILTER (3Hz 300Hz)
RIN34MUTE
VMID
Right Class Headphone Driver ROUT
ROUT_ENA OUT4MUTE RI4O4
0/-6dB
RMN3 RRI3ROVOL[2:0] -21dB RRI3RO DAC_BOOST[1:0] DACL_DATINV DACR_DATINV RL12ROVOL[2:0] -21dB RL12RO
Single Ended Mixer Diff with gain (Linput4 Rinput4) Diff Single Ended convertor (Balanced line Input Input
RIN34VOL[4:0] RR12ROVOL[2:0] -21dB RR12RO
-16.5dB +30dB
RMP4
RINPUT4
BVMID
RMP4 ADCL_DATINV ADCR_DATINV
Right Output Mixer
RIN34_ENA
DIS_LOUT
BVMID
VMID
Left Line
ROPGAVOL[6:0]
+6dB MUTE
RPGAO4
OUT4ATTN
VMID
OUT4 Class Headphone Driver OUT4
OUT4_ENA ROPGA_ENA
VMID
VMID_MODE[1:0]
AVDD Bias main Analgue Circuits Bias Outputs A-law u-law support Support
ROPMUTE RROPGAROP RL12ROP RR12ROP ROATTN
VMID 0/-6dB
DIS_OUT4
S-CURVE
DIGITAL AUDIO INTERFACE
ADC_COMP ADC_COMPMODE AIFADCL_SRC AIFADCR_SRC AIFADC_TDM_CHAN AIFADC_TDM
DAC_COMP DAC_COMPMODE AIFDACL_SRC AIFDACR_SRC AIFDAC_TDM_CHAN AIFDAC_TDM
DIS_RLINE
VMID POB_CTRL
VMID
VREF_ENA SOFTSLEEPEN QUATERBIASEN MSTRBIAS[1:0]
SOFTST FASTST VMIDTOG MAIN VMID/R BIAS bias
RONMUTE ROP_ENA ROPRON RLOPGARON RROPGARON
AGND INPUT VMID OUTPUT
VREF_ENA
MICBIAS
VMID
MBVSEL
FASTBIAS (VGS/R) BIAS
RON_ENA
VMID
MICBIAS_ENA
enable
BUFIOEN
Right Differential Line
AVDD
AGND
DGND
DCVDD
FLLVDD
I2S2VDD
I2S1VDD
GPIO3/BCLK2
GPIO2/MCLK2
DACDAT DACLRC ADCDAT ADCLRC/GPIO1 BCLK MCLK
GPIO4/DACDAT2
GPIO6 GPIO5/DACLRC2
April 2009,
WM8400
WM8400
ENABLING AUDIO CODEC
AUDIO CODEC POWER DOMAINS
Pre-Production
Operation audio CODEC requires appropriate power supplies connected associated power domains. CODEC power supplies derived from WM8400's integrated Regulators, then "Power Management Subsystem" further details these Regulators configured.) analogue input circuits CODEC powered AVDD domain. Line Outputs LOP, LON, ROP, also powered AVDD. digital CODEC circuits powered DCVDD domain. supplies AVDD DCVDD both referenced AGND. headphone outputs LOUT, ROUT, OUT3 OUT4 powered HPVDD domain (referenced HPGND). speaker outputs SPKP SPKN power SPKVDD domain (referenced SPKGND). operating ranges these supplies detailed "Recommended Operating Conditions" section.
ENABLING AUDIO CODEC
Before audio CODEC used, must enabled writing CODEC_ENA register bit. When this logic `0', CODEC registers held their default states. Setting this logic used reset CODEC registers their default values. CODEC also enabled writing logic CODEC_SOFTST register bit. Setting this will trigger pop-suppressed start-up sequence. part this sequence, CODEC_ENA will become automatically. CODEC disabled writing logic CODEC_SOFTSD register bit. Setting this will trigger pop-suppressed CODEC shut-down sequence. part this sequence, CODEC_ENA will reset logic `0'. Note that, when WM8400 Deep Sleep mode (see "Power Management Subsystem"), CODEC will disabled, CODEC_ENA will logic `0'. Therefore, exit from Deep Sleep mode, previous CODEC settings will lost. REGISTER ADDRESS (02h) LABEL DEFAULT
CODEC_ENA (rw) CODEC_SOFT CODEC_SOFT
Master CODEC enable bit. CODEC registers held reset CODEC registers operate normally CODEC Soft Start Sequence Disabled Enabled CODEC Soft Shutdown Sequence Disabled Enabled
(4Ch)
Table Enabling Audio CODEC
April 2009,
Pre-Production
WM8400
INPUT SIGNAL PATH
WM8400 eight highly flexible analogue input channels, configurable many combinations following: four pseudo-differential single-ended microphone inputs eight mono line inputs stereo line inputs Mono input from external voice CODEC fully balanced differential inputs These inputs mixed together independently routed different combinations output drivers. internal record path provided input mixers allow output mixed with input signal path (e.g. karaoke voice call recording). WM8400 input signal paths control registers illustrated Figure
Figure Control Registers Input Signal Path
April 2009,
WM8400
MICROPHONE INPUTS
Pre-Production
four microphones connected WM8400, either single-ended pseudodifferential mode. noise microphone bias fully integrated reduce need external components. single-ended microphone input configuration, microphone signal connected inverting input (LIN1, LIN3, RIN1 RIN3). non-inverting input PGAs should internally connected VMID this configuration. This enabled Input configuration register settings. this configuration, LIN2, LIN4, RIN2 RIN4 free used line inputs bypass inputs. pseudo-differential microphone input configuration, non-inverted microphone signal connected non-inverting input (LIN2, LIN4, RIN2 RIN4) inverted noisy ground) signal connected inverting input (LIN1, LIN3, RIN1 RIN3). input that used either microphone configuration should enabled line input path same time. gain input PGAs controlled register settings. Note that input impedance LIN1, LIN3, RIN1 RIN3 changes with input gain setting, described under "Electrical Characteristics". (Note this does apply input paths which bypass input PGA.) input impedance LIN2, LIN4, RIN2 RIN4 does change with input gain. inverting non-inverting inputs therefore matched differential configuration fully differential.
Figure Single-Ended Microphone Input
Figure Differential Microphone Input
April 2009,
Pre-Production
WM8400
LINE INPUTS
eight analogue input pins configured line inputs. Various signal paths exist provide flexibility, high performance power consumption different usage modes. LIN1 RIN1 operate line inputs Input PGAs LIN12 RIN12 provide high gain required small input signals. LIN2 RIN2 operate line inputs directly input mixers speaker output mixer. Direct routing speaker output minimises power consumption reducing number active amplifiers signal path. LIN3 RIN3 operate line inputs Input PGAs line input directly either output mixers LOMIX ROMIX. LIN1+LIN3 RIN1+RIN3 also used fully balanced differential inputs Input PGAs input mixers. (Note that these inputs have matched input impedances.) LIN4/RXN RIN4/RXP operate line inputs directly outputs OUT3 OUT4, providing ultra-low power stereo mono differential signal path (e.g. from external voice CODEC) speaker. LIN4/RXN RIN4/RXP also operate mono differential input input signal path output mixer stages.
Figure LIN1 RIN1 Line Inputs
Figure LIN2 RIN2 Line Inputs
Figure LIN3 RIN3 Line Inputs
Figure Fully Balanced Differential Input
April 2009,
WM8400
Pre-Production
Figure LIN4 RIN4 Voice Inputs with Direct Power Path Speaker
Figure LIN4 RIN4 Line Inputs
INPUT ENABLE
Input PGAs enabled using register bits LIN12_ENA, LIN34_ENA, RIN12_ENA RIN34_ENA described Table REGISTER ADDRESS (03h) LABEL DEFAULT
LIN34_ENA (rw) LIN12_ENA (rw) RIN34_ENA (rw) RIN12_ENA (rw)
LIN34 Input Enable disabled enabled LIN12 Input Enable disabled enabled RIN34 Input Enable disabled enabled RIN12 Input Enable disabled enabled
Table Input Enable
April 2009,
Pre-Production
WM8400
REFERENCE VOLTAGES
internal analogue input output circuitry requires reference voltage AVDD/2 (VMID). This voltage generated internally using 6.8k, 300k (+/- 15%) resistors buffered required. These functions controlled using register bits VMID_MODE VREF_ENA. REGISTER ADDRESS (02h) LABEL VMID_MODE [1:0] (rw) DEFAULT DESCRIPTION VMID Divider Enable Select VMID disabled (for mode) divider (Normal mode) 300k divider (Standby mode) 6.8k divider (for fast start-up) VREF Enable (Bias analogue functions) VREF bias disabled VREF bias enabled
VREF_ENA (rw)
Table Reference Voltages
MICROPHONE BIAS CONTROL
MICBIAS output provides noise reference voltage suitable biasing electret type microphones external resistor. Refer Applications Information section recommended external components. MICBIAS voltage enabled disabled using MIC1BIAS_ENA control voltage selected using MBSEL register detailed Table REGISTER ADDRESS (02h) LABEL MIC1BIAS_ENA (rw) MBSEL DEFAULT DESCRIPTION Microphone Bias (high impedance output) Microphone Bias Voltage Control AVDD 0.65 AVDD
(3Ah)
Table Microphone Bias Control
Note that maximum source current capability MICBIAS 3mA. external biasing resistance must large enough limit MICBIAS current 3mA.
MICROPHONE CURRENT DETECT
MICBIAS current detect function allows detection accessories such headset microphones. When MICBIAS load current exceeds programmable thresholds, (e.g. short circuit current normal operating current), interrupt GPIO output generated. current detection circuit enabled bit; current thresholds selected MCDTHR MCDSCTH register fields described Table "General Purpose Input/Output" full description these fields. Note that MICBIAS current thresholds subject wide tolerance +/-50% specified value.
April 2009,
WM8400
INPUT CONFIGURATION
Pre-Production
Each four Input PGAs configured single-ended pseudo-differential mode. Single-ended microphone operation Input selected connecting input source inverting input. non-inverting input must connected VMID setting appropriate register bits. pseudo-differential microphone operation, inverting non-inverting inputs both connected input source VMID. line input other connection using Input PGA, appropriate input should disconnected from external connected VMID. Register bits LMN1, LMP2, LMN3, LMP4, RMN1, RMP2, RMN3 RMP4 control connection inputs device pins shown Table maximum available attenuation these input paths achieved using these bits disable input path applicable PGA. When enabled analogue inputs General Purpose inputs, input pins biased VMID resistor. REGISTER ADDRESS (28h) LABEL LMP4 DEFAULT DESCRIPTION LIN34 Non-Inverting Input Select LIN4 connected LIN4 connected LIN34 Inverting Input Select LIN3 connected LIN3 connected LIN12 Non-Inverting Input Select LIN2 connected LIN2 connected LIN12 Inverting Input Select LIN1 connected LIN1 connected RIN34 Non-Inverting Input Select RIN4 connected RIN4 connected RIN34 Inverting Input Select RIN3 connected RIN3 connected RIN12 Non-Inverting Input Select RIN2 connected RIN2 connected RIN12 Inverting Input Select RIN1 connected RIN1 connected
LMN3
LMP2
LMN1
RMP4
RMN3
RMP2
RMN1
Table Input Configuration
April 2009,
Pre-Production
WM8400
INPUT VOLUME CONTROL
Each four Input PGAs independently controlled gain range -16.5dB +30dB 1.5dB steps. gains inverting non-inverting inputs PGAs always equal. Each Input independently muted using Mute bits described Table Maximum mute attenuation achieved simultaneously disconnecting corresponding inputs, described Table prevent "zipper noise", zero-cross function provided, that when enabled, volume updates will take place until zero-crossing detected. event long period without zerocrossings, timeout function available. When this function enabled (using TOCLK_ENA register bit), volume will update after timeout period earlier zero-cross occurred. timeout period TOCLK_RATE. "Clocking Sample Rates" more information these fields. IPVU controls loading input volume data. When IPVU volume data will loaded into respective control register, will actually change gain setting. LIN12, RIN12, LIN34, RIN34 volume settings updated when written IPVU. This makes possible update gain input paths simultaneously. Input Volume Control register fields described Table Table
April 2009,
WM8400
REGISTER ADDRESS (18h) LABEL IPVU[0] DEFAULT
Pre-Production DESCRIPTION Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) LIN12 Mute Disable Mute Enable Mute LIN12 Zero Cross Detector Change gain immediately Change gain zero cross only LIN12 Volume (See Table volume range) Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) LIN34 Mute Disable Mute Enable Mute LIN34 Zero Cross Detector Change gain immediately Change gain zero cross only LIN34 Volume (See Table volume range) Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) RIN12 Mute Disable Mute Enable Mute RIN12 Zero Cross Detector Change gain immediately Change gain zero cross only RIN12 Volume (See Table volume range) Input Volume Update Writing this will cause input volumes updated simultaneously (LIN12, LIN34, RIN12 RIN34) RIN34 Mute Disable Mute Enable Mute RIN34 Zero Cross Detector Change gain immediately Change gain zero cross only RIN34 Volume (See Table volume range)
LI12MUTE
LI12ZC
(19h)
LIN12VOL [4:0] IPVU[1]
01011b (0dB)
LI34MUTE
LI34ZC
(1Ah)
LIN34VOL [4:0] IPVU[2]
01011b (0dB)
RI12MUTE
RI12ZC
(1Bh)
RIN12VOL [4:0] IPVU[3]
01011b (0dB)
RI34MUTE
RI34ZC
RIN34VOL [4:0]
01011b (0dB)
Table Input Volume Control
April 2009,
Pre-Production
WM8400
LIN12VOL[4:0], LIN34VOL[4:0], RIN12VOL[4:0], RIN34VOL[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Table Input Volume Range VOLUME (dB) -16.5 -15.0 -13.5 -12.0 -10.5 -9.0 -7.5 -6.0 -4.5 -3.0 -1.5 +1.5 +3.0 +4.5 +6.0 +7.5 +9.0 +10.5 +12.0 +13.5 +15.0 +16.5 +18.0 +19.5 +21.0 +22.5 +24.0 +25.5 +27.0 +28.5 +30.0
April 2009,
WM8400
INPUT MIXER ENABLE
Pre-Production
WM8400 analogue input mixers which allow Input PGAs Line Inputs combined number ways output ADCs Output Mixers bypass paths. input mixers INMIXL INMIXR enabled AINL_ENA AINR_ENA register bits, described Table These control bits also enable Input Multiplexers Differential Input drivers, described following section. REGISTER ADDRESS (03h) LABEL AINL_ENA (rw) DEFAULT DESCRIPTION Left Input Path Enable (Enables AINLMUX, INMIXL, DIFFINL RXVOICE input AINLMUX) Input Path disabled Input Path enabled Right Input Path Enable (Enables AINRMUX, INMIXR, DIFFINR RXVOICE input AINRMUX) Input Path disabled Input Path enabled
AINR_ENA (rw)
Table Input Mixer Enable
INPUT MIXER CONFIGURATION
left right channel input multiplexers AINLMUX AINRMUX select three input sources Left Right channels independently. three input sources follows: INMIXL INMIXR output combination Input PGAs, line inputs internal record path). RXVOICE differential single-ended conversion LIN4/RXN RIN4/RXP inputs). DIFFINL DIFFINR output differential single-ended conversion Input PGAs). input source multiplexers controlled register bits AINLMODE AINRMODE described Table REGISTER ADDRESS (27h) LABEL AINLMODE [1:0] DEFAULT DESCRIPTION AINLMUX Input Source INMIXL (Left Input Mixer) RXVOICE (RXP RXN) DIFFINL (LIN12 LIN34 PGA) (Reserved) AINRMUX Input Source INMIXR (Right Input Mixer) RXVOICE (RXP RXN) DIFFINR (RIN12 RIN34 PGA) (Reserved)
AINRMODE [1:0]
Table Input Mixer Configuration
Input Mixer configuration described each three modes following sections. Note that Left Right multiplexer (mode) settings independently.
April 2009,
Pre-Production
WM8400
Mixer Mode (AINLMODE=00, AINRMODE=00), adjustable gain control available input mixers INMIXL INMIXR available input signals (PGA outputs, line inputs record paths). This configuration illustrated Figure applicable register settings shown Table CONFIGURATION Left Channel Mixer Mode (INMIXL AINLMUX) Select Mixer Mode Enable input paths required (see Table Table full definitions applicable settings listed here) Right Channel Mixer Mode (INMIXR AINRMUX) Select Mixer Mode Enable input paths required (see Table Table full definitions applicable settings listed here) REGISTER SETTINGS AINLMODE L12MNB, L12MNBST LIN12VOL, LIN12MUTE L34MNB, L34MNBST LIN34VOL, LIN34MUTE LDBVOL LI2BVOL AINRMODE R12MNB, R12MNBST RIN12VOL, RIN12MUTE R34MNB, R34MNBST RIN34VOL, RIN34MUTE RDBVOL RI2BVOL
Table Mixer Mode Register Settings
Figure Mixer Mode Signal Paths
April 2009,
WM8400
Pre-Production Voice Mode (AINLMODE=01, AINRMODE=01), adjustable gain control available RXVOICE output LR4BVOL[2:0] LL4BVOL[2:0] register fields left channel RL4BVOL[2:0] RR4BVOL[2:0] right channel. Both Volume fields desired channel(s) must same value true Differential input characteristics. This configuration illustrated Figure applicable register settings shown Table CONFIGURATION Left Channel Voice Mode (RXVOICE AINLMUX) REGISTER SETTINGS Select Voice Mode Enable Voice input required Important: These register fields must same value. Table full definitions these fields. Select Voice Mode Enable Voice input required Important: These register fields must same value. Table full definitions these fields. AINLMODE LL4BVOL LR4BVOL
Right Channel Voice Mode (RXVOICE AINRMUX)
AINRMODE RL4BVOL RR4BVOL
Table RxVoice Mode Register Settings
Record
RXVOICE
DIFFINL
RXVOICE DIFFINR
Figure RxVoice Mode Signal Paths
RIN1 RIN2
RIN3/GPI8 RIN4/RXP
RIN34
RIN12
LIN4/RXN
LIN3/GPI7
LIN1 LIN2
LIN12
LIN34
INMIXL AINLMUX
AINRMUX
INMIXR
Record
April 2009,
Pre-Production
WM8400
Differential Mode (AINLMODE=10, AINRMODE=10), additional volume control available input signal path, Input volume control used adjust signal level with other modes. Both PGAs desired channel(s) must enabled, volumes each same value true Differential input characteristics. Output (LIN12 RIN12) Mixer (INMIXL INMIXR) path must also enabled desired channel(s) register L12MNB R12MNB. This configuration illustrated Figure applicable register settings shown Table CONFIGURATION Left Channel Differential Mode (DIFFINL AINLMUX) REGISTER SETTINGS Select Differential Mode Enable LIN12 input path channel volume required. Important: LIN12 LIN34 volume mute settings must same value. Table full definitions these fields. Select Differential Mode Enable RIN12 input path channel volume required. Important: RIN12 RIN34 volume mute settings must same value. Table full definitions these fields. AINLMODE L12MNB LIN12VOL, LIN12MUTE LIN34VOL, LIN34MUTE
Right Channel Differential Mode (DIFFINR AINRMUX)
AINRMODE R12MNB RIN12VOL, RIN12MUTE RIN34VOL, RIN34MUTE
Table Differential Mode Register Settings
Figure Differential Mode Signal Paths
April 2009,
WM8400
INPUT MIXER VOLUME CONTROL
Pre-Production
Input Mixer volume controls described Table Left Channel Table Right Channel. Input levels Mute, 30dB boost. other gain controls provide adjustment from -12dB +6dB steps. prevent noise recommended that gain mute controls input mixers modified while signal paths active. volume control required input signal path recommended that input volume controls volume controls used instead input mixer gain registers.
April 2009,
Pre-Production REGISTER ADDRESS (29h) LABEL L34MNB DEFAULT
WM8400
LIN34 Output INMIXL Mute Mute Un-Mute LIN34 Output INMIXL Gain +30dB LIN12 Output INMIXL Mute Mute Un-Mute LIN12 Output INMIXL Gain +30dB LOMIX INMIXL Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB LIN2 INMIXL Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE AINLMUX Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE INMIXL Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB Note LR4BVOL must same value LL4BVOL when AINLMODE=01.
L34MNBST
L12MNB
L12MNBST
LDBVOL [2:0]
000b (Mute)
(2Bh)
LI2BVOL [2:0]
000b (Mute)
LR4BVOL [2:0]
000b (Mute)
LL4BVOL [2:0]
000b (Mute)
Table Left Input Mixer Volume Control
April 2009,
WM8400
REGISTER ADDRESS (2A) LABEL R34MNB DEFAULT
Pre-Production DESCRIPTION RIN34 Output INMIXR Mute Mute Un-Mute RIN34 Output INMIXR Gain +30dB RIN12 Output INMIXR Mute Mute Un-Mute RIN12 Output INMIXR Gain +30dB ROMIX INMIXR Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RIN2 INMIXR Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE AINRMUX Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB RXVOICE INMIXR Gain Mute Mute -12dB -9dB -6dB -3dB +3dB +6dB Note RL4BVOL must same value RR4BVOL when AINRMODE=01.
R34MNBST
R12MNB
R12MNBST
RDBVOL [2:0]
000b (Mute)
(2Ch)
RI2BVOL [2:0]
000b (Mute)
RL4BVOL [2:0]
000b (Mute)
RR4BVOL [2:0]
000b (Mute)
Table Right Input Mixer Volume Control
April 2009,
Pre-Production
WM8400
ANALOGUE DIGITAL CONVERTER (ADC)
WM8400 uses stereo 24-bit, oversampled sigma-delta ADCs. multi-bit feedback high oversampling rates reduces effects jitter high frequency noise. full scale input level proportional AVDD. "Electrical Characteristics" further details. input signal greater than full scale overload cause distortion. ADCs enabled ADCL_ENA ADCR_ENA register bits. REGISTER ADDRESS (03h) LABEL ADCL_ENA (rw) ADCR_ENA (rw) DEFAULT DESCRIPTION Left Enable disabled enabled Right Enable disabled enabled
Table Enable Control
DIGITAL VOLUME CONTROL
output ADCs digitally amplified attenuated over range from -71.625dB +17.625dB 0.375dB steps. volume each channel controlled separately. gain given eight-bit code given 0.375 (X-192) 239; MUTE +17.625dB
ADC_VU controls loading digital volume control data. When ADC_VU ADCL_VOL ADCR_VOL control data will loaded into respective control register, will actually change digital gain setting. Both left right gain settings updated when written ADC_VU. This makes possible update gain both channels simultaneously. REGISTER ADDRESS (10h) LABEL ADC_VU DEFAULT DESCRIPTION Volume Update Writing this will cause left right volume updated simultaneously Left Digital Volume (See Table volume range) Volume Update Writing this will cause left right volume updated simultaneously Right Digital Volume (See Table volume range)
(11h)
ADCL_VOL [7:0] ADC_VU
1100_0000b (0dB)
ADCR_VOL [7:0]
1100_0000b (0dB)
Table Digital Volume Control
April 2009,
WM8400
ADCL_VOL ADCR_VOL
Pre-Production
Volume (dB)
MUTE -71.625 -71.250 -70.875 -70.500 -70.125 -69.750 -69.375 -69.000 -68.625 -68.250 -67.875 -67.500 -67.125 -66.750 -66.375 -66.000 -65.625 -65.250 -64.875 -64.500 -64.125 -63.750 -63.375 -63.000 -62.625 -62.250 -61.875 -61.500 -61.125 -60.750 -60.375 -60.000 -59.625 -59.250 -58.875 -58.500 -58.125 -57.750 -57.375 -57.000 -56.625 -56.250 -55.875 -55.500 -55.125 -54.750 -54.375 -54.000 -53.625 -53.250 -52.875 -52.500 -52.125 -51.750 -51.375 -51.000 -50.625 -50.250 -49.875 -49.500 -49.125 -48.750 -48.375
ADCL_VOL ADCR_VOL
Volume (dB)
-48.000 -47.625 -47.250 -46.875 -46.500 -46.125 -45.750 -45.375 -45.000 -44.625 -44.250 -43.875 -43.500 -43.125 -42.750 -42.375 -42.000 -41.625 -41.250 -40.875 -40.500 -40.125 -39.750 -39.375 -39.000 -38.625 -38.250 -37.875 -37.500 -37.125 -36.750 -36.375 -36.000 -35.625 -35.250 -34.875 -34.500 -34.125 -33.750 -33.375 -33.000 -32.625 -32.250 -31.875 -31.500 -31.125 -30.750 -30.375 -30.000 -29.625 -29.250 -28.875 -28.500 -28.125 -27.750 -27.375 -27.000 -26.625 -26.250 -25.875 -25.500 -25.125 -24.750 -24.375
ADCL_VOL ADCR_VOL
Volume (dB)
-24.000 -23.625 -23.250 -22.875 -22.500 -22.125 -21.750 -21.375 -21.000 -20.625 -20.250 -19.875 -19.500 -19.125 -18.750 -18.375 -18.000 -17.625 -17.250 -16.875 -16.500 -16.125 -15.750 -15.375 -15.000 -14.625 -14.250 -13.875 -13.500 -13.125 -12.750 -12.375 -12.000 -11.625 -11.250 -10.875 -10.500 -10.125 -9.750 -9.375 -9.000 -8.625 -8.250 -7.875 -7.500 -7.125 -6.750 -6.375 -6.000 -5.625 -5.250 -4.875 -4.500 -4.125 -3.750 -3.375 -3.000 -2.625 -2.250 -1.875 -1.500 -1.125 -0.750 -0.375
ADCL_VOL ADCR_VOL
Volume (dB)
0.000 0.375 0.750 1.125 1.500 1.875 2.250 2.625 3.000 3.375 3.750 4.125 4.500 4.875 5.250 5.625 6.000 6.375 6.750 7.125 7.500 7.875 8.250 8.625 9.000 9.375 9.750 10.125 10.500 10.875 11.250 11.625 12.000 12.375 12.750 13.125 13.500 13.875 14.250 14.625 15.000 15.375 15.750 16.125 16.500 16.875 17.250 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625 17.625
Table Digital Volume Range
April 2009,
Pre-Production
WM8400
HIGH PASS FILTER
digital high pass filter applied default path remove offsets. This filter also programmed remove frequency noise voice applications (e.g. wind noise mechanical vibration). This filter controlled using ADC_HPF_ENA ADC_HPF_CUT register bits. hi-fi mode high pass filter optimised removing offsets without degrading bass response cut-off frequency 3.7Hz fs=44.1kHz. voice mode high pass filter optimised voice communication recommended program cut-off frequency below 300Hz (e.g. ADC_HPF_CUT=11 fs=8kHz ADC_HPF_CUT=10 fs=16kHz). REGISTER ADDRESS (0Fh) LABEL ADC_HPF_ENA DEFAULT DESCRIPTION Digital High Pass Filter Enable disabled enabled Digital High Pass Filter Cut-Off Frequency (fc) Hi-fi mode (fc=4Hz fs=48kHz) Voice mode (fc=127Hz fs=16kHz) Voice mode (fc=130Hz fs=8kHz) Voice mode (fc=267Hz fs=8kHz) (Note: scales with sample rate. Table cut-off frequencies supported sample rates)
ADC_HPF_CUT [1:0]
Table High Pass Filter Control Registers
SAMPLE FREQUENCY (kHz) 8.000 11.025 16.000 22.050 24.000 32.000 44.100 48.000
CUT-OFF FREQUENCY (Hz) ADC_HPF_CUT ADC_HPF_CUT ADC_HPF_CUT ADC_HPF_CUT 1063 1464 1594
Table High Pass Filter Cut-Off Frequencies
high pass filter characteristics shown "Digital Filter Characteristics" section.
April 2009,
WM8400
DIGITAL MIXING
Pre-Production
data combined various ways support range different usage modes. Data from either ADCs routed either left right channel digital audio interface. addition, data from either digital audio interface channels routed either left right DAC. "Digital Audio Interface" more information audio interface.
DIGITAL MIXING PATHS
Figure shows digital mixing paths available WM8400 digital core.
MAIN REGISTER REFERENCE REGISTER ALSO REFERENCED ELSEWHERE DIAGRAM READBACK AVAIABLE
DIGITAL CORE
DACL
HIGH PASS FILTER (VOICE HI-FI)
ADCL_DAC_SVOL [7:0]
ADC_TO_DACL [1:0] 00=0 01=ADCL 10=ADCR 11=Reserved ADC_TO_DACR [1:0]
DACL_VOL [7:0] MONO
ADCL_VOL [7:0]
ADCL_ENA ADC_HPF_CUT [1:0] ADCR_ENA
ADC_HPF_ENA
DAC_MONO
HIGH PASS FILTER (VOICE HI-FI)
DACR_VOL [7:0] DAC_MUTE, DAC_MUTEMODE, DAC_MUTERATE, DAC_SB_FILT, DEEMP[1:0]
DACR
ADCR_VOL [7:0]
ADCR_DAC_SVOL [7:0]
DAC_BOOST [1:0]
DAC_BOOST +6dB +12dB +18dB
ADCR_DATINV ADCL_DATINV
DACL_DATINV DACR_DATINV DACL_SRC DACR_SRC
AIFADCR_SRC AIFADCL_SRC
DIGITAL AUDIO INTERFACE
A-law u-law support Support
GPIO
Alternative Interface Alternative MCLK Button Control Accessory Detect Clock Output Inverted ADCLRC
GPIO6/ADCLRCB GPIO5/DACDAT2 GPIO4/DACLRC2 GPIO3/BCLK2 GPIO2/MCLK2
BCLK
DACLRC
DACDAT
ADCDAT
ADCLRC/GPIO1
Figure Digital Mixing Paths
April 2009,
Pre-Production
WM8400
polarity each output signal changed under software control using ADCL_DATINV ADCR_DATINV register bits. AIFADCL_SRC AIFADCR_SRC register bits used select which used left right digital audio interface data. These register bits described Table input data source each changed under software control using register bits DACL_SRC DACR_SRC. polarity each input also modified using register bits DACL_DATINV DACR_DATINV. These register bits described Table REGISTER ADDRESS (05h) LABEL AIFADCL_SRC DEFAULT DESCRIPTION Left Digital Audio channel source Left data output left channel Right data output left channel Right Digital Audio channel source Left data output right channel Right data output right channel Left Invert Left output inverted Left output inverted Right Invert Right output inverted Right output inverted Left Data Source Select Left outputs left channel data Left outputs right channel data Right Da
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