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ML505/ML506/ML507 ML505/ML506/M Evaluation Platform L507 Evaluation Platform
UG347 (v3.1) November 2008 [optional]
Xilinx disclosing this user guide, manual, release note, and/or specification (the "Documentation") solely development designs operate with Xilinx hardware devices. reproduce, distribute, republish, download, display, post, transmit Documentation form means including, limited electronic, mechanical, photocopying, recording, otherwise, without prior written consent Xilinx. Xilinx expressly disclaims liability arising your Documentation. Xilinx reserves right, sole discretion, change Documentation without notice time. Xilinx assumes obligation correct errors contained Documentation, advise corrections updates. Xilinx expressly disclaims liability connection with technical support assistance that provided connection with Information. DOCUMENTATION DISCLOSED "AS-IS" WITH WARRANTY KIND. XILINX MAKES OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, STATUTORY, REGARDING DOCUMENTATION, INCLUDING WARRANTIES MERCHANTABILITY, FITNESS PARTICULAR PURPOSE, NONINFRINGEMENT THIRD-PARTY RIGHTS. EVENT WILL XILINX LIABLE CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, INCIDENTAL DAMAGES, INCLUDING LOSS DATA LOST PROFITS, ARISING FROM YOUR DOCUMENTATION. 2006-2008 Xilinx, Inc. rights reserved. XILINX, Xilinx logo, Brand Window, other designated brands included herein trademarks Xilinx, Inc. PCI, PCI-SIG, EXPRESS, PCIE, PCI-X, PLUG, MINI PCI, EXPRESSMODULE, PCI, PCI-X, PLUG, MINI design marks trademarks, registered trademarks, and/or service marks PCI-SIG. other trademarks property their respective owners.
Revision History
following table shows revision history this document.
Date 11/29/06 12/01/06 Version Initial Xilinx release. Added "44. Soft Touch Landing Pad," page Corrected Table 1-6, page Added Table 1-13, page Added paragraph "36. Input Video Codec," page 01/09/06 Enhanced Table 1-3, page Corrected Table 1-31, page Updated document include ML506 board Corrected Table 1-31, page 02/16/07 Enhanced Figure 1-5, page Expanded "26. Adapter Input Power Switch/Jack," page Added Figure B-1, page Updated "Features," page 03/21/07 Swapped Table 1-3, page with Table 1-24, page better placement information Updated description Table 1-25, page Updated Table 1-31, page (see table notes) 04/17/07 06/28/07 10/30/07 Corrected GTP/GTX tile location Table 1-24, page Corrected Table 1-11, page Updated Table 1-31, page XAUI/SRIO support Update Appendix "References"Table 1-11, page Added sections "MIG Compliance," page "45. System Monitor," page Revision
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Date 05/19/08
Version
Revision Updated document include ML507 board. Added notes Figure 1-7, page Table 1-21, page Updated Appendix "References." Updated link Appendix "References." Updated Appendix "Board Revisions." Added content "17. System CompactFlash Connector," page "Configuration Options," page Updated Platform Flash memory Platform Flash PROM throughout.
07/21/08
3.0.1
11/10/08
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UG347 (v3.1) November 2008
Table Contents
Preface: About This Guide
Guide Contents Additional Documentation Additional Support Resources Typographical Conventions
Online Document Features Package Contents Additional Information Block Diagram
Overview
Related Xilinx Documents Detailed Description
Virtex-5 FPGA Configuration Voltage Rails Digitally Controlled Impedance DDR2 SODIMM Compliance DDR2 Memory Expansion DDR2 Clock Signal DDR2 Signaling Differential Clock Input Output with Connectors Oscillators Brightness Contrast Adjustment GPIO Switches (Active-High). User Error LEDs (Active-High) User Pushbuttons (Active-High) Reset Button (Active-Low) Expansion Headers Differential Expansion Connectors Single-Ended Expansion Connectors Other Expansion Connectors Stereo AC97 Audio Codec RS-232 Serial Port 16-Character 2-Line with 8-Kb EEPROM Connector PS/2 Mouse Keyboard Ports System CompactFlash Connector Synchronous SRAM Linear Flash Chips Xilinx XC95144XL CPLD 10/100/1000 Tri-Speed Ethernet Controller with Host Peripheral Ports Xilinx XCF32P Platform Flash PROM Configuration Storage Devices
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JTAG Configuration Port Onboard Power Supplies Adapter Input Power Switch/Jack Power Indicator DONE INIT Program Switch Configuration Address Mode Switches Encryption Battery Flash Controller Temperature/Voltage Monitor Piezo Input Video Codec JTAG Trace/Debug Debug Description JTAG Header Pinout JTAG Connection FPGA Rotary Encoder Differential GTP/GTX Input Output with Connectors Express Interface Serial-ATA Host Connectors Connector GTP/GTX Clocking Circuitry Overview Frequency Synthesizer SFP/SMA GTP/GTX Transceiver Clocking SATA GTP/GTX Transceiver Clock Generation. SGMII Loopback GTP/GTX Transceiver Clock Generation Soft Touch Landing System Monitor
Buses Configuration Options
JTAG (Xilinx Download Cable System Controller) Configuration Platform Flash PROM Configuration Linear Flash Memory Configuration Flash Memory Configuration
Appendix Board Revisions Appendix Programming Clock Chip
Overview Downloading ML50x Board
Appendix References
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Preface
About This Guide
ML50x evaluation platforms enable designers investigate experiment with features Virtex®-5 FPGAs. This user guide describes features operation ML505 (LXT), ML506 (SXT), ML507 (FXT) Evaluation Platforms.
Guide Contents
This manual contains following chapters: Chapter "ML505/ML506/ML507 Evaluation Platform,"provides details board components Appendix "Board Revisions," details differences between board revisions Appendix "Programming Clock Chip," shows restore default factory settings clock chip ML50x boards Appendix "References"
Additional Documentation
following documents also available download http://www.xilinx.com/virtex5. Virtex-5 FPGA Family Overview features product selection Virtex-5 FPGA family outlined this overview. Virtex-5 FPGA Data Sheet: Switching Characteristics This data sheet contains Switching Characteristic specifications Virtex-5 FPGA family. Virtex-5 FPGA User Guide This user guide includes chapters
Clocking Resources Clock Management Technology (CMT) Phase-Locked Loops (PLLs) Block FIFO memory Configurable Logic Blocks (CLBs) SelectIOResources Logic Resources Advanced Logic Resources
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Virtex-5 FPGA RocketIO GTP/GTX Transceiver User Guide This guide describes RocketIOGTP/GTX transceivers available Virtex-5 platform devices.
Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller User Guide This user guide describes dedicated Tri-Mode Ethernet Media Access Controller available Virtex-5 platform devices.
Virtex-5 FPGA Integrated Endpoint Block User Guide Express Designs This user guide describes integrated Endpoint blocks Virtex-5 platform devices Express® designs.
XtremeDSP Design Considerations This guide describes XtremeDSP. slice includes reference designs using DSP48E.
Virtex-5 FPGA Configuration User Guide This all-encompassing configuration guide includes chapters configuration interfaces (serial SelectMAP), bitstream encryption, Boundary-Scan JTAG configuration, reconfiguration techniques, readback through SelectMAP JTAG interfaces.
Virtex-5 FPGA System Monitor User Guide System Monitor functionality available Virtex-5 devices outlined this guide.
Virtex-5 FPGA Packaging Pinout Specification This specification includes tables device/package combinations maximum I/Os, definitions, pinout tables, pinout diagrams, mechanical drawings, thermal specifications.
Additional Support Resources
search database silicon software questions answers, create technical support case WebCase, Xilinx website http://www.xilinx.com/support.
Typographical Conventions
This document uses following typographical conventions. example illustrates each convention.
Convention Meaning Example
References other documents Italic font Emphasis text Underlined Text Indicates link page.
Virtex-5 Configuration Guide more information. address asserted after clock event http://www.xilinx.com/virtex5
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Typographical Conventions
Online Document
following conventions used this document:
Convention Blue text Meaning Cross-reference link location current document Cross-reference link location another document Hyperlink website (URL) Example section "Additional Documentation" details. Figure Virtex-5 Data Sheet http://www.xilinx.com latest documentation.
text Blue, underlined text
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Chapter
ML505/ML506/ML507 Evaluation Platform
Overview
ML505, ML506, ML507 Evaluation Platforms (referred ML50x this guide) enable designers investigate experiment with features Virtex-5 LXT, SXT, FPGAs. This user guide describes features operation these platforms. Although ML50x platforms provide access Virtex-5 FPGA RocketIOGTP transceivers, these boards only intended evaluation purposes, transceiver characterization. ML505, ML506, ML507 platforms same printed-circuit board (PCB). Appendix "Board Revisions" distinguishing characteristics.
Features
Xilinx Virtex-5 FPGA
XC5VLX50T-1FFG1136 (ML505) XC5VSX50T-1FFG1136 (ML506) XC5VFX70T-1FFG1136 (ML507)
Xilinx XCF32P Platform Flash PROMs each) storing large device configurations Xilinx System ACECompactFlash configuration controller with Type CompactFlash connector Xilinx XC95144XL CPLD glue logic 64-bit wide, 256-MB DDR2 small outline DIMM (SODIMM), compatible with supported software drivers Clocking
Programmable system clock generator chip open 3.3V clock oscillator socket External clocking SMAs (two differential pairs)
General purpose switches (8), LEDs (8), pushbuttons, rotary encoder Expansion header with single-ended I/O, LVDS-capable differential pairs, spare I/Os shared with buttons LEDs, power, JTAG chain expansion capability, expansion Stereo AC97 audio codec with line-in, line-out, 50-mW headphone, microphone-in jacks, SPDIF digital audio jacks, piezo audio transducer
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RS-232 serial port, header second serial port 16-character 2-line display 8-Kb EEPROM other capable devices PS/2 mouse keyboard connectors Video input/output
Video input (VGA) Video output connector (VGA supported with included adapter)
synchronous SRAM, 32-bit data with four parity bits Intel StrataFlash linear flash chip Serial Peripheral Interface (SPI) flash 10/100/1000 tri-speed Ethernet transceiver RJ-45 with support MII, GMII, RGMII, SGMII Ethernet interfaces interface chip with host peripheral ports Rechargeable lithium battery hold FPGA encryption keys JTAG configuration port with Parallel Cable III, Parallel Cable Platform download cable Onboard power supplies necessary voltages Temperature voltage monitoring chip with controller adapter Power indicator MII, GMII, RGMII, SGMII Ethernet Interfaces GTP/GTX: (1000Base-X) GTP/GTX: Differential Pairs) GTP/GTX: SGMII GTP/GTX: Express® (PCIeTM) edge connector Endpoint) GTP/GTX: SATA (dual host connections) with loopback cable GTP/GTX: Clock synthesis Mictor trace port debug port Soft touch port System monitor
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Overview
Package Contents
Xilinx Virtex-5 FPGA ML50x Evaluation Platform System CompactFlash card Power supply adaptor
Additional Information
Additional information support material located ML505 http://www.xilinx.com/ml505 ML506 http://www.xilinx.com/ml506 ML507 http://www.xilinx.com/ml507
This information includes: Current version this user guide format Example design files demonstration Virtex-5 FPGA features technology Demonstration hardware software configuration files System controller, Platform Flash PROM configuration storage device, CPLD, linear flash chips MicroBlazeEDK reference design files Full schematics format ViewDraw schematic format board layout Allegro format Gerber files board (Many free shareware Gerber file viewers available internet viewing printing these files.) Additional documentation, errata, frequently asked questions, latest news
information about Virtex-5 family FPGA devices, including product highlights, data sheets, user guides, application notes, Virtex-5 FPGA website www.xilinx.com/virtex5. Additional information available from data sheets application notes from component manufacturers.
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Block Diagram
Figure shows block diagram ML50x Evaluation Platform (board).
JTAG
CPLD Misc. Glue Logic
Sync SRAM
System Controller JTAG
Controller
Host Peripheral Peripheral
Flash
Flash Slave Serial
Platform Flash PROMs
10/100/1000 Ethernet DDR2 SO-DIMM
RJ-45
GPIO (Button/LED/DIP Switch) Piezo/Speaker Clock Generator Plus User Oscillator System Monitor (Differential In/Out Clocks) Dual PS/2
Master Serial
Digital Audio AC97 Audio CODEC Input Codec Output Codec DVI-I Video Serial Line Headphone Line
SelectMap
Virtex-5 LXT/SXT/FXT FPGA
JTAG
RS-232 XCVR Battery Header Character
JTAG
GTP: Serial
User
GTP: GTP:
Header
EEPROM
GTP: PCIe
UG347_03_110708
Figure 1-1:
Virtex-5 FPGA ML50x Evaluation Platform Block Diagram
Related Xilinx Documents
Prior using ML50x Evaluation Platform, users should familiar with Xilinx resources. Appendix "References" direct links Xilinx documentation. following locations additional documentation Xilinx tools solutions: EDK: www.xilinx.com/edk ISE: www.xilinx.com/ise Answer Browser: www.xilinx.com/support Intellectual Property: www.xilinx.com/ipcenter
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Detailed Description
Detailed Description
ML505 Evaluation Platform shown Figure (front) Figure 1-3, page (back). numbered sections pages following figures contain details each feature.
Diff Output Pair
Keybd
Mouse
System Reset
UG347_01_102907
Diff Input Pair
Figure 1-2:
Detailed Description Virtex-5 FPGA ML505 Components (Front)
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Figure 1-3:
shown.
Detailed Description Virtex-5 FPGA ML505 Components (Back)
Note: label CompactFlash (CF) card shipped with your board might differ from
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Detailed Description
Virtex-5 FPGA
Xilinx Virtex-5 FPGA installed board. Appendix "Board Revisions" device details.
Configuration
board supports configuration modes: JTAG, Master Serial, Slave Serial, Master SelectMAP, Slave SelectMAP, Byte-wide Peripheral Interface (BPI) Down, modes. "Configuration Options," page section more information.
Voltage Rails
Table summarizes FPGA voltage rail voltages applied each bank. Table 1-1: Voltage Rail FPGA Banks
Voltage Rail 3.3V 3.3V 3.3V 2.5V 3.3V 3.3V with 49.9 resistors installed 3.3V (unused) User selectable 2.5V 3.3V using jumper 3.3V with 49.9 resistors installed User selectable 2.5V 3.3V using jumper 1.8V with 49.9 resistors installed 1.8V with 49.9 resistors installed 3.3V 1.8V with 49.9 resistors installed 3.3V with 49.9 resistors installed 1.8V with 49.9 resistors installed 3.3V with 49.9 resistors installed 3.3V with 49.9 resistors installed 3.3V (unused) FPGA Bank
Notes:
Banks available ML507 only.
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Digitally Controlled Impedance
Some FPGA banks support digitally controlled impedance (DCI) feature Virtex-5 FPGAs. Support summarized Table 1-2. Table 1-2: Capability FPGA Bank
Capability supported supported supported supported Yes, 49.9 resistors installed supported Yes, 49.9 resistors installed Yes, 49.9 resistors installed Yes, 49.9 resistors installed Yes, 49.9 resistors installed Yes, 49.9 resistors installed supported Yes, 49.9 resistors installed
FPGA Bank
DDR2 SODIMM
ML50x platform shipped with single-rank unregistered SODIMM. DDR2 SODIMM used generally Micron MT4HTF3264HY-53E similar module. Serial Presence Detect (SPD) using interface DIMM also supported with FPGA. Note: board only tested DDR2 SDRAM operation data rate. Faster data
rates might possible tested.
Compliance
ML50x DDR2 interface pinout compliant. DDR2 routing guidelines outlined Xilinx Memory Interface Generator (MIG) User Guide [Ref have been achieved. board's DDR2 SODIMM memory interface designed requirements defined User Guide using tool. documentation requires that designers follow pinout layout guidelines. tool generates ensures that proper FPGA selections made support board's DDR2 interface. initial selection board modified then re-verified meet pinout requirements. ensure robust interface, ML50x DDR2 layout incorporates matched trace lengths data signals corresponding data strobe signal defined user guide. Appendix "References" links additional information about Virtex-5 FPGAs general.
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Detailed Description
DDR2 Memory Expansion
DDR2 interface support user installation SODIMM modules with more memory since higher order address chip select signals also routed from SODIMM FPGA.
DDR2 Clock Signal
matched length pairs DDR2 clock signals broadcast from FPGA SODIMM. FPGA design responsible driving both clock pairs with skew. delay clock trace designed match delay other DDR2 control signals.
DDR2 Signaling
DDR2 SDRAM control signals terminated through resistors 0.9V reference voltage. FPGA DDR2 interface supports SSTL18 signaling DDR2 signals controlled impedance. DDR2 data, mask, strobe signals matched length within byte groups. functionality SODIMM should utilized.
Differential Clock Input Output with Connectors
High-precision clock signals input FPGA using differential clock signals brought through connectors. This allows external function generator other clock source drive differential clock inputs that directly feed global clock input pins FPGA. FPGA configured present termination impedance. differential clock output from FPGA driven through LVDS clock multiplexer (U12) onto second pair connectors (J12 J13). This allows FPGA drive precision clock external device such piece test equipment. Table summarizes differential clock connections. Table 1-3:
Connector
Notes:
When jumper (located near battery) shunted (default), FPGA differential clock output selected driven connectors, J13.
Differential Clock Connections
Clock Name SMA_DIFF_CLK_IN_P SMA_DIFF_CLK_IN_N SMA_DIFF_CLK_OUT_P SMA_DIFF_CLK_OUT_N FPGA ML505/ML506 GTP1 GTP_X0Y4 receive pair GTP1 GTP_X0Y4 transmit pair ML507 GTX1
GTX_X0Y5 receive pair
GTX1 GTX_X0Y5 transmit pair
Oscillators
board crystal oscillator socket (X1) wired standard LVTTL-type oscillators. connects FPGA clock shown Table 1-4, page socket populated with 100-MHz oscillator powered 3.3V supply board also provides IDT5V9885 (U8) EEPROM programmable clock generator device. This device used generate variety clocks board peripherals
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FPGA. programmable clock generator provides following factory default singleended outputs: Ethernet (U16) 24.5 audio codec (U22) Controller (U23) Xilinx System (U2) MHz, MHz, differential clock Xilinx FPGA
users change factory default configuration clock generator chip, related reference design material might work designed. Instructions returning IDT5V9885 factory default configuration provided Appendix "Programming Clock Chip." Table 1-4: Oscillator Socket Connections
Clock Name USER_CLK CLK_33MHZ_FPGA CLK_27MHZ_FPGA CLK_FPGA_P CLK_FPGA_N FPGA AH15 AH17 AG18 Description single-ended single-ended single-ended differential pair (pos) differential pair (neg)
Reference Designator
Brightness Contrast Adjustment
Turning potentiometer adjusts image contrast character LCD. potentiometer should turned with screwdriver.
GPIO Switches (Active-High)
Eight general-purpose (active-High) switches connected user pins FPGA. Table summarizes these connections. Table 1-5: Switch Connections (SW4)
FPGA
GPIO_DIP_SW1 GPIO_DIP_SW2 GPIO_DIP_SW3 GPIO_DIP_SW4 GPIO_DIP_SW5 GPIO_DIP_SW6 GPIO_DIP_SW7 GPIO_DIP_SW8
AG27 AF25 AF26 AE27 AE26 AC25 AC24
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Detailed Description
User Error LEDs (Active-High)
There total active-High LEDs directly controllable FPGA: Eight green LEDs general purpose LEDs arranged Five green LEDs positioned next pushbuttons (only center cited Figure 1-2, page LEDs intended used signaling error conditions, such errors, used other purpose
Some LEDs buffered through CPLD allow signals used higherperformance expansion connector. Table summarizes definitions connections. Table 1-6: User Error Connections
Label/Definition North East South West Center GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO Error Error Color Green Green Green Green Green Green Green Green Green Green Green Green Green FPGA AF13 AG23 AG12 AF23 Buffered
Reference Designator DS20 DS21 DS22 DS23 DS24
DS17 DS16 DS15 DS14 DS13 DS12 DS11 DS10
AD26 AD25 AD24 AE24
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User Pushbuttons (Active-High)
Five active-High user pushbuttons available general purpose usage arranged North-East-South-West-Center orientation (only center cited Figure 1-2, page 15). Table summarizes user pushbutton connections. Table 1-7: User Pushbutton Connections
Label/Definition (GPIO North) (GPIO South) (GPIO East) (GPIO West) (GPIO Center) FPGA
Reference Designator
SW10 SW11 SW12 SW13 SW14
Reset Button (Active-Low)
reset button active-Low pushbutton used system user reset button. This pushbutton switch wired only FPGA also used general-purpose pushbutton switch (Table 1-8). Table 1-8: Reset Connections
Label/Definition RESET FPGA
Reference Designator
Expansion Headers
board contains expansion headers easy expansion adaptation board other applications. expansion connectors standard 0.1-inch headers. expansion connectors contain connections single-ended differential FPGA I/Os, ground, 2.5V/3.3V/5V power, JTAG chain, bus. signals connectors have matched length traces that matched each other.
Differential Expansion Connectors
Header contains pairs differential signal connections FPGA I/Os. This permits signals this connector carry high-speed differential signals, such LVDS data. differential signals routed with differential trace impedance. Matched length traces used across differential signals Consequently, these signals connect FPGA I/O, they used independent single-ended nets. VCCIO these signals 2.5V 3.3V setting jumper J20. Table 1-9, page summarizes differential connections this expansion connector.
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Detailed Description
Table 1-9:
Expansion Differential Connections (J4)
Schematic Name HDR2_4 HDR2_8 HDR2_12 HDR2_16 HDR2_20 HDR2_24 HDR2_28 HDR2_32 HDR2_36 HDR2_40 HDR2_44 HDR2_48 HDR2_52 HDR2_56 HDR2_60 HDR2_64 HDR2_2 HDR2_6 HDR2_10 HDR2_14 HDR2_18 HDR2_22 HDR2_26 HDR2_30 HDR2_34 HDR2_38 HDR2_42 HDR2_46 HDR2_50 HDR2_54 HDR2_58 HDR2_62 AF34 AF33 AC34 AC32 AC33 AN32 FPGA AA33 AE34 AE33 AD34 AB32 AB33 AP32
Differential Pair
Single-Ended Expansion Connectors
Header contains single-ended signal connections FPGA I/Os. This permits signals this connector carry high-speed, single-ended data. single-ended signals connector matched length traces. VCCIO these signals 2.5V 3.3V setting jumper J20. Table 1-10 summarizes single-ended connections this expansion connector. Table 1-10:
Expansion Single-Ended Connections (J6)
Schematic Name HDR1_2 HDR1_4 HDR1_6 HDR1_8 HDR1_10 HDR1_12 HDR1_14 HDR1_16 FPGA
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Table 1-10:
Expansion Single-Ended Connections (J6) (Cont'd)
Schematic Name HDR1_18 HDR1_20 HDR1_22 HDR1_24 HDR1_26 HDR1_28 HDR1_30 HDR1_32 HDR1_34 HDR1_36 HDR1_38 HDR1_40 HDR1_42 HDR1_44 HDR1_46 HDR1_48 HDR1_50 HDR1_52 HDR1_54 HDR1_56 HDR1_58 HDR1_60 HDR1_62 HDR1_64 FPGA AA34 AD32 AH34 AE32 AG32 AH32 AK34 AK33 AJ32 AK32 AL34 AL33 AM33 AJ34 AM32 AN34 AN33
Other Expansion Connectors
addition high-speed paths, additional signals power connections available support expansion cards plugged into ML50x board. Fourteen pins from general-purpose pushbutton switches LEDs board connected expansion connector This permits additional I/Os connect expansion connector pushbutton switches LEDs used. connection also allows expansion card utilize pushbutton switches LEDs board. expansion connector also allows board's JTAG chain extended onto expansion card setting jumper accordingly. board also extended onto expansion connector allow additional devices bused together. expansion utilized, user must
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Detailed Description
have pull-up resistors present expansion card. Bidirectional level shifting transistors allow expansion card utilize 2.5V signaling bus. Power supply connections expansion connectors provide ground, 2.5V, 3.3V, power pins. expansion card draws significant power from ML50x board, ensure that total power draw supplied board. ML50x expansion connector backward compatible with expansion connectors ML40x, ML32x, ML42x boards, thereby allowing their daughter cards used with ML50x Evaluation Platform. Table 1-11 summarizes additional expansion connections. Table 1-11: Additional Expansion Connections (J5)
Label VCC5 VCC5 VCC5 VCC5 VCC3V3 VCC3V3 VCC3V3 VCC3V3 FPGA_EXP_TMS FPGA_EXP_TCK FPGA_EXP_TDO FPGA_EXP_TDI FPGA Description Power Supply Power Supply Power Supply Power Supply Connected 3.3V Power Supply 3.3V Power Supply 3.3V Power Supply 3.3V Power Supply Connected Expansion Expansion Expansion Expansion North GPIO Switch North Center GPIO Switch Center West GPIO Switch West South GPIO Switch South East GPIO Switch East GPIO
AF13 AF23 AG12 AG23
GPIO_LED_N GPIO_LED_C SW14 GPIO_LED_W SW13 GPIO_LED_S SW11 GPIO_LED_E SW12 GPIOLED
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Table 1-11:
Additional Expansion Connections (J5) (Cont'd)
Label FPGA Description GPIO GPIO GPIO Connected Connected Expansion Expansion
GPIOLED GPIOLED GPIOLED
IIC_SCL_EXP IIC_SDA_EXP
Stereo AC97 Audio Codec
ML50x board AC97 audio codec (U22) permit audio processing. Analog Devices AD1981 Audio Codec supports stereo 16-bit audio with 48-kHz sampling. sampling rate record playback different. Note: reset AC97 codec shared with reset signal flash memory chips
designed asserted power-on system reset.
Separate audio jacks provided Microphone, Line Line Out, Headphone. jacks stereo except Microphone. Headphone jack driven audio codec's internal 50-mW amplifier. SPDIF jack supplies digital audio output from codec. Table 1-12 summarizes audio jacks. Table 1-12: Audio Jacks
Function Microphone Analog Line Analog Line Headphone SPDIF
Reference Designator
Table 1-13 shows control pins audio codec. Table 1-13: Audio Codec Control Connections
FPGA AF18 AE18 AG16 AF19 AG17
Name AUDIO_BIT_CLK AUDIO_SDATA_IN AUDIO_SDATA_OUT AUDIO_SYNC FLASH_AUDIO_RESET_B
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Detailed Description
RS-232 Serial Port
ML50x board contains male DB-9 RS-232 serial port, allowing FPGA communicate serial data with another device. serial port wired host (DCE) device. Therefore, null modem cable normally required connect board serial port computer. serial port designed operate 115200 interface chip used shift voltage level between FPGA RS-232 signals. Note: FPGA connected only data pins serial port. Therefore, other
RS-232 signals, including hardware flow-control signals, used. Flow control should disabled when communicating with computer.
secondary serial interface available using header support debug controller chip. Header brings RS-232 voltage level signals ground, data, data.
16-Character 2-Line
ML50x board 16-character 2-line (Tianma TM162VBA6) board display text information. Potentiometer adjusts contrast LCD. data interface connected FPGA support 4-bit mode only. CPLD used shift voltage level between FPGA LCD. module connector that allows removed from board access components below Caution! Care should taken scratch damage surface window.
with 8-Kb EEPROM
EEPROM (STMicroelectronics M24C08) provided board store nonvolatile data such Ethernet address. EEPROM write protect disabled board. pull-up resistors provided board. extended expansion connector that user additional devices share controller FPGA. expansion utilized, user must have additional pull-up resistors present expansion card. Bidirectional level shifting transistors allow expansion card utilize 2.5V signaling IIC.
Connector
connector (P7) present board support external video monitor. circuitry utilizes Chrontel CH7301C capable 1600 1200 resolution with 24-bit color. video interface chip drives both digital analog signals connector. monitor connected board directly. monitor also connected board using supplied DVI-to-VGA adaptor. Chrontel CH7301C controlled video bus.
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connector (Table 1-14) supports protocol allow board read monitor's configuration parameters. These parameters read FPGA using bus. Table 1-14: Controller Connections
FPGA AN12 AP12 AM13 AN13 AA10 AB10 AP14 AN14 AL11 AL10 AM12 AM11 Name DVI_D[0] DVI_D[1] DVI_D[2] DVI_D[3] DVI_D[4] DVI_D[5] DVI_D[6] DVI_D[7] DVI_D[8] DVI_D[9] DVI_D[10] DVI_D[11] DVI_XCLK_P DVI_XCLK_N DVI_HSYNC DVI_VSYNC DVI_DE DVI_RESET_B
PS/2 Mouse Keyboard Ports
board contains PS/2 ports: mouse (P5) other keyboard (P4). Bidirectional level shifting transistors allow FPGA's 1.8V interface with PS/2 ports. PS/2 ports board powered directly main power jack, which also powers rest board. Caution! Care must taken ensure that power load attached PS/2 devices does
overload adapter.
System CompactFlash Connector
Xilinx System CompactFlash (CF) configuration controller allows Type CompactFlash card program FPGA through JTAG port. Both hardware software data downloaded through JTAG port. System controller supports eight configuration images single CompactFlash card. configuration address switches allow user choose which eight configuration images use.
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Detailed Description
CompactFlash card shipped with board correctly formatted enable System controller access data stored card. System controller requires FAT16 file system, with only reserved sector permitted, sector-per-cluster size more than (UnitSize greater than 512). FAT16 file system supports partitions multiple partitions used, System directory structure must reside first partition CompactFlash, with xilinx.sys file located root directory. xilinx.sys file used System controller define project directory structure, which consists main folder containing eight sub-folders used store eight files containing configuration images. Only file should exist within each sub-folder. folder names must compliant short filename format. This means that folder names eight characters long, cannot contain following reserved characters: This filename restriction does apply actual file names. Other folders files also coexist with System project within FAT16 partition. However, root directory must contain more than total folder and/or file entries, including deleted entries. When ejecting unplugging CompactFlash device, important safely stop read write access CompactFlash device avoid data corruption. CompactFlash file system becomes corrupted, copy original demonstration image shipped with board), well instructions re-imaging CompactFlash card restore original demonstration image available online: ML505 ML506 ML507
Within demonstration image, Configuration Image (cfg6) File reserved placeholder replaced user design. After creating file, file copied from your computer ML50x\cfg6 directory CompactFlash card using CompactFlash programmer (USB CompactFlash reader/writer devices card adapters available computer stores). step-by-step instructions create file from FPGA bitstream (and file) using genace.tcl script, File section ML505/ML506/ML507 Getting Started Tutorial [Ref well Stand-Alone Software Applications section ML505/ML506/ML507 Reference Design User Guide [Ref System error status LEDs indicate operational state System controller: blinking error indicates that CompactFlash card present solid error indicates error condition during configuration blinking green status indicates configuration operation ongoing solid green status indicates successful download
Every time CompactFlash card inserted into System socket, configuration operation initiated. Pressing System reset button re-programs FPGA. Note: System configuration enabled switch. "31. Configuration Address
Mode Switches."
board also features System failsafe mode. this mode, System controller detects failed configuration attempt, automatically reboots back predefined configuration image. failsafe mode enabled inserting jumpers across horizontal vertical orientation).
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Caution! caution when inserting CompactFlash card with exposed metallic surfaces. Improper insertion cause short with traces components board. System port connected FPGA. This connection allows FPGA System controller reconfigure system access CompactFlash card generic file system. data System port shared with controller.
Synchronous SRAM
synchronous SRAM (ISSI IS61NLP25636A-200TQL) provides high-speed, lowlatency external memory FPGA. memory organized 256K bits. This organization provides 32-bit data with support four parity bits. SRAM located under removable visible Figure 1-2, page Note: SRAM FLASH memory share same data bus.
Linear Flash Chips
linear flash device (Intel JS28F256P30T95) installed board provide flash memory. This memory provides non-volatile storage data, software, bitstreams. flash chip bits wide shares data with SRAM. flash memory also used program FPGA. Note: reset AC97 Codec shared with reset signal flash memory chips
designed asserted power-on system reset.
Xilinx XC95144XL CPLD
Xilinx XC95144XL CPLD provides general-purpose glue logic board. CPLD located under removable visible Figure 1-2, page CPLD programmed from main JTAG chain board. CPLD mainly used implement level translators, simple gates, buffers.
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Detailed Description
10/100/1000 Tri-Speed Ethernet
board contains Marvell Alaska device (88E1111) operating 10/100/1000 Mb/s. board supports MII, GMII, RGMII, SGMII interface modes with FPGA. connected Halo HFJ11-1G01E RJ-45 connector with built-in magnetics. configured default power-on reset settings shown Table 1-15. These settings overwritten software. modes selectable jumpers shown Table 1-15. Table 1-15:
Config CONFIG0 CONFIG1 CONFIG2 CONFIG3
Board Connections Configuration Pins
Connection Board 2.5V Ground 2.5V 2.5V 2.5V LED_DUPLEX LED_LINK1000 (Set J24) 2.5V LED_LINK10 (Set J22) LED_RX Bit[2] Definition Value PHYADR[2] ENA_PAUSE ANEG[3] ANEG[0] HWCFG_MODE[2] (Set J24) DIS_FC Bit[1] Definition Value PHYADR[1] PHYADR[4] ANEG[2] ENA_XC Bit[0] Definition Value PHYADR[0] PHYADR[3] ANEG[1] DIS_125
CONFIG4
HWCFG_MODE[1]
HWCFG_MODE[0]
CONFIG5
DIS_SLEEP
HWCFG_MODE[3]
CONFIG6
SEL_BDT
INT_POL
75/50
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Jumpers J22, J23, allow user select default interface that uses (Figure Table 1-16). interface also changed MDIO commands.
GMII/MII copper
SGMII copper; clock
RGMII; modified copper
Note: SATA Clock Select
UG347_05_112706
Figure 1-4: Table 1-16:
Jumpers Board
Default Interface Mode
Jumper Settings
Mode GMII/MII copper (default) SGMII copper, clock RGMII Jumper over pins Jumper over pins Jumper over pins Jumper over pins Jumper over pins jumper jumper jumper Jumper
Controller with Host Peripheral Ports
Cypress CY7C67300 embedded host controller provides connectivity board. controller supports host peripheral modes operation. controller serial interface engines (SIE) that used independently. SIE1 connected Host connector (P18). SIE2 connected only Peripheral connector (P17). controller internal microprocessor assist processing commands. firmware this processor stored dedicated EEPROM (U28) downloaded from host computer peripheral connector. controller's serial port connected through RS-232 transceiver assist with debug. Jumper installed prevent controller from executing firmware stored EEPROM.
Xilinx XCF32P Platform Flash PROM Configuration Storage Devices
onboard Xilinx XCF32P Platform Flash PROM configuration storage devices offer convenient easy-to-use configuration solution FPGA. Platform Flash PROM holds separate configuration images four with compression) that accessed through configuration address switches. Platform Flash PROM configure FPGA, configuration switch must correct position.
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Detailed Description
Platform Flash PROM program FPGA using master slave configuration serial parallel (SelectMap) modes. Platform Flash PROM programmed using Xilinx iMPACT software through board's JTAG chain. "Configuration Options," page section more information.
JTAG Configuration Port
JTAG configuration port board (J1) allows device programming FPGA debug. JTAG port supports Xilinx Parallel Cable III, Parallel Cable Platform cable products. Third-party configuration products might also available. JTAG chain also extended expansion board setting jumper accordingly. "Configuration Options," page section more information.
Onboard Power Supplies
Power supply circuitry board generates 0.9V, 1.0V, 1.8V, 2.5V, 3.3V voltages power components board. 1.0V, 1.8V, 3.3V supplies driven Texas Instruments PTH08T2 switching power regulators. These regulators driven with clock they synchronous each other, reducing noise caused beat frequencies. clocks sent each regulator also phase reduce reflected noise input. addition, board utilizes regulators' turbo trans feature improve output transient response. diagram Figure 1-5, page shows power supply architecture maximum current handling each supply. typical operating currents significantly below maximum capable. board normally shipped with power supply, which should sufficient most applications.
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Brick 3.3V Host 240W Switching Regulator TPS74401 TPS74401 Host 220W Switching Regulator TPS74401 TPS74401
PS/2 1.0V FPGA Core 2.5V FPGA 2.5V FPGA VCCAUX 1.2V GTP/GTX AVTT 1.2V GTP; 1.0V GTP/GTX AVCC FPGA Host 240W Switching Regulator TPS74401 1.0V GTP/GTX AVCC 1.8V DDR2 SODIMM PROMs TPS51100 TPS51100 0.9V VTTVREF 0.9V VTTDDUG347_05_050908
Figure 1-5: Power Supply Diagram
Adapter Input Power Switch/Jack
board powered sources; P20, barrel type plug (center positive) J15, Personal Computer (PC) type disk drive connector. barrel type plug connects power brick provided with board while disk drive connector provided users want power their board while installed inside chassis. applications requiring additional power, such expansion cards drawing significant power, larger adapter might required. different adapter used, load regulation should less than better than ±10%. power switch, SW1, turns board controlling supply board shown Figure 1-5, page Note: Never apply power power brick connector (P20) disk drive connector (J15)
same time this will result damage board.
Power Indicator
Good lights when supply applied.
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Detailed Description
DONE
DONE indicates status DONE FPGA. should lighted when FPGA successfully configured.
INIT
INIT lights upon power-up indicate that FPGA successfully powered completed internal power-on process.
Program Switch
This switch grounds FPGA's Prog when pressed. This action clears FPGA.
Configuration Address Mode Switches
8-position switch (SW3) sets address mode configuration. also enables fallback configuration Platform Flash PROM enables System configuration. Table 1-17 lists function each switch. Table 1-17: Configuration Address Switch Settings
Function Config Address [2]. Config Address [1]. Config Address [0]. MODE [2]. MODE [1]. MODE [0]. Platform Flash PROM Fallback Enable, Disable).(1) System Configuration Enable, Disable). When enabled, System controller configures FPGA from card whenever card inserted SYSACE RESET button pressed. Switch (SW3)
Notes:
Reserved future use. currently implemented.
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Configuration Address [2:0] allows user select among multiple configuration images. System configuration, eight possible configurations stored card. Platform Flash PROM Linear Flash hold four separate bitstreams that chosen Configuration Address [2:0]. Mode[2:0] selects FPGA configuration mode according Table 1-18. Table 1-18: Configuration Mode Switch Settings
Mode Master Serial (Platform Flash PROM, four configurations) (One configuration) (Parallel Flash, four configurations) Down (Parallel Flash, four configurations) Master SelectMAP (Platform Flash PROM, four configurations) JTAG (PC4, System eight configurations) Slave SelectMAP (Platform Flash PROM, four configurations) Slave Serial (Platform Flash PROM, four configurations) Mode[2:0]
Encryption Battery
onboard rechargeable lithium battery connected VBATT FPGA hold encryption FPGA.
Flash
ML50x board 32-Mb Flash Microelectronics M25P32). Flash used FPGA configuration hold user data. Flash in-system programmed using Xilinx download cable with flying leads attached header (Figure 1-6).
Prog
INIT VCC3V3
UG347_09_021407
Figure 1-6:
Flash Programming Header
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Detailed Description
Controller Temperature/Voltage Monitor
Onboard temperature voltage monitoring control handled Analog Devices ADT7476A chip. This chip controlled provide following functions: Measure voltage 3.3V, 1.8V, 1.0V supplies Measure FPGA temperature DXP/DXN pins FPGA Measure ambient temperature Read power good status signals from 2.5V linear regulators control speed Tachometer readings Generate interrupts/alarms based readings
Connector keyed three-pin header similar those found computers. designed support fan. bypass controller chip operate full speed, user populate connector J32. high-power operating conditions, heatsink and/or FPGA accommodated board. board does ship with heatsink/fan unit accommodate (for example, Calgreg Electronics Smart-CLIP family heatsink/fan assemblies).
Piezo
piezo audio transducer (Table 1-19) provided allow simple beeps, tones, songs played. piezo driven transistor controlled FPGA. Table 1-19:
Name piezo
Piezo Connection
FPGA
Input Video Codec
DB15HD connector (P8) board supports connectivity external source. input codec circuitry utilizes Analog Devices AD9980 device (U19). AD9980 8-bit MSPS interface optimized capturing YPbPr video graphics signals. MSPS encode rate supports HDTV video modes graphics resolutions (1024 Hz). Analog Devices AD9980 device controlled Video bus. Table 1-20 shows connections input video codec. Table 1-20: Interface Connections
FPGA Name VGA_IN_RED0 VGA_IN_RED1 VGA_IN_RED2 VGA_IN_RED3 VGA_IN_RED4
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Table 1-20:
Interface Connections (Cont'd)
FPGA
Name VGA_IN_RED5 VGA_IN_RED6 VGA_IN_RED7 VGA_IN_GREEN0 VGA_IN_GREEN1 VGA_IN_GREEN2 VGA_IN_GREEN3 VGA_IN_GREEN4 VGA_IN_GREEN5 VGA_IN_GREEN6 VGA_IN_GREEN7 VGA_IN_BLUE0 VGA_IN_BLUE1 VGA_IN_BLUE2 VGA_IN_BLUE3 VGA_IN_BLUE4 VGA_IN_BLUE5 VGA_IN_BLUE6 VGA_IN_BLUE7 VGA_IN_CLAMP VGA_IN_COAST VGA_IN_EVEN_B VGA_IN_VSOUT VGA_IN_HSOUT VGA_IN_SOGOUT
JTAG Trace/Debug
Debug Description
External-debug mode used alter normal program execution. provides ability debug both system hardware software. External-debug mode supports setting multiple breakpoints, well monitoring processor status. Access processor debugging resources available through JTAG port (J51) providing appropriate connections FPGA fabric place.
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Detailed Description
JTAG debug port supports four required JTAG signals: TCK, TMS, TDI, TDO. also implements optional TRST signal. frequency JTAG clock signal range from (DC) one-half processor clock frequency. JTAG debug port logic reset same time system reset, using TRST. When TRST asserted, JTAG controller returns test-logic reset state. Figure shows 38-pin Mictor connector that combines Trace Debug interfaces high-speed, controlled-impedance signaling. Note: MICTOR_* pins only available ML507 board. These pins connected
ML505 ML506 boards.
Mictor (P22)
2.5V
TRC_TS6 TRC_TS5 TRC_TS4 TRC_TS3 TRC_TS2E TRC_TS1E TRC_TS2O TRC_TS1O MICTOR_22 MICTOR_20 MICTOR_18 MICTOR_16 TRC_VSENSE TRC_CLK
MICTOR_37 MICTOR_35 MICTOR_33 MICTOR_31 MICTOR_29 MICTOR_27 MICTOR_25 MICTOR_23 CPU_TRST FPGA_CS0_B CPU_TMS CPU_TCK CPU_TDO PC4_HALT_B MICTOR_5
GND,
UG347_06_011008
Figure 1-7:
Combined Trace/Debug Connector Pinout
Table 1-21 shows trace/debug connections from FPGA BDM. Table 1-21: Trace/Debug Connection FPGA
FPGA (U1)
Name
MICTOR_5 TRC_CLK PC4_HALT_B (CPU_HALT_N)
Mictor (P22)
(J51)
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Table 1-21:
Trace/Debug Connection FPGA (Cont'd)
FPGA (U1)
Name
CPU_TDO TRC_VSENSE CPU_TCK MICTOR_16 CPU_TMS MICTOR_18 FPGA_CS0_B (CPU_TDI) MICTOR_20 CPU_TRST MICTOR_22 MICTOR_23 TRC_TS1O MICTOR_25 TRC_TS2O MICTOR_27 TRC_TS1E MICTOR_29 TRC_TS2E MICTOR_31 TRC_TS3 MICTOR_33 TRC_TS4 MICTOR_35 TRC_TS5 MICTOR_37 TRC_TS6
Mictor (P22)
(J51)
AF21
AF10 AJ11 AK11 AD11 AD10
Notes:
MICTOR_* pins only available ML507 board. These pins connected ML505 ML506 boards.
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Detailed Description
JTAG Header Pinout
Figure shows J12, 16-pin header that used debug software operating with debug tools such Parallel Cable third party tools.
CPU_TMS CPU_HALT_N CPU_TCK CPU_TDI CPU_TDO
CPU_TRST_N CPU_VSENSE
UG347_07_111505
Figure 1-8: JTAG Header (J12)
JTAG Connection FPGA
connections between JTAG header (J12) FPGA shown Table 1-22. These attached PowerPC® processor JTAG debug resources using normal FPGA routing resources. JTAG debug resources hard-wired particular pins available attachment FPGA fabric, making possible route these signals preferred FPGA pins. Table 1-22: JTAG Connection FPGA
FPGA (U1) Connector (J12) Name CPU_TDO
AF21
FPGA_SC0_B (CPU_TDI)
CPU_TRST_N CPU_TCK CPU_TMS
PC4_HALT_B (CPU_HALT_N)
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Rotary Encoder
board provides connectivity rotary encoder (Panasonic EVQWK4001) with detents, pushbutton, phase output signals direction rotation interpretation. complete revolution rotary wheel produces pulses that output nets FPGA_ROTARY_INCA FPGA_ROTARY_INCB. Pushing rotary wheel laterally causes momentary switch closure FPGA_ROTARY_PUSH output. rotary encoder circuit wired that switch closures result active-High output. Table 1-23 shows connections rotary encoder. Table 1-23: Rotary Encoder Connections
FPGA (U1) AH30 AG30 AH29
Name FPGA_ROTARY_INCA FPGA_ROTARY_INCB FPGA_ROTARY_PUSH
Differential GTP/GTX Input Output with Connectors
Four connectors (Rosenberger 32K153-400E3) provide convenient easily accessible method interfacing GTP/GTX transceivers general-purpose connectivity. SMAs designed laid provide high-quality GTP/GTX connections speeds 3.125 Gb/s. Although ML50x provides access GTP/GTX transceivers, board intended transceiver characterization. transmit pair connected directly from FPGA connectors while receive pair connected FPGA series coupling capacitors. DC-coupled receive-side connection desired, these capacitors replaced with 0402-size resistors. Table 1-24 shows transceiver pairs available through connectors. Table 1-24: Pairs through Connectors
FPGA Connector ML505/ML506 GTP1 GTP_X0Y4 receive pair GTP1 GTP_X0Y4 receive pair ML507 GTX1
Name SMA_RX_P SMA_RX_N SMA_TX_P SMA_TX_N
GTX_X0Y5
receive pair GTX1
GTX_X0Y5
receive pair
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Detailed Description
Express Interface
Table 1-25 shows PCIe connector (P21) that provides single-lane access through RocketIO transceivers Virtex-5 FPGA integrated Endpoint block PCIe designs. Virtex-5 FPGA Integrated Endpoint Block User Guide Express Designs [Ref more information. Table 1-25: PCIe Connection FPGA
FPGA (U1) AF24 Edge Connector (P21) Description
Name PCIE_RX_N PCIE_RX_P PCIE_TX_N PCIE_TX_P PCIE_CLK_N PCIE_CLK_P PCIE_PRSNT_B PCIE_PERST_B PCIE_WAKE_B
Notes:
Integrated Endpoint block receive pair
Integrated Endpoint block transmit pair Integrated Endpoint block differential clock pair from PCIe edge connector Integrated Endpoint block present signal Integrated Endpoint block reset signal available CPLD Integrated Endpoint block wake signal available CPLD
ML505/ML506 platforms, access through GTP0 GTP_X0Y1. ML507 platforms, access through GTX0 GTX_X0Y2.
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Serial-ATA Host Connectors
Serial-ATA (SATA) next generation interface used storage devices such hard disks. board contains SATA host connectors that connected SATA device (such hard disk) using standard SATA cable. SATA connectors connected GTPs FPGA shown Table 1-26. Table 1-26:
Name SATA1_RX_P SATA1_RX_N SATA1_TX_P SATA1_TX_N SATA2_RX_P SATA2_RX_N SATA2_TX_P SATA2_TX_N
SATA Connections
FPGA (U1) Connector J40, J40, J40, J40, J41, J41, J41, J41, ML505/ML506 GTP0 GTP_X0Y2 receive pair GTP0 GTP_X0Y2 transmit pair GTP1 GTP_X0Y2 receive pair GTP1 GTP_X0Y2 transmit pair ML507 GTX0 GTX_X0Y3 receive pair GTX0
GTX_X0Y3
transmit pair GTX1 GTX_X0Y3 receive pair GTX1
GTX_X0Y3
transmit pair
SATA also used convenient cost medium connecting GTP/GTX transceivers. SATA physical interface carry GTP/GTX signals Gb/s general-purpose usage. board ships with special Xilinx SATA crossover cable that used loopback connection between SATA host connectors loopback testing error rate testing (BERT). SATA crossover cable also used connect GTP/GTX transceivers between boards. GTP/GTX SATA clock jumpering, Figure 1-4, page Note: special SATA crossover cable cannot used connect SATA host SATA device
(that hard disk). only intended host-to-host loopback connections.
Connector
board contains small form-factor pluggable (SFP) connector cage assembly that accepts modules. interface connected GTP0 GTP_X0Y4 FPGA. module serial interface connected multiplexer board (See "14. with 8-Kb EEPROM," page more information). control status signals module connected jumpers, test points, LEDs described Table 1-27. module connections shown Table 1-28, page
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Detailed Description
Table 1-27:
Configuration Module Control Status Signals
Board Connection Test Point TP20 High Fault Normal Operation Jumper Jumper Enabled Jumper Disabled Test Point TP21 High Module Present Module Present Jumper Jumper Full Bandwidth Jumper Reduced Bandwidth Test Point TP22 High Loss Receiver Signal Normal Operation DS40 Loss Receiver Signal Normal Operation
Control/Status Signal FAULT
DISABLE
DETECT
Table 1-28:
Module Connections
FPGA (U1) Description AC-coupled, LVDS, REFCLK pair. Receive pair. ML505/ML506: GTP0 GTP_X0Y4 ML507: GTX0 GTX_X0Y5 Transmit pair. ML505/ML506: GTP0 GTP_X0Y4 ML507: GTX0 GTX_X0Y5
Signal CLKBUF_Q0_P CLKBUF_Q0_N SFP_RX_P SFP_RX_N SFP_TX_P SFP_TX_N
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GTP/GTX Clocking Circuitry
Overview
jitter LVDS clock sources board provide high-quality reference clocks GTP/GTX transceivers. Different clock sources provided support each transceiver interfaces board. Table 1-29 provides summary clock sources. Table 1-29 provides summary clock sources. Table 1-29: Clock Sources (ML505/ML506)
Frequency GTP0 SATA1 SGMII PCIe
Notes:
Driven external PCIe source through PCIe edge connector (P21); driven internally.
Pairs GTP1 SATA2 Loopback Loopback Variable
Tile Location GTP_X0Y4 GTP_X0Y2 GTP_X0Y3 GTP_X0Y1
REFCLK Diff Pair Positive Negative
Table 1-30:
Clock Sources (ML507)
Frequency Tile Location GTX_X0Y5 GTX_X0Y3 GTX_X0Y4 GTX_X0Y2 REFCLK Diff Pair Positive Negative
Pairs GTX0 SATA1 SGMII PCIe
Notes:
GTX1 SATA2 Loopback Loopback Variable
Driven external PCIe source through PCIe edge connector (P21); driven internally.
Frequency Synthesizer SFP/SMA GTP/GTX Transceiver Clocking
Integrated Circuit Systems ICS843001-21 frequency synthesizer chip offers flexible, low-jitter clock generation GTP/GTX pair connected interfaces. ICS843001-21 connected 19.44-MHz crystal socketed 25-MHz oscillator (X5). switches (SW6) enable user select clock source frequency synthesis options generate number commonly used frequencies applications, such Gigabit Ethernet SONET (see Table 1-31, page 47). other frequencies, consult ICS843001-21 data sheet more information. 25-MHz oscillator socketed allow user change oscillator frequency entire range possible synthesized frequency outputs.
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Detailed Description
Table 1-31:
Configurations Clock Source Frequency Options
Input Clock SEL1 SEL0 (MHz) 19.44 19.44 19.44 19.44 Divider Divider Value Value (MHz) 622.08 622.08 622.08 622.08 Output Frequency (MHz) 155.52 77.76 622.08 311.04 62.5 156.25 Application SONET SONET SONET SONET Gigabit Ethernet Gigabit Ethernet Express SATA SATA XAUI/SRIO
Switch [1:8] Value
Notes:
Factory default setting. equates switch position. Fibre Channel support, Answer Record 24918.
native output ICS843001-21 LVPECL, resistor network present change voltage swing LVDS levels. LVDS output then multiplexed through Series coupling capacitors allow clock input FPGA common mode voltage.
SATA GTP/GTX Transceiver Clock Generation
Integrated Circuit Systems ICS844051-1 chip generates high-quality, low-jitter, 75-MHz 150-MHz LVDS clock from inexpensive 25-MHz crystal oscillator. This clock sent GTP/GTX transceiver driving SATA connectors. Jumper sets SATA GTP/GTX transceiver clock frequency (see Table 1-32). Series coupling capacitors also present allow clock input FPGA common mode voltage. Table 1-32: Configuration SATA GTP/GTX Clock Signals
Board Connection Jumper SATA Clock Frequency Jumper Jumper
SATA Clock Signal
SGMII Loopback GTP/GTX Transceiver Clock Generation
Integrated Circuit Systems ICS844021I chip generates high-quality, low-jitter, 125-MHz LVDS clock from inexpensive 25-MHz crystal oscillator. This clock sent GTPs driving SGMII onboard loopback interfaces. Series coupling capacitors also present allow clock input FPGA common mode voltage.
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Soft Touch Landing
Agilent Series soft touch landing available with logic analyzer. landing designed with Agilent E5404/06A 34-channel single-ended probe. soft touch landing shares some pins with header. Signals that user wants probe connected header signals specified Table 1-33. more information about soft touch connectors, www.agilent.com/find/softtouch. Table 1-33: Landing Signals Header
Header HDR1_2 HDR1_4 HDR1_10 HDR1_12 HDR2_36_SM_15_P HDR2_34_SM_15_N HDR1_22 HDR1_24 HDR1_30 HDR1_32 HDR1_38 HDR1_40 HDR1_46 HDR1_48 HDR1_50 HDR1_52 HDR1_58 HDR1_60 FPGA AE32 AG32 AK33 AJ32 AK32 AL34 AJ34 AM32 Number
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Detailed Description
Table 1-33:
Landing Signals Header (Cont'd)
Header HDR1_6 HDR1_8 HDR1_14 HDR1_16 HDR1_18 HDR1_20 HDR1_26 HDR1_28 HDR1_34 HDR1_36 HDR1_42 HDR1_44 HDR2_42_SM_14_N HDR2_44_SM_14_P HDR1_54 HDR1_56 HDR1_62 HDR1_64 FPGA AA34 AD32 AH34 AH32 AK34 AE34 AF34 AL33 AM33 AN34 AN33
Number
System Monitor
ML50x supports both dedicated auxiliary analog inputs Virtex-5 FPGA System Monitor block. pins shown Table 1-34, page dedicated pins, whereas VAUXP[x], VAUXN[x] represent user-selectable auxiliary analog input channels. ML50x layout pins designed using differential pairs anti-alias filtering close proximity FPGA recommended Virtex-5 FPGA System Monitor User Guide [Ref 14]. Please note that circuitry connected channels ML50x connected non-optimal fashion they implemented without anti-alias filtering FPGA. This tradeoff
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Chapter ML505/ML506/ML507 Evaluation Platform
made channels also used general-purpose connectors (see "10. Expansion Headers," page additional details). channels still available with System Monitor functions, they will attain performance level dedicated analog input noted Virtex-5 FPGA System Monitor User Guide. Access dedicated analog input pairs (VP/VN) provided through pins System Monitor Header (J9). Table 1-34. Virtex-5 FPGA System Monitor function built around 10-bit, 200-kSPS (kilosamples second) Analog-to-Digital Converter (ADC). When combined with number on-chip sensors, used measure FPGA physical operating parameters like on-chip power supply voltages temperatures. Access external voltages provided through dedicated analog-input pair (VP/VN) user selectable analog inputs, known auxiliary analog inputs (VAUXP[15:0], VAUXN[15:0]). System Monitor fully functional power measurement data accessed JTAG port pre-configuration. Xilinx ChipScopePro tool [Ref provides access System Monitor over JTAG port. System Monitor control logic implements some common monitoring features. example, automatic channel sequencer allows user-defined selection parameters automatically monitored, user-programmable averaging enabled ensure robust noise-free measurements. System Monitor also provides user-programmable alarm thresholds on-chip sensors. Thus, on-chip monitored parameter moves outside user-specified operating range, alarm logic output becomes active. addition monitoring onchip temperature user-defined applications, System Monitor issues special alarm called Over-Temperature (OT) FPGA temperature becomes critical 125°C). over-temperature signal deactivated when device temperature falls below userspecified lower limit. FPGA power-down feature enabled, FPGA enters power down when signal becomes active. FPGA powers again when alarm deactivated. additional information about System Monitor, consult Virtex-5 FPGA System Monitor User Guide [Ref 14]. Table 1-34 shows System Monitor connections. Table 1-34: System Monitor Connections
FPGA Header J9-10 Schematic Name FPGA_V_N External Input VAUXN[0] VAUXP[0] VAUXN[1] VAUXP[1] VAUXN[2] VAUXP[2] VAUXN[3] VAUXP[3] VAUXN[4] VAUXP[4]
AE34 AF34 AE33 AF33 AB33 AC33 AB32 AC32 AD34 AC34
J9-9
J4-42 J4-44 J4-46 J4-48 J4-58 J4-60 J4-54 J4-56 J4-50 J4-52
FPGA_V_P
HDR2_42_SM_14_N HDR2_44_SM_14_P HDR2_46_SM_12_N HDR2_48_SM_12_P HDR2_58_SM_4_N HDR2_60_SM_4_P HDR2_54_SM_13_N HDR2_56_SM_13_P HDR2_50_SM_5_N HDR2_52_SM_5_P
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ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
Detailed Description
Table 1-34:
System Monitor Connections (Cont'd)
FPGA AA34 AA33 Header J6-30 J6-26 J4-38 J4-40 J4-34 J4-36 J4-30 J4-32 J4-26 J4-28 J4-22 J4-24 J4-18 J4-20 J4-14 J4-16 J4-10 J4-12 J4-6 J4-8 J4-2 J4-4 Schematic Name HDR1_30 HDR1_26 HDR2_38_SM_6_N HDR2_40_SM_6_P HDR2_34_SM_15_N HDR2_36_SM_15_P HDR2_30_DIFF_3_N HDR2_32_DIFF_3_P HDR2_26_SM_11_N HDR2_28_SM_11_P HDR2_22_SM_10_N HDR2_24_SM_10_P HDR2_18_DIFF_2_N HDR2_20_DIFF_2_P HDR2_14_DIFF_1_N HDR2_16_DIFF_1_P HDR2_10_DIFF_0_N HDR2_12_DIFF_0_P HDR2_6_SM_7_N HDR2_8_SM_7_P HDR2_2_SM_8_N HDR2_4_SM_8_P
External Input VAUXN[5] VAUXP[5] VAUXN[6] VAUXP[6] VAUXN[7] VAUXP[7] VAUXN[8] VAUXP[8] VAUXN[9] VAUXP[9] VAUXN[10] VAUXP[10] VAUXN[11] VAUXP[11] VAUXN[12] VAUXP[12] VAUXN[13] VAUXP[13] VAUXN[14] VAUXP[14] VAUXN[15] VAUXP[15]
ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
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Chapter ML505/ML506/ML507 Evaluation Platform
Buses
board supports four buses; Main, Video, SFP, DDR2. Each buses pull-ups signals. Table 1-35 describes devices attached each four buses. Table 1-35: Connections
Device EEPROM Controller Clock Clock Expansion Cage Output: Codec Output: Connector Input: Codec DDR2 DDR2 Video Main Name Address 0x50 0x2C 0x6A 0x6A 0x76 0x4C 0x50 FPGA Pins
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ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
Configuration Options
Configuration Options
FPGA ML50x Evaluation Platform configured following major devices: Xilinx download cable (JTAG) System controller (JTAG) Platform Flash PROMs Linear Flash memory Flash memory
following section provides overview possible ways FPGA configured.
JTAG (Xilinx Download Cable System Controller) Configuration
FPGA, Platform Flash PROMs, CPLD configured through JTAG port. JTAG chain board illustrated Figure 1-9.
Platform Flash Memories
Connector
CPLD
System Controller
TSTTDI CFGTDO
FPGA
Expansion
UG347_08_112706
TSTDO CFGTDI
Figure 1-9:
JTAG Chain
chain starts connector goes through Platform Flash PROMs, CPLD, System controller, FPGA, optional extension chain expansion card. Jumper determines JTAG chain should extended expansion card. JTAG chain used program FPGA access FPGA hardware software debug. JTAG chain also used program Platform Flash PROM CPLD. JTAG connection JTAG chain allows host computer download bitstreams FPGA using iMPACT software tool. also allows debug tools such ChipScope Analyzer software debugger access FPGA. System controller also program FPGA through JTAG port. Using inserted CompactFlash card, configuration information stored played FPGA. System controller supports eight configuration images that selected using three configuration address switches. Under FPGA control, System chip instructed reconfigure eight configuration images. configuration mode should 101. Jumper should exclude expansion card from JTAG chain, switch SW3, should System configuration. When correctly, System controller programs FPGA upon power-up CompactFlash card present whenever CompactFlash card inserted.
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Chapter ML505/ML506/ML507 Evaluation Platform
Pressing System reset button also causes System controller program FPGA CompactFlash card present.
Platform Flash PROM Configuration
Platform Flash PROMs also used program FPGA. Platform Flash PROM hold configuration images four with compression), which selectable least significant bits configuration address switches. board wired Platform Flash PROM download bitstreams Master Serial, Slave Serial, Master SelectMAP (parallel), Slave SelectMAP (parallel) modes. Using iMPACT tool program Platform Flash PROM, user option select which four modes programming FPGA. configuration mode switches board must match programming method being used Platform Flash PROM. When correctly, Platform Flash PROM programs FPGA upon power-up whenever Prog button pressed.
Linear Flash Memory Configuration
Data stored linear flash used program FPGA (BPI mode). four configuration images theoretically supported. configuration mode switches board must BPI_up BPI_down. When correctly, FPGA programmed upon power-up whenever Prog button pressed.
Flash Memory Configuration
Data stored used program FPGA. configuration mode switches must configuration. When correctly, FPGA programmed upon power-up whenever Prog button pressed.
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ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
Appendix
Board Revisions
This appendix describes major differences ML50x platforms (Table A-1). Table A-1:
Platform
ML50x Platform Details
Device Package Product Revision 0483688-03 0483688-01 0483688-02 0483729-03 0483729-01 0483729-02 0483906-01 Description ML505 platform that supports RocketIO transceivers. ML506 platform that supports RocketIO transceivers ML507 platform that supports RocketIO transceivers.
XC5VLX50T-1C
ML505
1FFG1136 1FFG1136 1FFG1136 1FFG1136
XC5VLX50T-1CES XC5VSX50T-1C
ML506
XC5VSX50T-1CES
ML507
Notes:
XC5VFX70T-1CES
1FFG1136
Where AVCC_PLL voltage 1.2V. (R176 2.43K R177 4.99K Where AVCC_PLL voltage 1.0V. (R176 1.13K R177 4.53K
ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
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Appendix
Programming Clock Chip
Overview
ML50x evaluation boards feature Integrated Device Technology (IDT) 3.3V EEPROM Programmable Clock Generator that pre-programmed factory. event chip programming changed, instructions this appendix show return clock chip factory default settings using following equipment: Xilinx download cable JTAG flying wires
Downloading ML50x Board
Connect Xilinx download cable board using flying leads connected jumper (Figure B-1).
Prog
3.3V
UG347_apdx_a_02_020807
Figure B-1: Click Start iMPACT. Click Boundary Scan.
IDT5V9885 JTAG Connector
Right-click Xilinx Device. Locate file (ML50X_clock_setup.svf example shown Figure B-2, page click Open. Note: ML50X_clock_setup.svf file available ML50x product page. Right-click device select Execute XSVF/SVF.
ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
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UG347_apdx_a_01_112706
Figure B-2:
Programming IDT5V9885 ML50x Using iMPACT
finish programming chip, cycle power turning board power switch. After turning board back verify that clock frequencies correct.
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ML505/ML506/ML507 Evaluation Platform UG347 (v3.1) November 2008
Appendix
References
Documents specific ML50x Evaluation Platform:
UG348, ML505/ML506/ML507 Getting Started Tutorial.
UG349, ML505/ML506/ML507 Reference Design User Guide. Resources: ML505, ML506, ML507.
Documents supporting Virtex-5 FPGAs:
DS100, Virtex-5 FPGA Family Overview. DS202, Virtex-5 FPGA Data Sheet: Switching Characteristics. UG190, Virtex-5 FPGA User Guide. UG200, Embedded Processor Block Virtex-5 FPGAs Reference Guide. UG196, Virtex-5 FPGA RocketIO Transceiver User Guide. UG198, Virtex-5 FPGA RocketIO Transceiver User Guide.
UG194, Virtex-5 FPGA Tri-Mode Ethernet Media Access Controller User Guide. UG197, Virtex-5 FPGA Integrated Endpoint Block User Guide Express Designs. UG193, XtremeDSP Design Considerations. UG191, Virtex-5 FPGA Configuration User Guide. UG192, Virtex-5 FPGA System Monitor User Guide. UG195, Virtex-5 FPGA Packaging Pinout Specification.
Xilinx Memory Solutions page offers following material supporting Memory Interface Generator (MIG) tool:
WP260, Memory Interfaces Made Easy with Xilinx FPGAs Memory Interface Generator. UG086, Xilinx Memory Interface Generator (MIG) User Guide (for registered users). Demos Demand, Memory Interface Solutions with Xilinx FPGAs. Xilinx Support Memory Interface Resources (for registered users).
Resources Design:
UG203, Virtex-5 FPGA Designer's Guide. UG112, Device Package User Guide. UG195, Virtex-5 FPGA Package Pinout Specification. Xilinx Technology Solutions page design considerations:
Memory Solutions Signal Integrity Power Solutions
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Xilinx ChipScope Tool page offers following material supporting ChipScope Analyzer:
UG029, ChipScope Software Cores User Guide. UG213, ChipScope Serial Toolkit User Guide.
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