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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
DS264 June 2009
Product Specification
Introduction
LogiCOREIP Ethernet 1000BASE-X PCS/PMA SGMII core provides flexible solution connection Ethernet Media Access Controller (MAC) other custom logic supports standards operation that dynamically selected: 1000BASE-X Physical Coding Sublayer (PCS) Physical Medium Attachment (PMA) operation, defined IEEE 802.3 standard GMII Serial-GMII (SGMII) bridge, defined Serial-GMII specification (ENG-46158)
Virtex-6, Virtex-5 Virtex-4 Spartan®-3, Spartan-3E Spartan-3A/3A Spartan-6 Performance
LogiCORE Facts
Core Specifics
Supported FPGA Family1
Speed Grade 1.25 Gbps
Core Resources
Slices LUTs BUFG RocketIO Transceiver Block RAMs Designed IEEE802.3 Hardware Verified Documentation Design File Formats
140-11002 170-10902 180-9402 0-32 2-42 0-12 0-22
Core Highlights Simulation Only Evaluation Hardware Evaluation Provided with Core Product Specification, User Guide Getting Started Guide Netlist Example Design Demonstration Test Bench Scripts User Constraints File (.ucf)
Features
1000BASE-X Physical Coding Sublayer (PCS) designed IEEE 802.3 specification following: 1000BASE-X Physical Medium Attachment (PMA) using following: Virtex®-6 FPGA RocketIOGTX Transceiver Virtex-5 FPGA RocketIO ceiver Trans-
Virtex-4 FPGA RocketIO Multi-Gigabit Transceiver (MGT) 1000BASE-X parallel Ten-Bit-Interface (TBI) connection external SERDES4 Configured monitored through serial MDIO Interface (MII Management), which optionally omitted from core. Supports 1000BASE-X Auto-Negotiation information exchange with link partner, which optionally omitted from core Internal external GMII4 custom logic Alternative Serial-GMII (SGMII) functionality connection external PHYs Available under terms SignOnce Site License
Constraints File Example Designs
Supported Xilinx® Tools Simulation Tools3
1000BASE-X PCS/PMA using RocketIO transceiver 1000BASE-X with Ten-Bit Interface4 GMII SGMII Bridge4 Demo Test Environment Design Tool Requirements VHDL and/or Verilog ISE® v11.2, 11.2 ModelSim v6.4b above Cadence v8.1-s009 above Synopsys 2008.09 above Voltage Requirements4
supported family configurations Table precise number depends user configuration; Table Virtex-6, Virtex-5, Virtex-4 Spartan-6 device designs incorporating device-specific RocketIO transceiver require Verilog LRM-IEEE 1364-2005 encryption-compliant simulator. VHDL simulation, mixed license required. Virtex-6 devices support GMII 2.5V only. Please Virtex-6 FPGA Data Sheet: Switching Characteristics more information. Virtex-5, Virtex-4 Spartan-3 devices support GMII 3.3V lower.
2004-2009 Xilinx, Inc. XILINX, Xilinx logo, Virtex, Spartan, other designated brands included herein trademarks Xilinx United States other countries. other trademarks property their respective owners.
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Applications
Typical applications Ethernet 1000BASE-X PCS/PMA SGMII core include following: Ethernet 1000BASE-X Serial-GMII
Ethernet 1000BASE-X
Figure illustrates typical application Ethernet 1000BASE-X PCS/PMA SGMII core with core operating 1000BASE-X standard using device-specific RocketIO transceiver provide Physical Coding Sublayer (PCS) Physical Medium Attachment (PMA) sublayers 1-Gigabit Ethernet. connected external off-the-shelf GBIC optical transceiver complete Ethernet port. GMII Ethernet 1000BASE-X PCS/PMA connected embedded Ethernet Media Access Controller (MAC), example, Xilinx Tri-Mode Ethernet core.
Figure x-ref
Xilinx FPGA
Ethernet 1000BASE-X PCS/PMA SGMII Core RocketIO Transceiver TXP/TXN
User Logic (Ethernet Media Access Controller)
GBIC Optical Transceiver Optical Fiber
Internal GMII
RocketIO Interface
RXP/RXN
Figure Typical 1000BASE-X Application
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Serial-GMII
Figure illustrates typical application Ethernet 1000BASE-X PCS/PMA SGMII core, which shows core providing GMII SGMII bridge using device-specific RocketIO transceiver provide serial interface. device-specific RocketIO transceiver connected external off-the-shelf Ethernet device that also supports SGMII. (This tri-mode providing 10BASE-T, 100BASE-T, 1000BASE-T operation.) GMII Ethernet 1000BASE-X PCS/PMA SGMII core connected embedded Ethernet MAC, example, Xilinx Tri-Mode Ethernet core.
Figure x-ref
SGMII
Xilinx FPGA
Ethernet 1000BASE-X PCS/PMA SGMII LogiCORE RocketIO TXP/TXN Internal GMII RocketIO Interface BASE-T 100BASE-T 1000BASE-T Twisted Copper Pair
User Logic (Ethernet Media Access Controller)
RXP/RXN
Figure Typical SGMII Mode Application
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Overview Ethernet Architecture
Figure illustrates 1-Gigabit Ethernet sublayers provided this core, which part Ethernet architecture. part this architecture, from right, defined IEEE 802.3 specification. This figure also shows where supported interfaces into architecture.
Figure x-ref
GMII SGMII FIFO
RocketIO Serial
Figure Overview Ethernet Architecture
Ethernet Media Access Controller (MAC) defined IEEE 802.3, clauses responsible Ethernet framing protocols error detection these frames. independent connect type physical layer device.
GMII SGMII
Gigabit Media Independent Interface (GMII), parallel interface connecting physical sublayers (PCS, PMA, PMD), defined IEEE 802.3, clause operating speed Gbps, full GMII used; operating speed Mbps Mbps, GMII replaced with Media Independent Interface (MII) that uses subset GMII signals. Serial-GMII (SGMII) alternative interface GMII/MII that converts parallel interface GMII/MII into serial format capable carrying traffic speeds Mbps, Mbps, Gbps. This radically reduces count this reason often preferred designers. SGMII specification closely related 1000BASE-X sublayers, which enables offered this core.
Physical Coding Sublayer (PCS) 1000BASE-X operation defined IEEE 802.3, clauses performs following: Encoding (and decoding) GMII data octets form sequence ordered sets 8B10B encoding (and decoding) sequence ordered sets 1000BASE-X Auto-Negotiation information exchange with link partner
Interface
Ten-Bit-Interface (TBI), defined IEEE 802.3 clause parallel interface connecting transfers 8B10B encoded sequence-ordered sets. should used with external SERDES device.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Physical Medium Attachment
Physical Medium Attachment (PMA) 1000BASE-X operation, defined IEEE 802.3 clause performs following: Serialization (and deserialization) code-groups transmission (and reception) underlying serial Recovery clock from 8B/10B-coded data supplied device-specific RocketIO transceivers provide serial interface required connect Physical Medium Dependent (PMD).
Physical Medium Dependent
sublayer defined IEEE 802.3 clause 1000BASE-LX 1000BASE-SX (long short wavelength laser). This type provided external GBIC optical transceivers. alternative 1000BASE-CX (short-haul copper) defined IEEE 802.3 clause
Core Overview
Using Ethernet 1000BASE-X PCS/PMA SGMII core with device-specific RocketIO transceiver provides functionality implement 1000BASE-X sublayers. Alternatively, used provide GMII SGMII bridge. core interfaces device-specific RocketIO transceiver, which provides some layer functionality such 8B/10B encoding/decoding, SERDES, clock recovery. Figure illustrates remaining sublayer functionality major functional blocks core. description functional blocks signals provided subsequent sections.
Figure x-ref
LogiCORE Ethernet 1000BASE-X PCS/PMA SGMII Core
Transmit Engine
GMII
RocketIO Transeiver
RocketIO Block
GMII Block
Optional Auto-Negotiation
Sublayer
Receive Engine Synchronization
MDIO Interface
Optional Management
Figure Ethernet 1000BASE-X PCS/PMA SGMII Core using device-specific RocketIO Transceiver
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
GMII Block
core provides client-side GMII. This used internal interface connection embedded other custom logic. Alternatively, core GMII routed device IOBs provide off-chip GMII. Virtex-6 devices support GMII 2.5V only. Please Virtex-6 FPGA Data Sheet: Switching Characteristics more information; Virtex-5, Virtex-4, Spartan-6 Spartan-3 devices support GMIII 3.3V lower.
Transmit Engine
transmit engine converts GMII data octets into sequence ordered sets implementing state diagrams IEEE 802.3 (Figures 36-5 36-6).
Receive Engine Synchronization
synchronization process implements state diagram IEEE 802.3 (Figure 36-9). receive engine converts sequence ordered sets GMII data octets implementing state diagrams IEEE 802.3 (Figures 36-7a 36-7b).
Optional Auto-Negotiation Block
IEEE 802.3 clause describes 1000BASE-X Auto-Negotiation function that allows device advertise supported modes operation device remote link segment (link partner), detect corresponding operational modes that link partner advertising. Auto-Negotiation controlled monitored through Management Registers.
Optional Management Registers
Configuration status core, including access from optional Auto-Negotiation function, performed with 1000BASE-X Management Registers defined IEEE 802.3 clause These registers accessed through serial Management Data Input/Output Interface (MDIO), defined IEEE 802.3 clause were externally connected PHY. Management Registers omitted from core when core performing 1000BASE-X standard. this situation, configuration status made possible using alternative configuration vector status signal. When core performing SGMII standard, Management Registers become mandatory information registers takes different interpretation. LogiCORE Ethernet 1000BASE-X PCS/PMA SGMII User Guide.
RocketIO Transceiver Interface Block
interface block enables core connect device-specific RocketIO transceiver.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Ethernet 1000BASE-X PCS/PMA SGMII Core with Ten-Bit Interface
When used with TBI, Ethernet 1000BASE-X PCS/PMA SGMII core provides functionality implement 1000BASE-X sublayer, provide SGMII support with external SERDES.
Figure x-ref
LogiCORE Ethernet 1000BASE-X PCS/PMA SGMII Core
Transmit Engine
8B/10B Encoder
GMII Block
Block
GMII
IOBs
Optional Atuo-negotiation
Sublayer
Receive Engine Synchronization
8B/10B Decoder
Elastic Buffer
MDIO Interface
Optional Management
Figure Functional Block Diagram Ethernet 1000BASE-X PCS/PMA SGMII Core with
optional used place device-specific RocketIO transceiver provide parallel interface connection external SERDES device, providing alternative implementation families without device-specific RocketIO transceivers. this implementation, additional logic blocks required core replace some device-specific RocketIO transceiver functionality. These blocks surrounded dashed line (see Figure Other blocks identical those previously defined. Virtex-6 devices support 2.5V only. Please Virtex-6 FPGA Data Sheet: Switching Characteristics more information. Virtex-5, Virtex-4, Spartan-6 Spartan-3 devices support 3.3V lower. 8B/10B Encoder 8B10B encoding, defined IEEE 802.3 (Tables 36-1a 36-1e Table 36-2), implemented Block SelectRAMmemory, configured ROM, used large look-up table. 8B/10B Decoder 8B10B decoding, defined IEEE 802.3 (Tables 36-1a 36-1e Table 36-2), implemented Block SelectRAM memory, configured ROM, used large look-up table. Receiver Elastic Buffer Receiver Elastic Buffer enables 10-bit parallel data, received from sublayer synchronously receiver clocks, transferred onto core internal clock domain. Receiver Elastic Buffer asynchronous FIFO implemented internal RAM. operation Receiver Elastic Buffer attempt maintain constant occupancy inserting removing Idle sequences necessary. This causes corruption frames data.
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Block core provides interface, which should routed device IOBs provide off-chip TBI. Ethernet 1000BASE-X PCS/PMA SGMII User Guide more information.
Interface Descriptions
ports core internal connections FPGA fabric. example design, provided both VHDL Verilog, delivered with core. Where appropriate, example design connects core device-specific RocketIO transceiver and/or adds IBUFs, OBUFs, flip-flops external signals GMII TBI. IOBs added remaining unconnected ports take example design through Xilinx implementation software. clock management logic placed this example design allowing more flexibility implementation; example, designs using multiple cores. information about example designs, Ethernet 1000BASE-X PCS/PMA SGMII Getting Started Guide.
GMII Signal Definition
Table defines GMII-side interface signals common parameterizations core. These typically attached Ethernet MAC, either off-chip internally integrated. example design delivered with core connects these signals IOBs provide place-and-routable example.
Table GMII Interface Signal Pinout
Signal
gmii_txd[7:0] gmii_tx_en gmii_tx_er gmii_rxd[7:0] gmii_rx_dv gmii_rx_er gmii_isolate
Direction
Input Input Input Output Output Output Output
Clock Domain
Description
GMII Transmit data from MAC. GMII Transmit control signal from MAC. GMII Transmit control signal from MAC. GMII Received data MAC.
note
GMII Received control signal MAC. GMII Received control signal MAC. Tri-state control GMII Isolation. Only when implementing External GMII illustrated example design HDL.
Note: Signals synchronous cores internal reference clock; userclk2 when used with device-specific RocketIO transceiver, gtx_clk when used with TBI.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
GMII Usage Example
Standard Frame Transmission Figure illustrates timing normal outbound frame transfer. This shows that Ethernet frame preceded 8-byte preamble field completed with 4-byte frame check sequence (FCS) field (IEEE 802.3 clause This driven core transmitter client logic (usually connected other GMII). treats value placed gmii_txd[7:0] within gmii_tx_en assertion window data.
Figure x-ref
gmii_txd[7:0] preamble
gmii_tx_en
gmii_tx_er
note Table
Figure GMII Standard Frame Transmission
Standard Frame Reception Figure illustrates timing normal inbound frame transfer. This shows that Ethernet frame reception proceeded preamble field; IEEE 802.3 specification allows seven preamble bytes that proceed Start Frame Delimiter (SFD) lost (IEEE 802.3 clause 35). will always present well-formed frames. This frame presented core receiver client logic (usually connected other GMII).
Figure x-ref
gmii_rxd[7:0] preamble
gmii_rx_dv
gmii_rx_er
note Table
Figure GMII Standard Frame Reception
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Common Signal Definition
Table defines signals common parameterizations core.
Table Other Common Signals
Signal
reset
Direction
Input
Clock Domain
Description
Asynchronous reset entire core. Active High. Signal direct from sublayer indicating presence light detected optical receiver. '1,' this indicates that optical receiver detected light. this indicates absence light. unused this signal should enable correct operation core.
signal_detect
Input
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Table Other Common Signals (Continued)
Signal
Direction
Clock Domain
Bit[0]: Link Status
Description
This signal indicates status link. When high, link valid: synchronization link been obtained Auto-Negotiation present enabled) successfully completed. When low, valid link been established. Either link synchronization failed Auto-Negotiation present enabled) failed complete. When auto-negotiation enabled this signal identical Status Register 1.2: Link Status. When auto-negotiation disabled this signal identical status_vector Bit[1]. Bit[1]: Link Synchronization This signal indicates state synchronization state machine (IEEE802.3 figure 36-9) which based reception valid 8B10B code groups. This signal similar Bit[0] (Link Status), qualified with Auto-Negotiation. When high, link synchronization been obtained synchronization state machine, sync_status=OK. When low, synchronization failed. status_vector[7:0] Output note Bit[2]: RUDI(/C/) core receiving ordered sets (Auto-Negotiation Configuration sequences). Bit[3]: RUDI(/I/) core receiving ordered sets (Idles) Bit[4]: RUDI(INVALID) core received invalid data while receiving/C/ ordered set. Bit[5]: RXDISPERR core received running disparity error during 8B10B decoding function. Bit[6]: RXNOTINTABLE core received code group which recognized from 8B10B coding tables. Bit[7]: Link Status (SGMII mode only) When operating SGMII mode, this represents link status external device attached other SGMII link (high indicates that obtained link with link partner; indicates that linked with link partner). When operating 1000BASE-X mode this will remain should ignored
Note: Signals synchronous core internal reference clock; userclk2 when used with device-specific RocketIO transceiver; gtx_clk when used with TBI.
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Optional Management Signal Definition
Table describes optional MDIO interface signals core used access Management Registers. These signals typically connected MDIO port device, either off-chip internally integrated core.
Table Optional MDIO Interface Signal Pinout
Signal
mdio_in mdio_out mdio_tri phyad[4:0]
Direction
Input Input Output Output Input
Clock Domain
Description
Management clock (2.5 MHz) Input data signal Output data signal Output tri-state driver mdio_out. Active Physical Address Management register set. expected that this signal will tied logical value.
Alternative Management I/F: Configuration Vector Definition
Table describes alternative optional MDIO; optional configuration vector.
Table Optional Configuration Status Vectors
Signal
Direction
Clock Domain
Description
Bit[0]: Reserved (currently unused) Bit[1]: Loopback Control When core with device-specific RocketIO transceiver used, this places core into internal loopback mode. With version, connected ewrap. When this indicates external module enter loopback mode. Bit[2]: Power Down When Virtex-6, Virtex-5 Spartan-6 FPGA RocketIO transceivers used '1,' device-specific RocketIO transceiver placed power state. reset must applied clear. With version this unused. Bit[3]: Isolate When to'1,' GMII should electrically isolated. When '0,' normal operation enabled.
configuration_vector[3:0]
Input
note
Note: Signals synchronous core internal reference clock; userclk2 when used with device-specific RocketIO transceiver; gtx_clk when used with TBI.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Optional 1000BASE-X PCS/PMA SGMII) using RocketIO Transceiver Signal Definition
Table defines optional interface device-specific RocketIO transceiver. core connected device-specific RocketIO transceiver example design delivered with core. complete description device-specific RocketIO interface, RocketIO transceiver User Guide specific your device. (For RocketIO User Guide information, References [6], [7], this document.)
Table Optional RocketIO Transceiver Interface Pinout
Signal
Direction
Clock Domain
userclk2
Description
Reset signal issued core device-specific RocketIO transceiver receiver path. Connect RXRESET signal RocketIO transceiver. Reset signal issued core device-specific RocketIO transceiver transmitter path. Connect TXRESET signal RocketIO transceiver. Also connected TXUSRCLK RXUSRCLK device-specific RocketIO transceiver. Also connected TXUSRCLK2 RXUSRCLK2 device-specific RocketIO transceiver. used derive userclk userclk2. This implemented design example delivered with core. core will this input hold device-specific RocketIO transceiver reset until obtains lock.
mgt_rx_reset
Output
mgt_tx_reset
Output
userclk2
userclk userclk2
Input Input
dcm_locked
Input
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Table Optional RocketIO Transceiver Interface Pinout (Continued)
Signal
rxbufstatus[1:0] rxchariscomma rxcharisk rxclkcorcnt[2:0] rxdata[7:0] rxdisperr rxnotintable rxrundisp txbuferr powerdown txchardispmode txchardispval txcharisk txdata[7:0]
Direction
Input Input Input Input Input Input Input Input Input Output Output Output Output Output
Clock Domain
userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2 userclk2
Description
Connects RocketIO transceiver signal same name.
enablealign
Output
userclk2
Allow transceivers serially realign comma character. Connect ENMCOMMAALIGN ENPCOMMAALIGN device-specific RocketIO transceiver.
Note: When core used with device-specific RocketIO transceiver, userclk2 used reference clock entire core.
Optional 1000BASE-X with Signal Definition
Table defines optional signals that used alternative device-specific RocketIO transceiver interface. appropriate example design delivered with core connects these signals IOBs provide external suitable connection off-chip SERDES device. Table Optional Interface Signal Pinout Signal
gtx_clk tx_code_group[9:0] loc_ref
Direction
Input Output Output
Clock Domain
gtx_clk
Description
Clock signal MHz. Tolerance must within IEEE 802.3 specification. 10-bit parallel transmit data Sublayer (SERDES). Causes sublayer clock recovery unit lock pma_tx_clk. This signal currently tied Ground. When '1,' indicates external SERDES device enter loopback mode. When '0,' this indicates normal operation. 10-bit parallel received data from Sublayer (SERDES). This synchronous pma_rx_clk0.
ewrap
Output
gtx_clk
rx_code_group0[9:0]
Input
pma_rx_clk
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Table Optional Interface Signal Pinout (Continued) Signal
rx_code_group1[9:0] pma_rx_clk
Direction
Input Input
Clock Domain
pma_rx_clk1
Description
10-bit parallel received data from Sublayer (SERDES). This synchronous pma_rx_clk1. Received clock signal from Sublayer (SERDES) 62.5 MHz. Received clock signal from Sublayer (SERDES) 62.5 MHz. This degrees phase with pma_rx_clk0. Enables Sublayer perform comma realignment. This driven from Receive Engine during Loss-Of-Sync state.
pma_rx_clk1
Input
en_cdet
Output
gtx_clk
Note: When core used with TBI, gtx_clk used reference clock entire core.
Optional Auto-Negotiation Signal Definition
Table defines signals when optional Auto-Negotiation present.
Table Optional Auto-Negotiation Interface Signal Pinout
Signal
Direction
Clock Domain
Description
Used configure duration Auto-Negotiation function Link Timer. duration this timer binary number input into this port multiplied 4096 clock periods reference clock ns). expected that this signal will tied logical value. This port replaced when using dynamic switching mode. Active high interrupt signal completion Auto-Negotiation cycle. This interrupt enabled/disabled cleared writing appropriate Management Register. more information, Ethernet 1000BASE-X PCS/PMA SGMII User Guide.
link_timer_value[8:0]
Input
note
an_interrupt
Output
note
Note: Signals synchronous core internal reference clock, userclk2 when core used with device-specific RocketIO transceiver, gtx_clk when core used with TBI.
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Optional Dynamic Switching Signal Pinout
Table describes additional signals present when core generated with optional Dynamic Switching capability between 1000BASE-X SGMII standards.
Table Optional Dynamic Standard Switching Signals
Signal
Direction
Clock Domain
Description
Used configure duration Auto-Negotiation Link Timer period when performing 1000BASE-X standard. duration this timer binary number input into this port multiplied 4096 clock periods reference clock ns). expected that this signal will tied logical value. Used configure duration Auto-Negotiation Link Timer period when performing SGMII standard. duration this timer binary number input into this port multiplied 4096 clock periods reference clock ns). expected that this signal will tied logical value. Used reset default select standard. expected that this signal will tied logical value: signals that core will come reset operating 1000BASE-X; signals that core will come reset operating SGMII. Note: standard following reset using MDIO Management.
link_timer_basex[8:0]
Input
userclk2
link_timer_sgmii[8:0]
Input
userclk2
basex_or_sgmii
Input
userclk2
Core Latency
standalone core does meet latency requirements specified IEEE 802.3 latency Elastic Buffers both device-specific RocketIO transceiver versions. However, core used backplane other applications where strict adherence IEEE latency specification requirement. Where strict adherence IEEE 802.3 specification required, core used with Ethernet core which within IEEE specified latency sublayer. example, when core connected Xilinx Tri-Mode Ethernet core, system whole compliant with overall IEEE 802.3 latency specifications. more information about latency, Ethernet 1000BASE-X PCS/PMA SGMII User Guide.
Verification
Ethernet 1000BASE-X PCS/PMA SGMII core been verified with extensive simulation hardware verification.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Simulation
highly parameterizable transaction-based test bench used test core. tests included following: Register access Loss synchronization Auto-negotiation error handling Frame transmission error handling Frame reception error handling Clock compensation elastic buffers
Hardware Verification
core been tested variety hardware test platforms Xilinx represent variety parameterizations, including following: core used with device-specific RocketIO transceiver performing 1000BASE-X standard been tested with Xilinx Tri-Mode Ethernet core, which follows architecture shown Figure page test platform built around these cores, including back-end FIFO capable performing simple ping function, test pattern generator. Software running embedded PowerPC® processor provided access configuration status registers. Version this core taken University Hampshire Interoperability (UNH IOL) where conformance interoperability testing performed. core used with device-specific RocketIO transceiver performing SGMII standard been tested with LogiCORE Tri-Mode Ethernet core. This connected external capable performing 10BASE-T, 100BASE-T, 1000BASE-T, system tested three speeds. This follows architecture shown Figure page also includes PowerPC-based processor test platform described previously.
Family Support
Table Family Support 1000BASE-X PCS/PMA SGMII Core
LogiCORE Functionality 1000BASE-X GMII SGMII Bridge 1000BASE-X SGMII Standards with Dynamic Switching Using RocketIO Transceiver Supported Supported Supported Supported supported supported supported
Device Family
With
Using RocketIO Transceiver Supported Supported Supported Supported supported supported supported
With
Using RocketIO Transceiver Supported Supported Supported Supported supported supported supported
With
Virtex-6 Virtex-5 Virtex-4 Spartan-6 Spartan-3 Spartan-3E Spartan-3A
Supported Supported Supported Supported Supported Supported Supported
Supported Supported Supported Supported Supported Supported Supported
Supported Supported Supported Supported Supported Supported Supported
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Device Utilization
Virtex-6, Virtex-5 Spartan-6 device families contain input LUTs; other families contain four input LUTs. this reason, device utilization listed separately. following more information: "Virtex-6, Virtex-5 Spartan-6 Devices" page "Other Device Families" page
Virtex-6, Virtex-5 Spartan-6 Devices
Tables through provide approximate utilization figures various core options when single instance core instantiated Virtex-5 device. Utilization figures obtained implementing block-level wrapper core. This wrapper part example design connects core selected physical interface. BUFG Usage BUFG usage does consider multiple instantiations core, where clock resources often shared. BUFG usage does include reference clock required IDELAYCTRL. This clock source shared across entire device core specific.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
1000BASE-X
Table Device Utilization 1000BASE-X Standard
Parameter Values Device Resources
Physical Interface Rocket
MDIO Interface
AutoNegotiation N/A1 N/A1
Slices
LUTs
Block RAMs
BUFGs
DCMs
Auto-negotiation only available when MDIO Interface selected. These figures with transceivers: transceivers require three BUFGs DCM. Only BUFGs required (refer User Guide).
SGMII Bridge
Table Device Utilization GMII SGMII Bridge
Parameter Values Device Resources
Physical Interface Rocket
MDIO Interface
AutoNegotiation N/A1 N/A1
Slices
LUTs
Block RAMs
BUFGs
DCMs
Auto-negotiation only available when MDIO Interface selected. These figures with transceivers: transceivers require three BUFGs DCM. Only BUFGs required (refer User Guide).
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
1000BASE-X SGMII Standards with Dynamic Switching
Table Device Utilization 1000BASE-X SGMII Standards with Dynamic Switching
Parameter Values Device Resources
Physical Interface Rocket
MDIO Interface
AutoNegotiation N/A1 N/A1
Slices
LUTs
Block RAMs
BUFGs
DCMs
Auto-negotiation only available when MDIO Interface selected. These figures with transceivers: transceivers require three BUFGs DCM. Only BUFGs required (refer User Guide).
Other Device Families
Tables through provide approximate utilization figures various core options when single instance core instantiated Virtex-4 device. Other families have similar utilization figures, except indicated. Utilization figures obtained implementing block-level wrapper core. This wrapper part example design connects core selected physical interface. When physical interface Virtex-4 FPGA RocketIO transceiver, utilization figures include GT11 Calibration blocks GT11 initialization/reset circuitry. BUFG Usage BUFG usage does consider multiple instantiations core, where clock resources often shared.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
1000BASE-X
Table Device Utilization 1000BASE-X Standard
Parameter Values Device Resources
Physical Interface Rocket
MDIO Interface
AutoNegotiation N/A1 N/A1
Slices
LUTs
Block RAMs
BUFGs
DCMs
Auto-negotiation only available when MDIO Interface selected. Virtex-4 devices, this includes clock shared between Calibration Blocks GT11 Dynamic Reconfiguration Port (DRP). Only BUFGs required (refer User Guide). Spartan-3, Spartan-3E Spartan-3A devices require DCMs meet setup hold times.
SGMII Bridge
Table Device Utilization GMII SGMII Bridge
Parameter Values Device Resources
Physical Interface Rocket
MDIO Interface
AutoNegotiation N/A1 N/A1
Slices
LUTs
Block RAMs
BUFGs
DCMs
Auto-negotiation only available when MDIO Interface selected. Virtex-4 devices, this includes clock shared between Calibration Blocks GT11 Dynamic Reconfiguration Port (DRP). Only BUFGs required (refer User Guide). Spartan-3, Spartan-3E Spartan-3A devices require DCMs meet setup hold times.
DS264 June 2009 Product Specification
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
1000BASE-X SGMII Standards with Dynamic Switching
Table Device Utilization 1000BASE-X SGMII Standards with Dynamic Switching
Parameter Values Device Resources
Physical Interface Rocket
MDIO Interface
AutoNegotiation N/A1 N/A1
Slices
LUTs
Block RAMs
BUFGs
DCMs
1100
1090
Auto-negotiation only available when MDIO Interface selected. Virtex-4 devices, this includes clock shared between Calibration Blocks GT11 Dynamic Reconfiguration Port (DRP). Only BUFGs required (refer User Guide). Spartan-3, Spartan-3E Spartan-3A devices require DCMs meet setup hold times.
References
Virtex-6 FPGA User Guide (Virtex-6 FPGA product page) Virtex-5 FPGA User Guide (UG190) Virtex-4 FPGA User Guide (UG070) Spartan-6 FPGA User Guide (Spartan-6 FPGA product page) Spartan-3, Spartan-3E, Spartan-3A FPGA Data Sheets Virtex-6 FPGA RocketIO Transceiver User Guide (Virtex-6 FPGA product page) Virtex-4 FPGA RocketIO Multi-Gigabit Transceiver User Guide (UG076) Virtex-5 FPGA RocketIO Transceiver User Guide (UG196) Virtex-5 FPGA RocketIO Transceiver User Guide (UG198) [10] IEEE 802.3-2005 specification [11] Serial-GMII specification, revision
Support
technical support, visit www.xilinx.com/support. Xilinx provides technical support this product when used described product documentation. Xilinx cannot guarantee timing, functionality, support product implemented devices that listed documentation, customized beyond that allowed product documentation, changes made sections design marked MODIFY.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Ordering Information
This core provided under Xilinx User License Agreement generated using CORE Generator software v11.2 higher. CORE Generator software shipped with Xilinx FoundationSeries Development software. simulation evaluation license core shipped with CORE Generator software. access full functionality core, including FPGA bitstream generation, charge full license must obtained from Xilinx. 1000BASE-X product page: Please contact your local Xilinx sales representative pricing availability Xilinx LogiCORE modules software. Information additional LogiCORE modules available Xilinx Center.
List Acronyms
following table describes acronyms used this manual. Acronym FIFO FPGA GBIC Gbps GMII Mbps MDIO Spelled Digital Clock Manager Dynamic Reconfiguration Port Frame Check Sequence flip-flop First First Field Programmable Gate Array. Gigabit Interface Converter Gigabits second Gigabit Media Independent Interface Hardware Description Language Input/Output Input/Output Block Intellectual Property Integrated Software Environment Incisive Unified Simulator (Cadence) Lookup Table Media Access Controller Megabits second Management Data Input/Output Multi-Gigabit Transceiver Mega Hertz
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Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Acronym SGMII VHDL
Spelled Media Independent Interface Native Generic Circuit Native Generic Database Printed Circuit Board Physical Coding Sublayer physical-side interface Physical Medium Attachment Physical Medium Dependent Standard Delay Format Single Data Rate Start Frame Delimiter Small Form-Factor Pluggable Serial Gigabit Media Independent Interface Ten-Bit-Interface Verilog Compiled Simulator (Synopsys) VHSIC Hardware Description Language (VHSIC acronym Very High-Speed Integrated Circuits). Xilinx Synthesis Technology
Revision History
following table defines changes document since initial release. Date
9/24/04 10/11/04 4/28/05 1/11/06 7/13/06 10/23/06 2/15/07 8/08/07 3/24/08 4/24/09 6/24/09
Version
Initial Xilinx release.
Revision
Document updated with corrections Table (configuration_vector[3:0] definition). Updated core v6.0, Xilinx tools v7.1i SP2, Foundation software v7.1i. Updated core v7.0, Xilinx tools v8.1i. Updated core version 7.1, Xilinx tools v8.2i. Updated core version 8.0, support Virtex-5 Spartan devices. Updated core version 8.1, Xilinx tools 9.1i. Updated core version 9.0, Xilinx tools 9.2i. Updated core version 9.1, Xilinx tools 10.1. Updated core version 10.1, Xilinx tools 11.1, support Virtex-5 Virtex-6 devices. Updated core version 10.2, Xilinx tools 11.2, support Spartan-6 devices.
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DS264 June 2009 Product Specification
Ethernet 1000BASE-X PCS/PMA SGMII v10.2
Notice Disclaimer
Xilinx providing this product documentation, hereinafter "Information," with warranty kind, express implied. Xilinx makes representation that Information, particular implementation thereof, free from claims infringement. responsible obtaining rights require implementation based Information. specifications subject change without notice. XILINX EXPRESSLY DISCLAIMS WARRANTY WHATSOEVER WITH RESPECT ADEQUACY INFORMATION IMPLEMENTATION BASED THEREON, INCLUDING LIMITED WARRANTIES REPRESENTATIONS THAT THIS IMPLEMENTATION FREE FROM CLAIMS INFRINGEMENT IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Except stated herein, none Information copied, reproduced, distributed, republished, downloaded, displayed, posted, transmitted form means including, limited electronic, mechanical, photocopying, recording, otherwise, without prior written consent Xilinx. 2004-2009 Xilinx, Inc. XILINX, Xilinx logo, Virtex, Spartan, other designated brands included herein trademarks Xilinx United States other countries. PowerPC name logo registered trademarks Corp. used under license. other trademarks property their respective owners.
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