Drop-in module Virtex®-4, Virtex-5,Virtex-6, Spartan®-3, Spartan-3A, S
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DS558 June 2009 Product Specification
Drop-in module Virtex®-4, Virtex-5,Virtex-6, Spartan®-3, Spartan-3A, Spartan-3A DSP, Spartan-3E Spartan-6 FPGAs Very high performance, including optimal optional DSP48 Sine, cosine, quadrature outputs Look-up table allocated distributed block memory Phase dithering Taylor series correction options provide high dynamic range signals using minimal FPGA resources. SFDR range Phase dithering removes spectral line structure associated with conventional phase truncation waveform synthesis architectures Support independent channels High-precision synthesizer with fine frequency resolution 0.02 fclk MHz, 34-bit phase accumulator) 4-bit 20-bit two's complement output sample precision Optional phase offset capability allows multiple synthesizers with precisely controlled phase differences Simple fixed-output frequency option Incorporates Xilinx SmartIPtechnology utmost parameterization optimum implementation with Xilinx CORE Generatorv11.2 later
Phase Accumulator Phase Increment B(n)
Applications
Digital radios modems Software-defined radios (SDR) Digital down/up converters cellular base stations Waveform synthesis digital phase locked loops Generating injection frequencies analog mixers
General Description
Direct digital synthesizers (DDS), numerically controlled oscillators (NCO), important components many digital communication systems. Quadrature synthesizers used constructing digital down converters, demodulators, implementing various types modulation schemes, including (phase shift keying), (frequency shift keying), (minimum shift keying). common method digitally generating complex real valued sinusoid employs look-up table scheme. look-up table stores samples sinusoid. digital integrator used generate suitable phase argument that mapped look-up table desired output waveform. simple user interface accepts system-level parameters such desired output frequency spur suppression generated waveforms. high-level view core presented Figure
X-Ref Target Figure
B(n) Sine/Cosine Lookup Table Table Depth 2B(n) cos((n)) sin((n))
fout fclk/2B(n)
XIP166
Figure Phase Truncation Simplified View Core)
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Theory Operation
integrator (components computes phase slope that mapped sinusoid (possibly complex) look-up table quantizer which simply slicer, accepts high-precision phase angle generates lower precision representation angle denoted figure. This value presented address port look-up table that performs mapping from phase-space time. fidelity signal formed recalling samples sinusoid from look-up table affected both phase amplitude quantization process. length width look-up table affect signal's phase angle resolution signal's amplitude resolution, respectively. "Spectral Purity Considerations" more details. Direct digital synthesizers addressing scheme with appropriate look-up table form samples arbitrary frequency sinusoid. analog output required, presents these samples digital-to-analog converter (DAC) low-pass filter obtain analog waveform with specific frequency structure. course, samples also commonly used directly digital domain. look-up table traditionally stores uniformly spaced samples cosine sine wave. These samples represent single cycle length prototype complex sinusoid correspond specific values sinusoid's argument shown Equation
Equation
where time series sample index. Quarter wave symmetry basis waveform exploited construct that uses shortened tables. this case, most significant bits quantized phase angle used perform quadrant mapping. This implementation results more area efficient implementation because memory requirements minimized: either fewer FPGA block RAMs reduced distributed memory. Based core customization parameters, core automatically employs quarter-wave symmetry when appropriate (1).
Output Frequency
output frequency, waveform function system clock frequency number bits phase accumulator phase increment value that fout (fclk, B(n), Output frequency Hertz defined Equation
fout
fclk
Equation
very short tables, FPGA logic resources actually minimized storing complete cycle. user required make design decisions this context; CORE Generator always produces smallest core possible.
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DS558 June 2009 Product Specification
example, parameters shown Equation
fclk 1210
Equation output frequency shown Equation
1406250
Equation phase increment value Equation required generate output frequency
shown
Equation
Frequency Resolution
frequency resolution synthesizer function clock frequency number bits employed phase accumulator. frequency resolution determined using Equation
Equation
example, parameters Equation
Equation
frequency resolution shown Equation
0.0279396
Equation
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Phase Increment
phase increment unsigned value. phase increment term defines synthesizer output frequency. Consider with parameterization shown Equation
Equation generate sinusoid with frequency MHz, required phase increment shown Equation
778.24
Equation
Spectral Purity Considerations
fidelity signal formed recalling samples sinusoid from look-up table affected both phase amplitude quantization process. length width look-up table affect signal's phase angle resolution signal's amplitude resolution, respectively. These resolution limits equivalent time base jitter amplitude quantization signal spectral modulation lines white broad-band noise floor signal's spectrum. conjunction with system clock frequency, phase accumulator width determines frequency resolution DDS. accumulator must have sufficient field width span desired frequency resolution. most practical applications, large number bits allocated phase accumulator satisfy system frequency resolution requirements. example, required resolution clock frequency MHz, required field width accumulator shown Equation 26.5754 27bits Equation where denotes ceiling operator. excessive memory requirements, full precision phase accumulator cannot used index sine/cosine look-up table. quantized truncated) version phase angle used this purpose. block labeled phase truncation DDS, Figure performs phase angle quantization. look-up table located block distributed memory.
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DS558 June 2009 Product Specification
Quantizing phase accumulator introduces time base jitter output waveform. shown Equation this jitter results undesired phase modulation that proportional quantization error.
(n)e
Equation Figure shows look-up table addressing error, complex output time-series, spectral domain representation output waveform produced structure shown Figure normalized frequency this signal 0.022 which corresponds phase accumulation steps 7.92 degrees output sample. angular resolution 256-point look-up table 360/256 1.40625 degrees address, which equivalent 7.92/1.40625 5.632 addresses output sample. Since address must integer, fractional part discarded resultant phase jitter cause spectral artifacts. Figure provides exploded view spectral plot Figure 2(c).
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-100
Figure Phase Truncation DDS. 0.022 Table Depth 12-Bit Precision Samples. Phase Angle Addressing Error Complex Output Time Series Output Spectrum
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uadrature utput ample Precision able epth Frequency 0.022 Length 2048 indow lackman 16-Sep-2000 14:51:00
Figure Phase Truncation DDS. 0.022 Table Depth 12-Bit Precision Samples. Exploded View Figure 2(c).
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observations related phase jitter structure level made. First, observe that fractional part address count periodic (sawtooth) error sequence, which responsible harmonic rich (and aliased) low-level phase modulation evident Figure Also, note that peak distortion level incidental phase modulation approximately below desired signal level, which consistent with dB/bit address space. another way, spur suppression required output waveform, referenced primary tone, look-up table must support least address bits. example, which means that highest spur will below main signal, then minimum number address bits look-up table bits; that 4096-deep table. Figure Figure demonstrate performance similar presented Figure this example, 16-bit precision output samples have been used. Observe that highest spur still level, allocating four additional bits output samples contributed further spur reduction. phase truncation DDS, only option further reduce spur levels increase depth look-up table.
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-100
Figure Phase Truncation DDS. 0.022 Table Depth 16-Bit Precision Samples. Phase Angle Addressing Error Complex Output Time Series Output Spectrum
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uadrature Output Sample Precision able epth requency 0.022 Length 2048 indow Blackman 16-Sep-2000 14:51:42
-100
Figure Phase Truncation DDS. 0.022 Table Depth 16-Bit Precision Samples. Exploded View Figure (c).
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DS558 June 2009 Product Specification
Further examples illustrating performance various configurations shown Figure through Figure configuration details annotated plot. some these examples, synthesized frequency been swept across small range available output bandwidth. these cases, sweep start frequency, stop frequency, frequency increment number tones sweep interval (Num Tones) indicated. analysis transform length window function applied output time series also indicated plots.
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drature Outp cisio pr-20 :33:47
-100 -0.5
reque
Figure Example Plot
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drature Outp cisio pr-20 :34:44
-100 -0.5
reque
Figure Example Plot
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rature recis able tart 0.022 uency 0.0257 05Hz pr-200 18:36:50
-0.5
Frequency
Figure Example Plot
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uadrature Output Sample Precision able epth Frequency 0.032 06-Apr-2001 13:18:48
-48D
-0.5
Frequency
Figure Example Plot
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rature recis able requenc 0.032 pr-200 18:23:18
-0.5
Frequency
Figure Example Plot
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DS558 June 2009 Product Specification
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rature recis able requenc 0.032 pr-200 18:24:12
-0.5
Frequency
Figure Example Plot
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rature recis able tart 0.022 uency 0.04 018Hz ep-2000 3:33
-0.5
Frequency
Figure Example Plot
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rature recis able tart 0.322 uency 0.35 028Hz ep-2000 4:42
-0.5
Frequency
Figure Example Plot
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Quad rature Outp recis Table tart 0.022 uency 0.0462 0242 ep-2000 5:43
-0.5
Frequency
Figure Example Plot
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rature recis able tart 0.022 uency 0.0762 0108 ep-2000 6:28
-0.5
Frequency
Figure Example Plot Figure provides simplified view core. more detailed view shown Figure This detailed figure similar simplified view, also indicates control interface signals, ADDR, REG_SELECT, DATA, RFD, RDY. Also note inclusion PHASE OFFSET register designated POFF. This register used applying constant phase offset phase slope computed phase accumulator PACC. When core customized, phase offset source defined either programmable register constant, omitted entirely. When register option selected, phase offset value must supplied DATA port. phase offset value treated unsigned quantity. necessary, phase offset zero-extended before added phase accumulator. phase increment value sourced from either register constant. When registered option selected, DATA port supplies phase increment value phase increment register. When constant option selected, output frequency fixed cannot adjusted once core embedded design.
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DS558 June 2009 Product Specification
X-Ref Target Figure
Phase Accumulator PINC DATA
Phase Offset
Dither
SIN/COS
Taylor Series Correction SINE COSINE
REG_SELECT
POFF
Dither Generator
DS558_16_041107
Figure Core (Detailed View)
Phase Dithered
phase truncation architecture shown Figure quantizer introduces phase error phase slope discarding least significant part, actually fractional component, highprecision phase accumulator. phase error discarded fractional part address count periodic series which results undesired spectral line structure. Figure provides example this process with table depth N=1024 table sample precision bits. Figure phase error generated taking difference between quantizer input output signals, Figure 17(b) output time series Figure 17(c) signal output spectrum. Observe Figure 17(a) periodic sawtooth structure phase error signal. line spectrum associated with this correlated error sequence impressed final output waveform results spectral lines synthesizer output spectrum. These spurious components clearly seen Figure 17(c).
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-100
FREQU
Figure Plots Showing Phase Error Time Series, Complex Output Time Series, Output Spectrum. 1024 Deep Look-Up Table, 16-Bit Samples, Output Frequency 0.333 This structure suppressed breaking regularity address error with additive randomizing signal. This randomizing sequence, called dither, noise sequence, with variance approximately equal least significant integer phase accumulator. dither sequence added high-precision accumulator output prior quantization
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dithered supplies, approximately, additional spurious free dynamic range (SFDR) comparison phase truncation design. This achieved spreading spectral energy phase error signal. additional logic resources required implement dither sequence generator significant. provide spur suppression using phase truncation DDS, referenced primary tone, internal look-up table must support least address bits. achieve this same performance using dithered architecture requires fewer address bits, minimizing number block RAMs logic slices distributed memory implementation) used FPGA implementation. summary, dithered implementation, number address bits needed support spur suppression equal Figure Figure provide results several dithered simulations. Figure shows eight simulations complex dithered employing table depth 4096 16-bit precision samples. each plot output frequency different annotated plot. phase truncation design would typically generate output spurs below output frequency, independent actual value output frequency. Indicated each plots parameter peak spur level achieved simulation. eight spurs -88.12, -88.22, -86.09, -88.80, -87.21, -87.55, -87.83, -87.12 below output frequency. worst case value -86.09 14.09 better than similarly configured phase truncation DDS. achieve this same SFDR extending table length phase truncation design would require extending table more than factor four. Figure provides more dithered simulation where output frequency swept over band frequencies. spectrum each discrete tone sweep band overlaid construct final plot. sweep start frequency, frequency, number tones sweep, configuration annotated plot.
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0.47506
0.11557
-88.1194dB 0.20728Hz
-88.217dB 0.45374Hz
0.30342 Frequency -86.092dB 0.11707Hz
0.24299 Frequency -88.8048dB 0.0026855Hz
0.44565 Frequency -87.2061dB 0.06543Hz
0.38105 Frequency -87.5455dB 0.1554Hz
0.22823 Frequency -87.8365dB 0.034058Hz
0.0092518 Frequency -87.1189dB 0.11377Hz
Frequency
Frequency
Figure Dithered Simulations. Configuration 4096, eight plots spectral domain representations eight different output frequencies. Each plot annotated with peak spur.
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DS558 June 2009 Product Specification
Figure synthesized signal swept over range frequencies starting from 0.0311 0.0415 There tones sweep separated frequency 0.00104 this example, phase truncation would produce peak spurs with respect primary signal. dithered provides approximately better performance with peak spur below output signal. further advantage dithered that spectral line structure present phase truncation design removed out-of-band signal significantly whitened. This white broadband noise floor more desirable than line structured spectrum. digital communication receivers that generating mixing signals performing channelization functions, spurs phase truncation low-level mixing tones cause undesirable spectral contamination desired channel. virtually applications, preferred implementation dithered DDS.
X-Ref Target Figure
start sweep 0.0311 sweep 0.0415 sweeps 0.00104 epth 4096 recision recision 08-A pr-2001 11:45:12
Frequency
Figure Example Plot
Taylor Series Corrected
phase dithered DDS, well phase truncation DDS, have quantizer which produces lower precision (n), discarding fractional component high precision (n). reason this quantization step keep size look-up memory reasonable size. trade-off spectral purity. With availability embedded multipliers DSP48 primitives Virtex-II Pro, Spartan-3, Virtex-4, Virtex-5 FPGAs, practical previously discarded fractional bits calculate corrections that added look-up table values produce outputs with very high spurious free dynamic range (SFDR). These embedded multipliers ASIC-like multipliers consume logic fabric. Figure Figure Figure Figure show results four different Taylor series corrected simulations. Taylor series corrected architecture uses table depth 4096 18-bit precision samples. However, precision output feed-forward error processor bits. each plot, output frequency different annotated directly plot. similarly configured phase truncation would produce spurs phase dithered peak spurs four plots -118.25, -118.13, -118.10, -118.17 below output frequency. Figure shows swept frequency Taylor series corrected DDS. starting frequency this example 0.0313 final frequency 0.0813, there tones sweep. Using this configuration, phase truncation would produce peak spurs approximately below output signal phase dithered would produce peak spurs approximately below output signal. shown plot, Taylor series corrected produced spurs that were
DS558 June 2009 Product Specification
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down below output signal. This result better than phase dithering DDS, better than phase truncation DDS, still only consumes single 18Kb block look-up storage. Figure shows another frequency sweep simulation with tones over broader frequency range. Note that SFDR limited phase increment value. When values SFDR above required, 18-bit output block extrapolated bits using phase error. this phase error constant because phase increment zeroes least significant bits, then aliasing occurs SFDR limited recommended that least significant accumulator avoid mathematical aliasing effects. These aliasing effects mathematics rather than implementation.
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0.0092518 Peak Spur -118.2488dB Depth 4096 Precision PACC Precision 05-Mar-2002 17:00:38
-100 -120 -140 -0.5
-118
-0.25
0.25
Frequency
Figure Taylor Series Corrected Single-Tone Test, 0.0092518
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0.22823 Peak Spur -118.1295dB Depth 4096 Precision PACC Precision 05-Mar-2002 17:05:12
-100 -120 -140 -0.5
-118
-0.25
0.25
Frequency
Figure Taylor Series Corrected Single-Tone Test, 0.22823
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DS558 June 2009 Product Specification
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0.30342 Peak Spur -118.0964dB Depth 4096 Precision PACC Precision 05-Mar-2002 17:06:29
-100 -120
-118
-140 -0.5
-0.25
0.25
Frequency
Figure Taylor Series Corrected Single-Tone Test, =0.30342
X-Ref Target Figure
0.47506 Peak Spur -118.1732dB Depth 4096 Precision PACC Precision 05-Mar-2002 17:08:30
-100 -120 -140 -0.5
-118
-0.25
0.25
Frequency
Figure Taylor Series Corrected Single-Tone Test, 47506
X-Ref Target Figure
-100
start sweep 0.0313 sweep 0.0813 sweeps 0.0005 Peak Spur -117.7752dB Depth 4096 Precision PACC Precision 05-Mar-2002 16:30:45
-118 -120 -140 -0.5 -0.25 0.25
Frequency
Figure Taylor Series Corrected Frequency Sweep Simulation, tones
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-100
start sweep 0.025 sweep 0.25 sweeps 0.0064286 Peak Spur -112.3654dB Depth 4096 Precision PACC Precision 06-Mar-2002 16:32:35
-112 -120 -140 -0.5 -0.25 0.25
Frequency
Figure Taylor Series Corrected Frequency Sweep Simulation, tones
Interface, Control, Timing
compiler core pinout shown Figure possible pins shown, though specific pins instance depend upon generation parameters. Table details pinout core.
X-Ref Target Figure
Figure Symbol
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DS558 June 2009 Product Specification
Table Core Signal Pinout Signal Name
REG_SELECT(1)
Direction
Input Input
Description
Master Clock active rising edge. Address select writing phase increment (PINC) memory phase offset (POFF) memory. When REG_SELECT=0, PINC memory selected. When REG_SELECT=1, POFF memory selected. This will exist both POFF PINC programmable. This used address channels currently selected memory. number bits ADDR channels, channels, channels, channels. This will exist either PINC POFF programmable there multiple channels. Write enable active High. Enables write operation PINC POFF memories. Clock enable active High. must High during normal core operation, required active during write access PINC POFF memories. Time shared data bus. DATA port used supplying values PINC POFF memories. value input DATA describes phase angle. bits wide, full circle into phase segments, ranges [-2N-1, 2N-1 both describe full circle. Because this, makes difference this port considered signed unsigned. Both PINC POFF registers fixed point. lower precision values that required other, these values must right-justified input upper bits DATA bus. example, with Data width bits, POFF only needs 1/8, 2/8, 3/8, etc., bits used describe phase offset must bits DATA port. Synchronous clear active High. When SCLR asserted, accumulator reset. also deasserted. Note that outputs core following SCLR undefined until fresh data qualified RDY) output. Output data ready active High. Indicates when output samples valid. Ready data active High. dataflow control signal present many Xilinx LogiCORE cores. context DDS, supplied only consistency with other LogiCORE cores. This optional port always tied VCC. Channel index. Indicates which channel currently available output when configured multi-channel operation. This unsigned signal. width determined number channels. qualified RDY. Sine time-series. Cosine time-series. Phase corresponding Sine Cosine Values presented. format same DATA port, that 2N-1describes 360) degrees.
ADDR(1)(2)
Input
WE(1) CE(1)
Input Input
DATA(1)
Input
SCLR(1)
Input
RDY(1) RFD(1)
Output Output
CHANNEL(1)
Output
SINE(1) COSINE(1) PHASE_OUT
Output Output Output
Notes:
Denotes optional pin. "Known Hazards," page
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Figure shows timing sequence single-channel core. this example, both phase increment (PINC) phase offset (POFF) memory (the phase offset memory only required when there phase offset). PINC memory first written. This realized supplying value DATA port addressing PINC memory setting REG_SELECT Since this example single-channel case, ADDR port present need considered. write performed positive clock edge. must active; that WE=1, perform this operation. After PINC memory loaded, value written POFF memory. This requires REG_SELECT WE=1.
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Figure Timing: Single Channel memory loaded rising edge clock. does have active write either PINC POFF memories. starts operating after clock enable applied (CE=1). Since optional pin, configurations that include this will begin operating after FPGA configured system clock active. After start-up latency (measured from assertion (1)) that depends pipelining configuration chosen core, samples will presented output port(s). This indicated RDY=1. Note that this case, SCLR asserted, then deasserted. latency core determines delay from deassertion SCLR assertion RDY. most configurations, assertion core indicates first valid output sample. However, there exception. customized such that 0-cycle latency phase accumulator option selected, sine-cosine look-up table distributed memory, table purely combinatorial, writes PINC register will immediately reflected output port(s). This irrespective whether asserted not. this situation, there registers between PINC register output nodes; there only combinatorial arrangement logic. Therefore, cannot have influence this path through system. will, course, still control operation register PACC. illustrated Figure valid samples begin appearing output ports when goes High. have optional synchronous clear port (SCLR). This active High. When SCLR applied, SINE COSINE output ports assume value SINE COSINE become nonzero before assertion RDY, these values artifact internal structure valid data values. Valid data qualified RDY.
Latency
Since compiler core true data-in port, latency very confusing. Latency defined number registers design following accumulator. accumulator's register included this definition, hence defined separate parameter. However, delay from
Assuming this port present.
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DS558 June 2009 Product Specification
disassertion SCLR first valid output, delays from changes programmable parameters (phase increment offset) change output values same latency figure. reason this that optimal speed area, especially context multiple channels, extra registers used accumulator feedback. behavioral model simulated exact delay give parameters. Note also that delay from accumulator register outputs measured clock-enabled clock cycles, when there present, progammable registers increment offset parameters dependent only address. recommended that core reset before while parameters changed, that reset released only after parameter changes have been programmed. However, on-the-fly changes parameters required, then again behavioral model again used exact delay given combination parameters. given configuration, delay from changes PINC POFF output will constant, variation family, requested latency, area/speed optimization, DSP48 because PINC/POFF registers gated latency PINC POFF very complex, hence recommendation make changes only during SCLR. When SCLR asserted, accumulator will reset first cycle following disassertion SCLR, accumulator will increment PINC. After number cycles equal latency parameter, corresponding COSINE values will seen output. POFF added phase immediately following accumulator, latency from POFF output clock enabled cycle less (assuming accumulator latency than latency PINC changes. Note that PINC POFF, write PINC POFF register occur without regard propagation change output will fixed number clock enabled cycles. latency each these inputs number clock cycles plus number clock enabled cycles. When single channel mode, with DSP48_use maximal C_OPTIMISE_GOAL speed, there registers between inputs accumulator PINC. other single channel cases, there only single register. number clock enabled stages following this latency plus accumulator latency. POFF with DSP48_use minimal, latency will PINC, without accumulator latency. When DSP48_use maximal, POFF latency will same PINC latency, except when latency maximal, which case will clock enabled cycle less than PINC. multichannel cases, delay further complicated fact that circuit timemultiplexed, delay from inputs each channel's PINC POFF depends also phase time-multiplex channel selector. behavioral model matches behavior core cases. Since writes PINC POFF registers unaffected SCLR, recommended that SCLR held High until values have been loaded. This simplifies latency considerations since only SCLR latency need considered, also there signal indicate data output based values.
Parameters
customization parameter definitions are: Component Name: user-defined component name. Output_Selection: have quadrature output (Sine_and_Cosine), single output port either Sine Cosine. Negative_Sine, Negative_Cosine: sign output signal(s) defined using Negative Sine Negative Cosine checkboxes.
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Channels: core generate single-channel implementation well multi-channel implementation with support independent channels. multi-channel implementation generated, channels will timeshare outputs. Performance Options: Both system-level circuit-level performance requirements specified, core generates implementation meet these requirements
Clock Rate: frequency which core will clocked. Spurious Free Dynamic Range (SFDR): This parameter defines frequency domain requirements out-of-band noise generated outputs. range from spur suppression. Note that SFDR value greater forces implementation employing Taylor Series Correction which requires embedded multipliers DSP48 primitives. Note also that SFDR cannot guaranteed, because also affected frequency resolution phase_increment value. ensure full SFDR, frequency resolution must give accumulator width least great output width, phase_increment value must such that bits this width accumulator change. instance, accumulator width bits output width bits, least five least significant bits phase increment value should set; otherwise SFDR will degraded. Frequency Resolution: This parameter determines granularity tuning frequency. value entered tuning frequency adjusted precision example, could tune frequency 5.00003 MHz.
Output Frequencies: each channel, independent frequency entered into table Sine Cosine outputs. allowable upper range displayed above table calculated taking half clock rate then dividing total number channels. This upper limit required that clock rate does drop below Nyquist frequency.
Phase Increment: user choice making output frequency constant value in-circuit changeable. Selecting Fixed will make frequencies constant, selecting Programmable will allow phase increment values changed in-circuit. Programmable selected, values entered table will initial frequencies that take effect once FPGA been configured. SCLR signal asserted, output frequency settings will altered. Note that Fixed Programmable option applied channels. Note also that minimal resource use, CREG DSP48 used PINC register. This occurs only when DSP48_use maximal, clock rate (area optimization) there only single channel. this case, initialization value ignored and, hence, must programmed before use.
Phase Offset Angles: independent offset added phase angle each channel entering value into table. entered values will multiplied radians. valid range -1.0 1.0.
Phase Offset: user choice making phase offset angles constant value, incircuit changeable, used (saving resources). Selecting Fixed will make offsets constant; selecting Programmable will allow them changed in-circuit; selecting None will prevent offset from being added. Programmable selected, values entered table will initial offsets that will take effect once FPGA been configured. SCLR signal asserted, phase offset angles settings will altered. Note that Fixed, Programmable, None option applied channels.
Clear Options: SCLR selected, core will generated with reset that synchronized clock. When asserted, internal logic returns initialized state. Note that programmable values retained. Sine Cosine output ports will undefined until enough clock cycles have passed fill core internal pipeline, which determined adding Latency Accumulator Latency values. Note that data outputs cleared
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DS558 June 2009 Product Specification
zero following SCLR. However, signal will qualify valid data, will following SCLR until valid data output. Clock Enable: core have optional clock enable port. Noise Shaping: radio buttons this frame control whether phase truncation, dithered DDS, Taylor series corrected implementation generated. When Auto selected, noiseshaping type will automatically determined, based other core parameters including SFDR. When None selected, phase truncation produced. Phase Dithering Taylor Series Corrected selections self-explanatory. resolved value shown summary page (page GUI). Memory Type: This field controls location trigonometric look-up table. When Distributed selected, table placed distributed memory. Block selected, table will implemented using block memory. Auto selected, actual memory type will automatically determined, based other core parameters, including SFDR. resolved value shown summary page (page GUI). Optimization Goal: This field determines whether design optimized speed area. left automatic, this decision made basis DDS_Clock_Rate parameter family. resolved value shown summary page (page GUI). Handshaking Options: Optional handshaking ports- RFD-can included core. output signal simply tied optional port that included compatibility with other Xilinx LogiCORE cores that employ this style dataflow interface. shown Figure output signal identifies when valid sine/cosine samples appear these ports after core started from rest either after system power-on reset (synchronous asynchronous). type core reset will cause removed (RDY=0). When Channels parameter value more Channel parameter selected, additional output will generated indicate which channel current output samples belong Accumulator Width (readout only): Phase accumulator precision. This field defines precision PACC register (Figure 16). location register phase accumulator controlled latency selection options. When one-cycle latency option selected, phase accumulator output will taken synchronously, that from output accumulator register. When zero-cycle option selected, output taken asynchronously from adder logic accumulator. Note that zero-cycle only available when Latency Latency (readout only). Since does have true data-in datapath, latency defined number pipeline stages following accumulator. recovery from SCLR differs clock cycle single channel opposed multi-channel cases. This multi-channel cases. High latency allows fewer levels logic between registers hence allows faster operation, also uses more chip resources. "Performance Characteristics" resource estimates achieved frequencies various combinations Latency other parameters.
DS558 June 2009 Product Specification
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File Parameters
Generic parameters shown Table Table Generic Parameters Parameter
Output_selection
Values
Generic VHDL Parameter
Generic Values
0,1,2
Description
sine only, only, both false, true false, true Number channels
Sine, Cosine, C_OUTPUTS_REQUIRED Sine_and_Cosine false, true false, true Integer, 0.01 0.0233 10000 DDS_clock_rate/ Channels) Fixed Programmable real (-1.0 +1.0) C_PHASE_INCREMENT_ VALUE C_PHASE_INCREMENT C_PHASE_OFFSET_ VALUE C_PHASE_OFFSET C_NEGATIVE_SINE C_NEGATIVE_COSINE C_CHANNELS Notes 6,7.
Negative_Sine Negative_Cosine Channels DDS_clock_rate Spurious_free_dynamic_ range Frequency_Resolution Output_Frequency1, Output_Frequency2,. Output_Frequency16 Phase_Increment Phase_Offset_Angles1, Phase_Offset_Angles2,. Phase_Offset_Angles16 Phase_Offset
Note
Programmable, Fixed
Notes -1.0 -180 degrees, +1.0 +180 degrees 0,1,2 None, Programmable, Fixed false, true false, true None, Phase Dithering, Taylor Series Correction Area, speed. Auto, Block, Distributed minimal, maximal false, true false, true false, true
None, Fixed Programmable false, true false, true
SCLR_Pin Clock_Enable Noise_Shaping
C_HAS_SCLR C_HAS_CE
0,1,2
Auto, None, C_NOISE_SHAPING Phase_DIthering, Taylor_Series_Co rrected Auto, Area, Speed C_OPTIMISE_GOAL Auto, C_MEM_TYPE Distributed_ROM, Block_ROM minimal, maximal false, true false, true false, true C_USE_DSP48 C_HAS_RFD C_HAS_RDY C_HAS_CHANNEL
Optimization_Goal Memory_Type
0,1,2
DSP48_use Channel_Pin
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DS558 June 2009 Product Specification
Table Generic Parameters (Cont'd) Parameter
Latency_Configuration Latency Accumulator_Latency Notes:
C_PHASE_INCREMENT_VALUE comma separated string value, example "0110, 0111, 0000", where each entry corresponds channel etc. binary value will padded (with truncated C_DATA_WIDTH phase increment value accumulator corresponding channel. single-channel cases with Phase_increment programmable, DSP48_use maximal DDS_clock_rate MHz, Phase_increment_value shall ignored must programmed before use. C_PHASE_OFFSET_VALUE, like C_PHASE_INCREMENT_VALUE, comma-separated string value. each channel, value added after phase accumulation stage. Each value considered unsigned purposes padding. Latency configured specific figure, core determine latency required maximal speed, function other parameters. When Latency_Configuration Auto, generic C_LATENCY will This will pipeline core maximal speed. When Latency_Configuration Configurable, C_LATENCY will same value Latency. C_ACCUMULATOR_WIDTH log2(DDS clock rate/Frequency resolution) rounded must least C_OUTPUT_WIDTH SFDR compromised. C_OPTIMISE_GOAL (speed) Clock Rate MHz. C_OUTPUT_WIDTH (SFDR/6) rounded except Taylor Series Correction, where added this basic formula. SFDR less than requested Frequency Resolution gives C_ACCUMULATOR_WIDTH less than C_OUTPUT_WIDTH accumulator value (PINC) mutually prime with 2^C_ACCUMULATOR_WIDTH. However, C_ACCUMULATOR_WIDTH forced great C_OUTPUT_WIDTH. "Known Hazards," page
Values
Auto, Configurable 0,1,.15
Generic VHDL Parameter
C_LATENCY
Generic Values
0,1,.15
Description
Note
C_ACCUMULATOR_ LATENCY
Generic Parameters
been designed system architects. C_ACCUMULATOR_WIDTH determines width phase accumulator, bits. determining precision phase increment, this determines frequency resolution fraction system clock. C_DATA_WIDTH width data used program phase_increment values phase_offset values. C_DATA_WIDTH should typically same C_ACCUMULATOR_WIDTH. allowed larger. C_OUTPUT_WIDTH sets width output buses SINE COSINE. C_PHASE_ANGLE_WIDTH sets width accumulated, adjusted, dithered phase into SIN/COS lookup table. Larger values typically increase spectral purity outputs, cost extra terms RAM. C_OPTIMISE_GOAL speed/area option. C_OPTIMISE_GOAL, optimizes circuit speed. optimizes area. Except very high clock speeds (above about Virtex-4 devices), area optimization recommended. parameters supplied filter captured logged file. full name this file simply Component Name with .xco file extension. Table defines .xco file parameter names range specifications.
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Performance Characteristics
Table through Table show performance compiler core terms resource usage maximum achieved operating frequency. These results were obtained with v11.2 tools. Note that resource count speed core change depending surrounding circuitry your design. Therefore, these figures should taken only guide. tool settings achieve these results were follows:
high high
Note: tool settings have significant effect area speed. Xilinx Xplorer script used
find optimal settings.
Table Spartan3A-DSP XC3SD3400A Device Description
Accumulator width Output width Noise shaping Channels Use_DSP48 Optimization Latency Phase Offset Slices LUTs BRAM18s DSP48As Frequency Part Speed grade
Small
None Area
Medium
Area
Large Dither with Offset
Dither Speed fully pipelined Constant XC3SD3400A
Taylor
Taylor Speed fully pipelined
Taylor MultiChannel
Taylor Speed fully pipelined
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Table Spartan3A-DSP XC3SD3400A Device Description
Accumulator width Output width Noise shaping Channels Phase Offset Optimization Latency Use_DSP48 Slices LUTs BRAM18s DSP48As Frequency Part Speed grade
SFDR50
None none speed full
SFDR70
None none speed full
SFDR84
Dither none speed full
SFDR110
Taylor none speed full
XC3SD3400A
Table Virtex-5 XC5VLX50t Device Description
Accumulator width Output width Noise shaping Channels Use_DSP48 Optimization Latency Phase Offset LUT_FF pairs LUTs BRAM36/18s DSP48Es Frequency (speed grade Part
Small
None Area
Medium
Area
Large
Dither Speed fully pipelined Constant XC5VLX50T
Taylor
Taylor Speed fully pipelined
Taylor MultiChannel
Taylor Speed fully pipelined
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Table Virtex-5 XC5VLX50t Device Description
Accumulator width Output width Noise shaping Channels Phase_offset Optimization Latency Use_DSP48 LUT_FF pairs LUTs BRAM36/18s DSP48Es Frequency (speed grade Part
SFDR50
None none speed full
SFDR70
None none speed full
SFDR84
Dither none speed full
SFDR110
Taylor none speed full
XC5VLX50T
Table Spartan-6 XC6SLX45 Device Description
Accumulator width Output width Noise shaping Channels Use_DSP48 Optimization Latency Phase Offset Slices LUTs BRAM18/9 DSP48As Frequency Part Speed grade
Small
None Area
Medium
Area
Large Dither with Offset
Dither Speed fully pipelined Constant XC6SLX45-FGG484-2
Taylor
Taylor Speed fully pipelined
Taylor MultiChannel
Taylor Speed fully pipelined
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Table Spartan-6 XC6SLX45 Device Description
Accumulator width Output width Noise shaping Channels Phase Offset Optimization Latency Use_DSP48 Slices LUTs BRAM18/9 DSP48As Frequency Part Speed grade
SFDR50
None none speed full
SFDR70
None none speed full
SFDR84
Dither none speed full
SFDR110
Taylor none speed full
XC6SLX45-FGG484-2
Table Virtex-6 XC6VLX75t Device Description
Accumulator width Output width Noise shaping Channels Use_DSP48 Optimization Latency Phase Offset LUT_FF pairs LUTs BRAM36/18s DSP48Es Frequency (speed grade Part
Small
None Area
Medium
Area
Large
Dither Speed fully pipelined Constant XC6VLX75T-FF484-1
Taylor
Taylor Speed fully pipelined
Taylor MultiChannel
Taylor Speed fully pipelined
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Table Virtex-6 XC6VLX75t Device Description
Accumulator width Output width Noise shaping Channels Phase_offset Optimization Latency Use_DSP48 LUT_FF pairs LUTs BRAM36/18s DSP48Es Frequency (speed grade Part
SFDR50
None none speed full
SFDR70
None none speed full
SFDR84
Dither none speed full
SFDR110
Taylor none speed full
XC6VLX75T-FF484-1
Test Case Descriptions
Small: This with SINE COSINE outputs, channel, SCLR, accumulator width bits, noise shaping, output bits, programmable frequency, phase offset. other parameters default values. Medium: This differs from Small that accumulator width bits, output phase angle bits. Large: This differs from medium that output width bits, phase angle bits, constant phase offset dithering noise shaping used. Taylor: This with accumulator width bits, channel, SCLR, output width bits, phase angle width bits, Taylor Series correction, full pipelining. Taylor Multichannel: This differs from EFF1 that channels. SFDR50: single-channel, dual output DDS, fully pipelined, with SCLR programmable phase increment, phase offset, optimized speed, with SDFR 50dB. SFDR70: SFDR50, with SFDR 70dB. SFDR84: SFDR50, with SFDR 84dB (using dithering). SDFR110: SFDR50, with SFDR (using Taylor correction).
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Version Changes
From Version version
Support Virtex-6 Spartan-6 been added.
From Version version
address port core been separated into channel select address port (ADDR) register select port (REG_SELECT). REG_SELECT replaces A(4) ADDR(3-0) replace A(3-0). reason this change that individual address lines present according core parameters. additional register been added following accumulator stages when DSP_use maximal when optimization goal speed. This increases maximum operating frequency, increases resource use, hence optional based optimization goal parameter.
Known Hazards
Subharmonic Frequencies
equations SFDR rely assumption that rounding errors from discretization phase amplitude incoherent. This assumption invalidated values Phase Increment which mutually prime with weight accumulator. anomalies, such spurii, will more prominent values PINC which have larger common factor with accumulator weight (2accumulator_width). This because such values will tend revisit same locations Lookup table, rounding errors will correlated. avoid this, avoid values Output Frequency which simple fractions example 3/8, 1/64. CR457411 multi-channel designs with phase offset, there circumstances which phase adjust value channel will fact apply channel (modulo number channels). example, three channel design (channels initial value phase offset dynamically programmed value phase offset channel will apply channel This defect applies only following circumstances: (Number channels (phase offset constant programmable) (DSP48 minimal (DSP48 maximal latency maximal less than maximal)). Maximal latency value when latency allocation automatic.
Design Examples
accepts system-level parameters instead low-level parameters such width phase accumulator, width phase angle, etc. Because this, requirements above entered into directly without having calculate low-level core details. also provides feedback hardware parameters translation system-level parameters low-level parameters been seen. Note that binary point POFF PINC registers fixed point, less precision required POFF register, data values must shifted right justified POFF register.
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Example
single-channel with system clock, frequency resolution accumulator width synthesize output 23.4 kHz, returns value 5FD8(hex), 24536(decimal). This will give synthesized frequency 24536/2^20 23399.35 application requires this modulated phase offsets, phase offset need only bits, these must bits data bus. Hence, phase offset cycle would entered 0.125 GUI. This returns value 20000(hex). This could entered 3-bit 001(binary). remaining bits POFF disregarded they will default zero.
Example (DDS requiring negative frequencies)
4-channel with 100MHz System Clock, Frequency Resolution 1Hz, Phase Width bits. Frequencies -3MHz, -1MHz, 1MHz 3MHz required. clock channel which System Clock/Number channels, that 25MHz this example. negative frequencies alias every legal range enter entered frequencies this example must 22MHz (Fs-3MHz), 24MHz (Fs-1MHz), 1MHz 3MHz respectively.
Support
Xilinx provides technical support this LogiCORE product when used described product documentation. Xilinx cannot guarantee timing, functionality, support product implemented devices that defined documentation, customized beyond that allowed product documentation, changes made section design labeled MODIFY.
Ordering Information
This core downloaded from Xilinx Center with Xilinx CORE Generator v11.2 later. Xilinx CORE Generator bundled with Alliance Series Software packages, additional charge. order Xilinx software, contact your local Xilinx sales representative. Information additional Xilinx LogiCORE modules available Xilinx Center.
Revision History
following table shows revision history this document. Date
09/28/06 11/30/06 05/17/07 03/24/08 06/24/09
Version
Initial Xilinx release.
Revision
Updated core release version 1.1. Updated core release version support Spartan-3A FPGAs. Updated core release version 2.1. Support VIrtex-6 Spartan-6 added.
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Notice Disclaimer
Xilinx providing this product documentation, hereinafter "Information," with warranty kind, express implied. Xilinx makes representation that Information, particular implementation thereof, free from claims infringement. responsible obtaining rights require implementation based Information. specifications subject change without notice. XILINX EXPRESSLY DISCLAIMS WARRANTY WHATSOEVER WITH RESPECT ADEQUACY INFORMATION IMPLEMENTATION BASED THEREON, INCLUDING LIMITED WARRANTIES REPRESENTATIONS THAT THIS IMPLEMENTATION FREE FROM CLAIMS INFRINGEMENT IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Except stated herein, none Information copied, reproduced, distributed, republished, downloaded, displayed, posted, transmitted form means including, limited electronic, mechanical, photocopying, recording, otherwise, without prior written consent Xilinx.
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