Product Specification Introduction Xilinx LogiCOREIP CORDIC

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Product Specification Introduction Xilinx LogiCOREIP CORDIC

Datasheet Thumbnail

Top Searches for this datasheet

CORDIC v4.DS249 April 2009
Product Specification
Introduction
Xilinx LogiCOREIP CORDIC core implements generalized coordinate rotational digital computer (CORDIC) algorithm.
with Xilinx CORE Generatorand Xilinx System Generatorv11.1 later.
General Description Features
Drop-in module Virtex®-6, Virtex-5, Virtex-4, Spartan®-6, Spartan-3/XA, Spartan-3A/XA/AN/3A Spartan-3E/XA FPGAs Functional configurations
CORDIC core implements generalized coordinate rotational digital computer (CORDIC) algorithm, initially developed Volder[1] iteratively solve trigonometric equations, later generalized Walther[2] solve broader range equations, including hyperbolic square root equations. CORDIC core implements following equation types: Rectangular Polar Conversion Trigonometric Hyperbolic Square Root
Vector rotation (polar rectangular) Vector translation (rectangular polar) Sinh Cosh Atan Atanh Square root
architectural configurations available CORDIC core: fully parallel configuration with single-cycle data throughput expense silicon area word serial implementation with multiple-cycle throughput occupying small silicon area
Optional coarse rotation module extend range CORDIC from first quadrant (+Pi/4 Pi/4 Radians) full circle Optional amplitude compensation scaling module compensate CORDIC algorithm's output amplitude scale factor Output rounding modes: Truncation, Round Infinity, Round Pos/Neg Infinity, Round Nearest Even Word serial architectural configuration small area Parallel architectural configuration high throughput Control internal add-sub precision Control number add-sub iterations Optional input output registers Optional control signals: SCLR, RFD, data formats: Signed Fraction, Unsigned Fraction, Unsigned Integer Phase data formats: Radian, Radian Fully synchronous design using single clock
coarse rotation performed rotate input sample from full circle into first quadrant. (The coarse rotation stage required CORDIC algorithm only valid over first quadrant). inverse coarse rotation stage rotates output sample into correct quadrant. CORDIC algorithm introduces scale factor amplitude result, CORDIC core provides option automatically compensating CORDIC scale factor. block diagram CORDIC core presented Figure
2002-2009 Xilinx, Inc. Xilinx, Inc. XILINX, Xilinx logo, Virtex, Spartan, other designated brands included herein trademarks Xilinx United States other countries. other trademarks property their respective owners.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
X-Ref Target Figure
Input Stage
X_IN Y_IN P_IN
CORDIC Engine
Shift Add-Sub Stages
Output Stage
X_OUT Y_OUT P_OUT
SCLR
CONTROL LOGIC
Figure CORDIC Symbol Pinout
Interface Pins
Table Core Pinout Port Name
X_IN [Input_Width-1:0] Y_IN [Input_Width-1:0] PHASE_IN [Input_Width-1:0] X_OUT [Output_Width-1:0] Y_OUT [Output_Width-1:0] PHASE_OUT [Output_Width-1:0]
Direction
Description
component input sample. Required depending Functional Configuration. component input sample. Required depending Functional Configuration. Phase component input sample. Required depending Functional Configuration. component output sample. Optional component output sample. Optional Phase component output sample. Optional sample input ports. Active high. Ready data sample. Active high. output data ready. Active high.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Table Core Pinout Port Name
SCLR
Direction
Clock. Active rising edge. Clock enable. Active high.
Description
Synchronous clear. Active high, SCLR priority over
Data Inputs
X_IN, Y_IN PHASE_IN data input ports CORDIC Core. data input ports read simultaneously form single input sample. width data input ports configured using parameter Input Width. data input ports optionally registered. data input ports required particular Functional Configuration automatically determined shown Table
Data Outputs
X_OUT, Y_OUT PHASE_OUT data output ports CORDIC core. default settings data output ports required particular Functional Configuration automatically determined shown Table modified from default settings user. width CORDIC data output ports using parameter Output Width. data output ports optionally registered. Table Input/Output Pins Functional Configuration1
Rotate Translate Sinh Cosh Tanh Root
XOUT
YOUT
POUT
Grey shading indicates port configurations that fixed selected function.
CORDIC Algorithm
CORDIC algorithm initially designed perform vector rotation, where vector (X,Y) rotated through angle yielding vector (X',Y'). Vector Rotation Equation
Equation
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
CORDIC algorithm performs vector rotation sequence successively smaller rotations, each angle atan(2-i), known micro-rotations. Equation shows expression iteration where iteration index from Expression microrotation
atan where direction rotation.
Equation
"Vector Rotation" "Vector Translation" details selecting Each micro-rotation stage expressed simple shift add/subtract operation. Equation shows Vector rotation expression iteration. Vector rotation expressed series micro-rotations
Equation
atan
atan
atan
CORDIC algorithm used generate either vector rotation vector translation.
Vector Rotation
Vector rotation rotates vector through angle yield vector (X',Y'), illustrated Figure Vector rotation performed selecting such that converges towards zero. i.e., when when Vector Rotation Equations
acos atan
Equation
Vector Translation
Vector translation rotates vector (X,Y) around circle until component equals zero illustrated Figure outputs from vector translation magnitude, phase, input vector (X,Y).
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Vector translation performed selecting such that converges towards zero. i.e., when Yi-1 when Yi-1 Vector Translation Equations
atan acos atan
Equation
CORDIC Scale Factor
outputs CORDIC algorithm, equations equivalent vector rotation vector translation scaled constant constant known CORDIC scale factor. CORDIC Scale Factor
acos atan
Equation
Taylor series expansion acos (atan (2-i 2-2i)-1/2. Hence, constant expressed
CORDIC scale factor, only dependent number iterations, Only functional configurations: Rotate, Translate, Rectangular Polar, Polar Rectangular affected CORDIC scale factor. When these functional configurations selected, CORDIC core provides option multiplying cancel scaling factor. "Advanced Configuration Parameters" detailed information.
Output Quantization Error
Output Quantization Error split into components; Output Quantization Error Input Quantization (OQEIQ) Output Quantization Error Internal Precision (OQEIP). OQEIQ quantization noise Phase inputs. vector rotation this input quantization noise results OQEIQ both outputs. vector translation this input quantization noise results OQEIQ output however OQEIQ phase output dependant ratio Thus small inputs effect input quantization noise OQEIQ greatly magnified. OQEIP limited precision internal calculations. CORDIC core default internal precision such that accumulated OQEIP less than OQEIQ. internal precision manually (input width output width log2(output_width)). This will reduce OQEIP (i.e. phase will calculated full precision regardless magnitude input vector). Output Quantization Error, CORDIC core with default internal precision, dominated OQEIQ. OQEIQ only reduced increasing number significant magnitude bits input vector (X,Y). Increasing internal precision zero padding inputs only affects OQEIP will have minimal effect total output quantization error.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
effect input quantization internal quantization CORDIC phase output quantization error illustrated following examples. Example quantization error phase output small input vector, (Xin_small, Yin_small). Xin_small "0000000001" 1/256. Yin_small "0000000001" 1/256. Vector translation with input quantization: Xin_ideal "0000000001" 1/256. Yin_ideal "0000000001" 1/256. Pout_ideal "0001100100" 0.79. Output quantization error input quantization: Xin_Quant Xin_small Yin_Quant Yin_small lsb. Xin_Quant "00000000001" 1/512. Yin_Quant "00000000011" 3/512. Pout_Quant "0010100000" =>1.25. OQEIQ abs( abs(Pout_Quant) abs(Pout_Ideal) OQEIQ "0000111100" 0.47. Output quantization error internal precision: Xin_cordic "0000000001" 1/256. Yin_cordic "0000000001" 1/256. Pout_cordic "0001111010" 0.95. OQEIP abs( abs(Pout_cordic) abs(Pout_Ideal) OQEIP "0000010110" 0.17. Example Quantization error phase output large input vector, (Xin_large, Yin_large). Xin_large "0100000000" 256/256. Yin_large "0100000000" 256/256. Vector translation with input quantization: Xin_ideal "0100000000" 256/256. Yin_ideal "0100000000" 256/256. Pout_ideal "0001100100" 0.79. Output quantization error input quantization: Xin_Quant Xin_large Yin_Quant Yin_small lsb. Xin_Quant "00111111111" 511/512. Yin_Quant "01000000001" 513/512. Pout_Quant "0001100101" =>0.79. OQEIQ abs( abs(Pout_Quant) abs(Pout_Ideal) OQEIQ "0000000001" 0.00. Output quantization error internal precision: Xin_cordic "0100000000" 256/256.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Yin_cordic "0100000000" 256/256. Pout_cordic "0001100100" 0.79. OQEIP abs( abs(Pout_cordic) abs(Pout_Ideal) OQEIP "0000000000" 0.Functional Description
Vector Rotation
Polar Rectangular Translation
When vector rotation functional configuration selected input vector, rotated input angle, using CORDIC algorithm. This generates scaled output vector, (X', Y'), shown Figure inputs, X_IN, Y_IN PHASE_IN, limited ranges given Table Inputs outside these ranges will produce unpredictable results. "Input/Output Data Representation" detailed information regarding CORDIC binary data formats. optional coarse rotation module provided extend range inputs, Phase, full circle. this functional configuration coarse rotation module selected default manually deselected user. "Advanced Configuration Parameters" detailed information. optional compensation scaling module provided compensate CORDIC scale factor this functional configuration compensation scaling module selected default manually deselected user. "Advanced Configuration Parameters" detailed information. Polar Rectangular Translation implemented setting functional configuration vector rotation, input vector (Mag, rotation angle shown Figure Vector rotation linear with respect magnitude, thus user scale input/output range, that rotated angle (X', then K*(X, rotated angle K*(X', Y').
X-Ref Target Figure
Zi.(X',Y') Output Vector (X',Y')
(X,Y) Input Vecto
Figure Vector Rotation
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
X-Ref Target Figure
Zi.(X',Y') Output Vector (X',Y')
Input Vector
Figure Polar Rectangular Conversion
Table Vector Rotation Signal
X_IN Y_IN PHASE_IN X_OUT Y_OUT X_IN<=1 Y_IN<=1 PHASE_IN -Sqrt(2) X_OUT<= Sqrt(2) -Sqrt(2) Y_OUT<= Sqrt(2)
Range
Description
Input Coordinate Input Coordinate Input Rotation Angle Output Coordinate Output Coordinate
Example Vector Rotation input vector, (Xin, Yin), output vector, (Xout, Yout) expressed pair fixed-point complement numbers with integer width 2-bits (1QN format). input rotation angle, radians, also expressed fixed-point complement number with integer width 3-bits (2QN format). Please refer "Input/Output Data Representation" section further information CORDIC binary data formats. this example, input/output width bits output vector (Xout, Yout) scaled compensate CORDIC scale factor. "0010110101" 00.10110101 0.707 "0001000000" 00.01000000 0.25 "1100110111" 110.0110111 -Pi/2 Xout "0001000001" 00.01000001 0.25 Yout "1101001011" 11.01001011 -0.707
Vector Translation
Rectangular Polar Translation
When vector translational functional configuration selected, input vector (X,Y) rotated using CORDIC algorithm until component zero. This generates scaled output magnitude, Mag(X,Y), output phase, Atan(Y/X), shown Figure inputs, X_IN Y_IN, limited ranges given Table Inputs outside these ranges will produce unpredictable results. "Input/Output Data Representation" detailed information regarding CORDIC binary data formats.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
optional coarse rotation module provided extend range inputs, full circle. this functional configuration coarse rotation module selected default manually deselected user. "Advanced Configuration Parameters" detailed information. optional compensation scaling module provided compensate CORDIC scale factor this functional configuration compensation scaling module selected default manually deselected user. "Advanced Configuration Parameters" detailed information. rectangular polar translation implemented setting functional configuration vector translation, input vector (X,Y), shown Figure Vector translation linear with respect magnitude, thus user scale input/output range; that vector translated (X', then vector K*(X, translated K*(X', phase angle zero length vector, (0,0), indeterminate output phase angle generated core will unpredictable. accuracy phase output from CORDIC vector translation algorithm limited number significant magnitude bits input vector Red>CORE Generator Parameters detailed information.
X-Ref Target Figure
(X,Y) Input Vector
Output Phase Zi.(Mag,0) Output (Mag,0)
Figure Vector Translation (Polar Rectangular)
Table Vector Translation Signal
X_IN Y_IN X_OUT PHASE_OUT
Range
X_IN Y_IN X_OUT Sqrt(2) Phase
Description
Input Coordinate Input Coordinate Output Magnitude Output Phase
Example Vector Translation individual input vector elements, (Xin, Yin), output magnitude, Xout, expressed fixed-point complement numbers with integer width 2-bits (1QN format). output phase angle, Pout radians, expressed fixed-point complement number with integer width 3-bits (2QN format). this example input/output width bits output Xout scaled compensate CORDIC scale factor. "0010110101" 00.10110101 0.707 "0001000000" 00.01000000 0.25
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
Xout "0011000000" 00.11000000 0.75 Pout "0000101011" 000.0101011 0.336
When functional configuration selected, unit vector rotated, using CORDIC algorithm, input angle, This generates output vector (Cos( Sin( input, PHASE_IN, limited range given Table Inputs outside this range will produce unpredictable results. "Input/Output Data Representation" detailed information regarding CORDIC binary data formats. optional coarse rotation module provided extend range input angle, full circle. this functional configuration coarse rotation module selected default manually deselected user. "Advanced Configuration Parameters" detailed information. compensation scaling module disabled functional configuration internally pre-scaled compensate CORDIC scale factor. Table Signal
PHASE_IN X_OUT Y_OUT
Range
PHASE_IN X_OUT Y_OUT
Description
Input Angle Output Cos( Output Sin(
Example input angle, Pin, expressed fixed-point complement number with integer width 3-bits (2QN format). output vector, (Xout, Yout), expressed pair fixed-point complement numbers with integer width 2-bits (1QN format). this example input/output width bits. Pin: "0001100100" 000.1100100 0.781 Xout "0010110110" 00.10110110 0.711 Yout "0010110100" 00.10110100 0.703
Sinh Cosh
When SinhCosh functional configuration selected, CORDIC algorithm used move vector (1,0) through hyperbolic angle, along hyperbolic curve shown Figure hyperbolic angle represents area under vector unrelated trigonometric angle. This generates output vector (Cosh(p), Sinh(p)). input hyperbolic angle, PHASE_IN, limited range given Table Inputs outside this range will produce unpredictable results. "Input/Output Data Representation" detailed information regarding CORDIC binary data formats. coarse rotation module disabled Sinh Cosh functional configuration, does apply hyperbolic transformations. compensation scaling module disabled Sinh Cosh functional configuration, internally pre-scaled compensate CORDIC hyperbolic scale factor.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
X-Ref Target Figure
Output Vector (Sinh, Cosh) Hyperbolic "Angle" (PHASE_IN) Input Vector(X_IN,0) Hyperbolic Curve
Figure Hyperbolic Sinh Cosh
Table Sinh Cosh Signal
PHASE_IN X_OUT Y_OUT
Range
-Pi/4 PHASE_IN Pi/4 X_OUT Y_OUT
Description
Input Hyperbolic Angle Output Cosh Output Sinh
Example Sinh Cosh input hyperbolic angle, Pin, expressed fixed-point complement number with integer width 3-bits (2QN format). output vector, (Xout, Yout), expressed pair fixed-point complement numbers with integer width 2-bits (1QN format). this example input/output width bits. "0001001110" 000.1001110 0.781 Xout "0100110001" 01.00110001 1.191 Yout "0010100110" 00.10100110 0.648
ArcTan
When functional configuration selected, input vector (X,Y) rotated (using CORDIC algorithm) until component zero. This generates output angle, Atan(Y/X). inputs, X_IN Y_IN, limited ranges given Table Inputs outside these ranges will produce unpredictable outputs. "Input/Output Data Representation" detailed information regarding CORDIC binary data formats. optional coarse rotation module provided extend range inputs full circle. this functional configuration coarse rotation module selected default manually deselected user. "Advanced Configuration Parameters" detailed information. compensation scaling module disabled functional configuration magnitude data output. ArcTan zero length vector, (0,0), indeterminate output angle generated core will unpredictable.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
accuracy output angle from CORDIC vector translation algorithm limited number significant magnitude bits input vector "Output Quantization Error" detailed information. Table ArcTan Signal
X_IN Y_IN PHASE_OUT X_IN Y_IN Phase
Range
Description
Input Coordinate Input Coordinate Output Angle
Example input vector (Xin, Yin) expressed pair fixed-point complement numbers with integer width 2-bits (1QN format). output angle, Pout radians, expressed fixed-point complement number with integer width 3-bits (2QN format). this example, input/output width bits. "0010100000" 00.10100000 0.625 "0010000000" 00.10000000 0.500 Pout "0001010110" 000.1010110=> 0.672
ArcTanh
When ArcTanh functional configuration selected, CORDIC algorithm used move input vector (X,Y) along hyperbolic curve (Figure until component reaches zero. This generates hyperbolic "angle," Atanh(Y/X). hyperbolic angle represents area under vector (X,Y) unrelated trigonometric angle. inputs, X_IN Y_IN, limited ranges given Table Inputs outside these ranges will produce unpredictable outputs. Additionally, Y_IN must less than equal (4/5 X_IN) CORDIC algorithm will converge. "Input/Output Data Representation" detailed information about CORDIC binary data formats. coarse rotation module disabled Tanh functional configuration, does apply hyperbolic transformations. compensation scaling module disabled Tanh functional configuration output magnitude data output.
X-Ref Target Figure
Input Vector (Xin, Yin) Hyperbolic "Angle" (Phase_out) Internal Vector(Xout,0) Hyperbolic Curve
Figure Hyperbolic ArcTan
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Table ArcTanh Signal
X_IN Y_IN PHASE_OUT X_IN Y_IN -X_IN Y_IN X_IN -Pi/2 Phase Pi/2
Range
Description
Input Coordinate Input Coordinate Output Hyperbolic Angle
Example Tanh input vector, (Xin, Yin), expressed pair fixed-point complement numbers with integer width 2-bits (1QN format). output, Pout, expressed fixed-point complement number with integer width 3-bits (2QN format). this example, input/output width bits. "0001100101" 00.01100101 0.395 "0001100101" 00.01100101 0.395 Pout "0001110001" 000.1110001=> 0.883
Square Root
When square root functional configuration selected simplified CORDIC algorithm used calculate positive square root input. input, X_IN, output, X_OUT, always positive both expressed either, unsigned fractions unsigned integers. When data format Unsigned Fraction, X_IN limited range: X_IN When data format Unsigned Integer, X_IN limited range: X_IN 2**Input Width, output width determined automatically based input width. "Input/Output Data Representation" detailed information regarding CORDIC binary data formats. coarse rotation module disabled because coarse rotation required Square Root functional configuration. compensation scaling module disabled because output compensation required Square Root functional configuration. Table Square Root Signal Range
Unsigned Fraction: X_IN Unsigned Integer: X_IN 2**Input Width Unsigned Fraction: X_OUT Unsigned Integer: X_OUT 2**[int(Input Width/2)+1]
Description
Input Value
X_IN
Output Square Root
X_OUT
Example Square Root Unsigned Fraction
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
input, Xin, output, Xout, expressed unsigned fixed-point number with integer width 1-bit. this example input/output width bits. "0000100000" 0.000100000 1/16 Xout "0010000000" 0.010000000 Example Square Root Unsigned Integer input, Xin, expressed unsigned integer. output, Xout, expressed unsigned integer. this example input width bits output width automatically bits. "0000100000" Xout :"000110"
Architectural Configuration
architectural configurations available CORDIC core: Parallel, with single-cycle data throughput large silicon area, Word Serial, with multiple-cycle throughput smaller silicon area.
Word Serial Architectural Configuration
CORDIC algorithm requires approximately shift-addsub operation each accuracy. CORDIC core implemented with word serial architectural configuration, implements these shift-addsub operations serially, using single shift-addsub stage feeding back output. word serial CORDIC core with output width latency cycles produces output every cycles. implementation size word serial CORDIC core directly proportional internal precision.
X-Ref Target Figure
Figure Word Serial Architecture Configuration
Parallel Architectural Configuration
CORDIC algorithm requires approximately shift-addsub operation each accuracy. CORDIC core with parallel architectural configuration implements these shift-addsub operations parallel using array shift-addsub stages. parallel CORDIC core with output width latency cycles produces output every cycle. implementation size parallel CORDIC core directly proportional internal precision times number iterations.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
X-Ref Target Figure
X_IN Y_IN PHASE_IN Shift Addsub Stages
X_OUT Y_OUT PHASE_OUT
Figure Parallel Architectural Configuration
Input/Output Data Representation
Data Signals
Data Signals are: X_IN, Y_IN, X_OUT Y_OUT. Functional Configurations, Rotate, Translate, Atan Data Signals represented using fixed-point complement numbers with integer width 2-bits. integer width fixed regardless word width, remainder bits used fractional portion number. Using Numbers Format" this representation described where word width also described Fix(N+2)_N using Mathworks® format. Input data signals, X_IN Y_IN, must range: input data signal Input data outside this range will produce unpredictable results. Using 10-bit word width, represented: "0100000000" 01.00000000 +1.0 "1100000000" 11.00000000 Square Root Functional Configuration, Data Signals, X_IN X_OUT, both represented either Unsigned Fractional Unsigned Integer data format. input data signal, X_IN, must range: X_IN when data format Unsigned Fraction range X_IN 2**Input Width when data format Unsigned Integer. When Unsigned Fractional data format been selected Data Signals represented using unsigned fixed-point number with integer with 1-bit. integer width fixed remainder word used represent fractional portion number. Using Mathworks® format this representation described UFix(N+1)_N, where number fractional bits being used defined word width Number format used represent signed complement numbers therefore suitable describe representation format used square root function.
Phase Signals
Phase Signals are: PHASE_IN PHASE_OUT. phase signals always represented using fixed-point complement number with integer width 3-bits. with data signals integer width fixed remaining bits used fractional portion number. Phase Signals require increased integer width accommodate increased range values they must represent when Phase Format Radians. When Phase Format Radians, PHASE_IN must range: (PHASE_IN) PHASE_IN outside this range will produce unpredictable results.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
2Q7, Fix10_7, format values, -Pi, represented: "01100100100" 011.00100100 +3.14 "10011011100" 100.11011100 3.14 When Phase Format Scaled Radians PHASE_IN must range: (PHASE_IN) PHASE_IN outside this range will produce unpredictable results. 2Q7, Fix10_7 format values, represented: "0010000000" 001.0000000 +1.0 "1110000000" 111.0000000
Numbers Format
format number 1+X+N complement binary number; sign followed integer bits followed mantissa (fraction). format used express numbers range 2(-N) equivalent notation using MathWorks® format, defined would Fix(1+X+N)_N. number using format equivalent number using Fix16_15 representation, number 1Q15 format equivalent number using Fix17_15 representation. Table Table contain examples Format Numbers Table Format Data: example Fix9_7) format number (Sign)
+Pi/4 -Pi/4
Fractional Bits
Table Format Phase: example Fix9_6) format number (Sign)
Fractional
Mapping different Data formats
Rotate, Translate, Atan Functional Configurations
Functional Configurations, Rotate, Translate, Atan possible alternative Data Signal formats fixed integer width fractional number used CORDIC. When input output width differ care must taken re-interpret CORDIC output.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
following example develops Example from "Vector Translation" section demonstrate possible remapping. Example Vector Translation function determines magnitude phase angle given input vector (X_IN, Y_IN). input output width bits. standard CORDIC data representation Fix10_8, alternative format being mapped onto CORDICs input Fix10_1. X_IN value: "0010110101" Table Example mapping alternative data format onto X_IN input
Sign Binary Value Fix10_8 weighting Fix10_1 weighting 0.707 90.5 Decimal Value
Y_IN value: "0001000000" Table Example mapping alternative data format onto Y_IN input
Sign Binary Value Fix10_8 weighting Fix10_1 weighting 0.25 Decimal Value
Below, Matlab® used generate expected results. Firstly magnitude phase angle standard CORDIC input format 1Q8, Fix10_8 generated: a=0.707+0.25j magnitude abs(a) magnitude 0.7499 phase_angle angle(a) phase_angle 0.3399 Secondly using mapped input format, Fix10_1: b=90.5+32j magnitude abs(b) magnitude 95.9909 phase_angle angle(b) phase_angle 0.3399 CORDIC output will X_OUT value: "0011000000" PHASE_OUT value: "0000101011"
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
Table Table demonstrate CORDICs output value being interpreted using data representation formats. Table Example X_OUT interpretation
Sign Binary Value Fix10_8 weighting Fix10_1 weighting 0.75 Decimal Value
Table Example PHASE_OUT interpretation
Sign Binary Value Fix10_7 weighting 0.336 Decimal Value
Example output width less than input width CORDIC reduces fractional width result When data output, X_OUT, being re-interpreted alternative data format value must scaled appropriately. following table demonstrates resulting decimal value change when output width reduced 8-bits. Table Example X_OUT interpretation with reduced output width
Sign Binary Value Fix8_6 weighting Fix8_0 weighting 0.75 Decimal Value
similar situation will arise when output width greater than input width. this circumstance CORDIC increases fractional width result. When data output being re-interpreted data format with fractional bits this will result increased magnitude. This output will then also need scaled appropriately.
Square Root Functional Configuration
Square Root Functional Configuration also possible other data formats onto CORDICs data format necessary re-interpret scale output. following example modifies Example from "Square Root" section. Example X_IN value: "00001000" Table Example mapping alternative data format onto X_IN input
Binary Value UFix8_7 weighting UFix8_1 weighting UFix8_0 weighting 0.0625 Decimal Value
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
expected output values each input format follows: UFix8_7 format: sqrt(0.0625) 0.25 UFix8_1 format: sqrt(4) UFix8_0 format: sqrt(8) 2.8284 CORDIC output will X_OUT value: "00100000" Table demonstrates output value directly interpreted each input formats. Table X_OUT direct interpretation
Binary Value UFix8_7 weighting UFix8_1 weighting UFix8_0 weighting 0.25 Decimal Value
Table shows that output value directly interpreted alternative data format wrong decimal value determined. output value must scaled correctly. output scaling determined follows. CORDIC core calculates square root input values range X_IN
alternative data format represents values range X_IN 2N+1 wish calculate:
Interpreting Xalt using standard CORDIC data format scales input 2-N, shown Table
Table shows directly re-interpreting CORDIC output alternative data formats results incorrect decimal value. This scale factor introduced remapping input square root function. This scaling factor introduced shown above, 2-N/2. corrected results shown below: UFix8_1 weighting: 16/2(6/2) UFix8_0 weighting: 32/2(7/2) 2.8284 When even scaling factor integer power two. This applied simply right shifting CORDIC output, X_OUT, N/2. example using UFix8_1 format demonstrates this with scaling factor 1/8. When scaling factor integer power two. This introduces additional output scaling factor example using UFix8_0 demonstrates this with scaling factor 2-7/2 2-3.5. This could implemented first scaling output right shift then multiplying more efficient would translate scaling input square root function.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
This demonstrated below where 2-N/2=2-M-(1/2).
scaling becomes simple divide right shift, input, X_IN, before applying square root function. Followed scaling output, X_OUT, 2-M. input value used UFix8_0 formatting example. Divided this gives Table shows that maps 1/32 CORDIC input range. sqrt(1/32) 0.17678 0.0010110 Table show that CORDIC output value, 0.0010110, will decimal value UFix8_0 formatting. Applying output scaling 2-3, 1/8, gives 2.75. lost accuracy representing sqrt(1/32) using only 8-bits. full accuracy result used then re-interpreted alternative data format (Fix8_0) then scaled, correct result obtained. e.g. sqrt(1/32) 2.8284
CORE Generator Parameters
CORDIC Graphical User Interface (GUI) contains three pages configuring core information tabs:
Symbol Implementation Details
Symbol illustrates core pinout. Implementation Details displays core's latency resource usage. Please note that BRAM Mult/DSP Slice resources only utilized when Compensation Scaling selected.
Page
Used configure functional selection architecture CORDIC core. Component Name: Used base name output files generated core. Names must begin with letter composed from following characters: "_." Functional Selection: following functional selections available: Rotate, Cos, Tan, Square Root, Translate, Sinh Tanh. "Functional Description" section detailed information each supported functions. general, X_IN, Y_IN, X_OUT Y_OUT express signed binary numbers format PHASE_IN PHASE_OUT express signed binary numbers format. When Square Root selected, data formats available: Unsigned Integer Unsigned Fraction. details about CORDIC binary data formats "Input/Output Data Representation". Architectural Configuration: architectural configurations available CORDIC core, Parallel Word Serial. Refer "Architectural Configuration" more details. Pipelining Mode: CORDIC core provides three pipelining modes: None, Optimal, Maximum. choice pipelining mode based selection Functional Configuration Architectural Configuration. Unavailable pipelining modes greyed GUI.
None: CORDIC core implemented without pipelining. Optimal: CORDIC core implemented with many stages pipelining possible without using additional LUTs.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Maximum: CORDIC core implemented with pipeline after every shift-add stage.
Page
Used configure phase magnitude data formats, rounding mode input-outputs. Data Format: CORDIC core provides three formats expressing components data samples:
Signed Fraction: Default setting. inputs outputs expressed fixed-point complement numbers with integer width 2-bits. Example: "11100000" represents value -0.5. Unsigned Fraction: inputs outputs expressed unsigned fixed-point number with integer with 1-bit. Available only Square Root functional configuration. Example: "11100000" represents value +1.75. Unsigned Integer: inputs outputs express unsigned integers. Available only Square Root functional configuration. Example: "11100000" represents value +224. Radians: phase expressed fixed-point complement numbers with integer width 3-bits, radian units. Example: "01100000" represents value radians. Scaled Radians: phase expressed fixed-point complement numbers with integer width 3-bits, with pi-radian units. scaled-radian equals radians. Example: "11110000" represents value -0.5 radians.
Phase Format: CORDIC core provides Phase Format options:
"Input/Output Data Representation" detailed information about CORDIC binary data formats. Input Output Options: CORDIC core provides four input output common configuration options.
Input Width: Input Width controls widths input ports, X_IN, Y_IN PHASE_IN. Input Width configured range bits. Register Inputs: Selects input signals X_IN, Y_IN, PHASE_IN registered. Output Width: Output Width controls widths output ports, X_OUT, Y_OUT, PHASE_OUT. Output Width configured range bits. Register Outputs: Selects output signals, X_OUT, Y_OUT, PHASE_OUT registered.
Round Mode: CORDIC core provides four rounding modes. Table illustrates behavior different Rounding modes.
Truncate: X_OUT, Y_OUT, PHASE_OUT outputs truncated. Positive Infinity: X_OUT, Y_OUT, PHASE_OUT outputs rounded such that rounded (towards positive infinity). equivalent MATLAB® function floor(x+0.5). Infinity: outputs X_OUT, Y_OUT, PHASE_OUT rounded such that rounded (towards positive infinity) -1/2 rounded down (towards negative infinity). equivalent MATLAB® function round(x).
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
Nearest Even: X_OUT, Y_OUT, PHASE_OUT outputs rounded toward nearest even number such that rounded down rounded
Table Rounding Modes Truncate
1.50 1.00 0.50 0.25 0.00 0.25 0.50 0.75
Infinity Positive Infinity
Nearest Even
Page
Provides options advanced configuration parameters (Coarse Rotation, Iterations, internal Precision, Compensation Scaling) optional control signals. Advanced Configuration Parameters
Iterations: Controls number internal add-sub iterations perform.When Iterations zero, number iterations performed determined required accuracy output. default, Iterations zero, thus number iterations automatically determined. Precision: Configures internal precision add-sub iterations. When Precision zero, internal precision determined automatically based required accuracy output number internal iterations. default, Precision zero, thus internal precision automatically determined. When Precision (input width output width log2(output_width)) output phase precise full output width regardless input magnitude. However, output phase accuracy still limited OQEIQ component "Output Quantization Error" number Iterations Cordic Micro-Rotation block. Coarse Rotation: Controls instantiation coarse rotation module. Instantiation coarse rotation module default following functional configurations: Vector rotation, Vector translation, Cos, Tan. Coarse Rotation turned these functions then input/output range limited first quadrant (-Pi/4 Pi/4). Coarse rotation required Sinh Cosh, Arctanh, Square Root configurations. standard CORDIC algorithm operates over first quadrant. Coarse Rotation extends CORDIC operational range full circle rotating input sample into first quadrant inverse rotating output sample back into appropriate quadrant. Compensation Scaling: Controls compensation scaling module used compensate CORDIC magnitude scaling. CORDIC magnitude scaling affects Vector Rotation Vector Translation functional configurations, does affect SinCos, SinhCosh, ArcTan, ArcTanh Square Root functional configurations. latter configurations, compensation scaling Scale Compensation. CORDIC magnitude scaling side effect CORDIC algorithm. magnitude outputs, generated scaled CORDIC scale factor, compensation scaling module compensates effect CORDIC magnitude scaling scaling outputs, 1/Zn.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Scale Compensation: outputs will compensated will generated scaled ratio Based: outputs compensated using LUT-based Constant Coefficient Multiplier. BRAM: outputs compensated using BRAM-based Constant Coefficient Multiplier. Embedded Multiplier: outputs compensated using XtremeDSPSlice embedded multiplier depending family part chosen Coregen project options.
Optional Selection
Control Signals: RDY,SCLR, control signals optional. presence control signals determined based selected Architectural Configuration, Pipelining Mode, Register Inputs, Register Outputs. Output Signals: X_OUT, Y_OUT PHASE_OUT optional. default states these signals determined based selected functional configuration manually overridden user. Refer Table more information.
System Generator Parameters
This section details parameters that differ from CORE Generator GUI. "CORE Generator Parameters" more detailed information about other parameters.
Page
When Word Serial architectural configuration selected System Generator block will operate system sample period. core's control signal should used determine control when input sample applied core. Refer "Control Signals Timing" more details core's control signals. Please refer "Page "CORE Generator Parameters" section details each parameters.
Page
input width parameter been abstracted value taken from input ports System Generator block. input output registers always enabled. Please refer "Page "CORE Generator Parameters" section details each parameters.
Page
System Generator block renames SCLR RST. Please refer "Page "CORE Generator Parameters" section details each parameters.
Implementation
Please refer System Generator documentation information regarding FPGA Area Estimation parameter.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
Control Signals Timing
following section describes control signals used CORDIC core. control signals synchronous rising edge CLK. timing diagram CORDIC core with Word Serial Architectural Configuration shown Figure timing diagram CORDIC core with Parallel Architectural Configuration shown Figure
core operations synchronous with rising edge (Clock) input. mandatory when core pipelined Registered Inputs/Outputs have been selected. Otherwise, present.
When (New Data) input high, input data sampled same rising clock edge. ignored low. mandatory when Word Serial architecture been selected. Otherwise, optional.
(Ready Data) indicates that core ready sample input data. signal high upon startup during reset. mandatory when Word Serial architecture been selected. Otherwise, present.
(Ready) output signals that valid data sample present Data Output Ports. pulsed high first clock cycle valid data output. signal upon startup during reset. mandatory when Word Serial architecture been selected. Otherwise, optional.
SCLR
When SCLR asserted (High), core flip-flops synchronously initialized. core remains this state until SCLR de-asserted. SCLR optional. SCLR priority over
When (Clock Enable) Low, synchronous inputs ignored core remains current state. optional.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Word Serial Timing
X-Ref Target Figure
ltip
Figure Control Signal Timing Diagram (Word Serial Architecture)
Parallel Architecture Timing
X-Ref Target Figure
ltip
Figure Control Signal Timing Diagram (Parallel Architecture)
Migrating CORDIC v4.0 from CORDIC v3.The CORE Generator core update functionality used update existing file from CORDIC v3.0 CORDIC v4.0. more information this feature, CORE Generator documentation.
Parameter changes
CORDIC v4.0 does support ACLR, Synchronization Enable Create parameters. Compensation Scaling options have changed from: No_Scale_Compensation, CCM_Scale_Compensation Block_Multiplier No_Scale_Compensation, LUT_Based, BRAM_based Embedded_Multiplier.
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
Where CCM_Scale_Compensation LUT_Based Block_Multiplier Embedded_Multiplier BRAM_based option. other parameters unchanged.
Port changes
CORDIC v4.0 does support ACLR control port. other port names widths remain same.
Performance Resource Utilization
Table through Table performance resource usage information number different core configurations. maximum clock frequency results were obtained double-registering input output ports reduce dependence placement. inner level registers used separate clock signal measure path from input registers first output register through core. resource usage results include above "characterization" registers represent true logic used core. counts include SRL16s SRL32s (according device family). options used were: "map high" options used were: "par high" Table contains characterization data Virtex-5 using XC5VSX35T-1FF665. results have been generated with automatically determined Iterations Precision, Coarse Rotation, Compensation Scaling Maximum Pipelining. Table Virtex-5 characterization data Function
Rotate
Architecture
Word Serial
Input/Output Width
Round Mode
Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate
LUT-FF pairs
1221 1863 1179 4023 8524 1490 1179 4023 8416
Maximum Clock Frequency (Mhz)
Parallel
Translate
Word Serial
Parallel
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Table Virtex-5 characterization data Function
Architecture
Word Serial
Input/Output Width
Round Mode
Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate
LUT-FF pairs
1376 1093 3812 8126 1000 1185 3999 8274 1550
Maximum Clock Frequency (Mhz)
Parallel
tanh
Word Serial
Parallel
Square Root
Parallel
Table contains characterization data Spartan 3ADSP using XC3SD1800A-4FG676. results have been generated using same default parameters Virtex-5. Table Spartan-3A characterization data Function
Rotate
Architecture
Word Serial
Input/Output Width
Round Mode
Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate
Slices
1292 2122 4352 1090 2189 4147
Maximum Clock Frequency (Mhz)
Parallel
Translate
Word Serial
Parallel
DS249 April 2009 Product Specification
www.xilinx.com
CORDIC
Table Spartan-3A characterization data Function
Architecture
Word Serial
Input/Output Width
Round Mode
Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate Truncate Nearest Even Truncate
Slices
1066 1983 4147 2178 4363 1939
Maximum Clock Frequency (Mhz)
Parallel
tanh
Word Serial
Parallel
Square Root
Parallel
References
Volder, "The CORDIC Trigonometric Computing Technique" Trans. Electronic Computing, Vol. EC-8, Sept. 1959, pp330-334 Walther, J.S., Unified Algorithm Elementary Functions," Spring Joint computer conf., 1971, proc., pp379-385
Ordering Information
This core downloaded from Xilinx Center with Xilinx CORE Generator v11.1 later. Xilinx CORE Generator system shipped with Xilinx FoundationSeries Development software. order Xilinx software, contact your local Xilinx sales representative. Information additional Xilinx LogiCORE modules available Xilinx Center.
www.xilinx.com
DS249 April 2009 Product Specification
CORDIC
Revision History
Date
03/28/03 03/28/03 03/28/03 05/21/04 04/28/05 04/24/09
Version
Revision
Revision History added document. Updated Hyperbolic Transformations PiRadian format. Improved parameterization, rounding modes, data formats. Added Virtex-4 support update v6.2i Xilinx CORE Generator system. Updated indicate support Spartan-3E Xilinx software v7.1i. Updated include support Virtex-6, Virtex-5, Spartan-6 Spartan-3A/3A devices.
Notice Disclaimer
Xilinx providing this design, code, information (collectively, "Information") "AS-IS" with warranty kind, express implied. Xilinx makes representation that Information, particular implementation thereof, free from claims infringement. responsible obtaining rights require implementation based Information. specifications subject change without notice. XILINX EXPRESSLY DISCLAIMS WARRANTY WHATSOEVER WITH RESPECT ADEQUACY INFORMATION IMPLEMENTATION BASED THEREON, INCLUDING LIMITED WARRANTIES REPRESENTATIONS THAT THIS IMPLEMENTATION FREE FROM CLAIMS INFRINGEMENT IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Except stated herein, none Information copied, reproduced, distributed, republished, downloaded, displayed, posted, transmitted form means including, limited electronic, mechanical, photocopying, recording, otherwise, without prior written consent Xilinx.
DS249 April 2009 Product Specification
www.xilinx.com

Product Specification Introduction Xilinx LogiCOREIP CORDIC

Top Searches for this datasheet

Other recent searches