74LCX07 Voltage Buffer with Open Drain Outputs tolerant inputs 2.
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74LCX07 Voltage Buffer with Open Drain Outputs
74LCX07 Voltage Buffer with Open Drain Outputs
tolerant inputs 2.3V 5.5V specifications provided 2.9ns max. (VCC 3.3V), 10µA max. Power down high impedance inputs outputs +24mA output drive (VCC 3.0V) Implements patented noise/EMI reduction circuitry Latch-up performance exceeds JEDEC conditions performance:
General Description
LCX07 contains buffers. inputs tolerate voltages allowing interface systems systems. outputs LCX07 open drain connected other open drain outputs implement active HIGH wire active wire functions. 74LCX07 fabricated with advanced CMOS technology achieve high speed operation while maintaining CMOS power dissipation.
Human body model 2000V Machine model 200V Leadless DQFN package
Ordering Information
Order Number
74LCX07M 74LCX07SJ 74LCX07BQX(1) 74LCX07MTC
Package Number
M14A M14D MLP14A MTC14
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide 14-Terminal Depopulated Quad Very-Thin Flat Pack Leads (DQFN), JEDEC MO-241, 3.0mm 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Note: DQFN package available Tape Reel only. Device also available Tape Reel. Specify appending suffix letter ordering number. packages lead free JEDEC: J-STD-020B standard.
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Connection Diagram
Assignments SOIC, SOP, TSSOP
Logic Symbol
IEEE/IEC
Assignments DQFN
(Top Through View)
Description
Names
Description
Inputs Outputs
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Absolute Maximum Ratings
Stresses exceeding absolute maximum ratings damage device. device function operable above recommended operating conditions stressing parts these levels recommended. addition, extended exposure stresses above recommended operating conditions affect device reliability. absolute maximum ratings stress ratings only.
Symbol
Supply Voltage Input Voltage
Parameter
Rating
-0.5V +7.0V -0.5V +7.0V State(2) -0.5V +7.0V -50mA -50mA +50mA ±50mA ±100mA ±100mA -65°C +150°C
Output Voltage, Output HIGH Input Diode Current, Output Diode Current
IGND TSTG
Output Current Supply Current Supply Ground Current Ground Storage Temperature
Note: Absolute Maximum Rating must observed.
Recommended Operating Conditions(3)
Recommended Operating Conditions table defines conditions actual device operation. Recommended operating conditions specified ensure optimal performance datasheet specifications. Fairchild does recommend exceeding them designing absolute maximum ratings.
Symbol
Supply Voltage Operating Data Retention Input Voltage Output Voltage Output Current 4.5V-5.5V 3.0V-3.6V 2.7V-3.0V 2.3V-2.7V
Parameter
Min.
Max.
Units
Free-Air Operating Temperature Input Edge Rate, 0.8V-2.0V, 3.0V
Note: Unused inputs must held HIGH LOW. They float.
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Electrical Characteristics
-40°C +85°C Symbol
Parameter
HIGH Level Input Voltage
2.3-2.7 2.7-3.6 4.5-5.5
Conditions
Min.
Max.
Units
Level Input Voltage
2.3-2.7 2.7-3.6 4.5-5.5
100µA 12mA 16mA 24mA 32mA 5.5V 5.5V 3.6V 5.5V 0.6V 5.5V 0.55 0.55 ±5.0
Level Output Voltage
2.3-5.5
IOFF IOHZ
Input Leakage Current Power-Off Leakage Current Quiescent Supply Current Increase Input State Current
2.3-5.5 2.3-5.5 2.3-5.5 2.3-3.6 4.5-5.5 2-5.5
Electrical Characteristics
-40°C +85°C, 5.0V 0.5V, 3.3V 0.3V, 50pF 50pF Symbol Parameter Min.
2.7V, 50pF
2.5V 0.2V, 30pF
Max.
Min.
Max.
Units
tPZL, tPLZ Propagation Delay Time
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Dynamic Switching Characteristics
25°C Symbol
VOLP VOLV
Parameter
Quiet Output Dynamic Peak Quiet Output Dynamic Valley
Conditions
50pF, 3.3V, 30pF, 2.5V, 50pF, 3.3V, 30pF, 2.5V,
Typical
-0.8 -0.6
Unit
Capacitance
Symbol
COUT
Parameter
Input Capacitance Output Capacitance Power Dissipation Capacitance
Conditions
Open, 3.3V, 3.3V, VCC, 10MHz
Typical
Units
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Loading Waveforms
Test
tPZL, tPLZ
Switch
0.5V 0.3V 0.2V
Figure Test Circuit includes probe capacitance)
3-STATE Output Enable Disable Times Logic
trise tfall
Symbol
5.0V 0.5V
0.3V 0.3V
3.3V 0.3V
1.5V 1.5V 0.3V 0.3V
2.7V
1.5V 1.5V 0.3V 0.3V
2.5V 0.2V
0.15V 0.15V
Figure Waveforms (Input Pulse Characteristics; =1MHz, 3ns)
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Tape Reel Specification
Tape Format DQFN
Package Designator
Tape Section
Leader (Start End) Carrier Trailer (Hub End)
Number Cavities
(Typ.) 3000 (Typ.)
Cavity Status
Empty Filled Empty
Cover Tape Status
Sealed Sealed Sealed
Tape Dimensions inches (millimeters)
Reel Dimensions inches (millimeters)
Tape Size
12mm
13.0 (330.0)
0.059 (1.50)
0.512 (13.00)
0.795 (20.20)
2.165 (55.00)
0.488 (12.4)
0.724 (18.4)
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Physical Dimensions
8.75 8.50 7.62
0.65
5.60 6.00 4.00 3.80
INDICATOR
1.70
1.27
1.27 (0.33)
0.51 0.35
0.25
LAND PATTERN RECOMMENDATION
1.75 1.50 1.25 0.25 0.10
0.10
DETAIL
0.25 0.19
NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS JEDEC MS-012, VARIATION ISSUE DIMENSIONS MILLIMETERS. DIMENSIONS INCLUDE MOLD GAGE PLANE FLASH BURRS. LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 DRAWING CONFORMS ASME Y14.5M-1994 DRAWING FILE NAME: M14AREV13
0.50 0.25 R0.10 R0.10
0.90 0.50 (1.04)
DETAIL
SCALE: 20:1
SEATING PLANE
Figure 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings provided service customers considering Fairchild components. Drawings change manner without notice. Please note revision and/or date drawing contact Fairchild Semiconductor representative verify obtain most recent revision. Package specifications expand terms Fairchild's worldwide terms conditions, specifically warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area most recent package drawings:
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Physical Dimensions (Continued)
Figure 14-Lead Small Outline Package (SOP), EIAJ TYPE 5.3mm Wide
Package drawings provided service customers considering Fairchild components. Drawings change manner without notice. Please note revision and/or date drawing contact Fairchild Semiconductor representative verify obtain most recent revision. Package specifications expand terms Fairchild's worldwide terms conditions, specifically warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area most recent package drawings:
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Physical Dimensions (Continued)
Figure 14-Terminal Depopulated Quad Very-Thin Flat Pack Leads (DQFN), JEDEC MO-241, 3.0mm
Package drawings provided service customers considering Fairchild components. Drawings change manner without notice. Please note revision and/or date drawing contact Fairchild Semiconductor representative verify obtain most recent revision. Package specifications expand terms Fairchild's worldwide terms conditions, specifically warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area most recent package drawings:
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
Physical Dimensions (Continued)
0.43
0.65
1.65
0.45
6.10
12.00° R0.09
BOTTOM
CONFORMS JEDEC REGISTRATION MO-153, VARIATION NOTE DIMENSIONS MILLIMETERS DIMENSIONS EXCLUSIVE BURRS, MOLD FLASH, EXTRUSIONS DIMENSIONING TOLERANCES ANSI Y14.5M, 1982 LANDPATTERN STANDARD: SOP65P640X110-14M DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings provided service customers considering Fairchild components. Drawings change manner without notice. Please note revision and/or date drawing contact Fairchild Semiconductor representative verify obtain most recent revision. Package specifications expand terms Fairchild's worldwide terms conditions, specifically warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area most recent package drawings:
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
74LCX07 Voltage Buffer with Open Drain Outputs
TRADEMARKS following includes registered unregistered trademarks service marks, owned Fairchild Semiconductor and/or global subsidiaries, intended exhaustive list such trademarks. ACEx® Build NowCorePLUSCROSSVOLTCTLCurrent Transfer LogicEcoSPARK® EZSWITCH*
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PDP-SPMPower220® POWEREDGE® Power-SPMPowerTrench® Programmable Active DroopQFET® QSQT OptoelectronicsQuiet SeriesRapidConfigureSMART STARTSPM® STEALTHSuperFETSuperSOT-3 SuperSOT-6 SuperSOT-8
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Power Franchise®
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EZSWITCHand FlashWriter® trademarks System General Corporation, used under license Fairchild Semiconductor. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES RIGHT MAKE CHANGES WITHOUT FURTHER NOTICE PRODUCTS HEREIN IMPROVE RELIABILITY, FUNCTION, DESIGN. FAIRCHILD DOES ASSUME LIABILITY ARISING APPLICATION PRODUCT CIRCUIT DESCRIBED HEREIN; NEITHER DOES CONVEY LICENSE UNDER PATENT RIGHTS, RIGHTS OTHERS. THESE SPECIFICATIONS EXPAND TERMS FAIRCHILD'S WORLDWIDE TERMS CONDITIONS, SPECIFICALLY WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS AUTHORIZED CRITICAL COMPONENTS LIFE SUPPORT DEVICES SYSTEMS WITHOUT EXPRESS WRITTEN APPROVAL FAIRCHILD SEMICONDUCTOR CORPORATION. used herein: Life support devices systems devices systems which, intended surgical implant into body support sustain life, whose failure perform when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. PRODUCT STATUS DEFINITIONS Definition Terms Datasheet Identification Advance Information Product Status Formative Design Definition This datasheet contains design specifications product development. Specifications change manner without notice. This datasheet contains preliminary data; supplementary data will published later date. Fairchild Semiconductor reserves right make changes time without notice improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves right make changes time without notice improve design. This datasheet contains specifications product that been discontinued Fairchild Semiconductor. datasheet printed reference information only.
Rev.
critical component component life support, device, system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Preliminary
First Production
Identification Needed
Full Production
Obsolete
Production
©1999 Fairchild Semiconductor Corporation 74LCX07 Rev. 1.11.0
www.fairchildsemi.com
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