Timing Operation Solid-State Reliability Color Monochrome Operation Fi
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SN28837 1/2-INCH TIMER
Timing Operation Solid-State Reliability Color Monochrome Operation Five Selectable Antiblooming Modes Variable-Integration-Time Option Surface-Mount Package Clamp Pulse-Select Option Horizontal Vertical Resets External Synchronization
PACKAGE (TOP VIEW) GT1/SH3 GT3/SH2 CLK13M BCP1 BCP2 CSYNC CBLK SCBLK HGATE TESTA
description
SN28837 monolithic integrated circuit designed supply timing signals Texas Instruments 8-mm-diagonal TC276 (PAL color) TC277 (PAL monochrome) image sensors. SN28837 supplies both CCD-drive signals PAL-television synchronization signals standard video rates. requires single supply voltage 13.37-MHz crystal oscillator input. SN28837 provides user with several options including multiple antiblooming modes, variable integration time, external synchronization, clamp pulse selection, delayed horizontal transfer.
VCC1 ABIN
internal connection
SN28837 designed drive image sensor through intermediary level-shifting devices such TMS3473B parallel driver SN28846 serial driver. also supplies sample-and-hold signals TL1593 3-channel sample-and-hold circuit multiplex signals TL1051 video preprocessor. color applications, SN28837 interfaces with SN28838 color subcarrier generator generate color subcarrier. SN28837 supplied 60-pin plastic flat package characterized operation from -20°C 45°C.
This device contains circuits protect inputs outputs against damage high static voltages electrostatic fields. These circuits have been qualified protect this device against electrostatic discharges (ESD) according MIL-STD-883C, Method 3015; however, precautions should taken avoid application voltage higher than maximum-rated voltages these high-impedance circuits. During storage handling, device leads should shorted together device should placed conductive foam. circuit, unused inputs should always connected appropriate logic voltage level, preferably either ground. Specific guidelines handling devices this type contained publication Guidelines Handling (ESDS) Devices Assemblies available from Texas Instruments.
Copyright 1991, Texas Instruments Incorporated
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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TESTB TESTC VGATE ABS0 ABS1 ABS2 HIGH
SN28837 1/2-INCH TIMER
functional block diagram
Oscillator CLK13M BCP1 BCP2 CSYNC CBLK SCBLK TESTA TESTB TESTC VGATE HGATE
Divide
Horizontal Counter
Decoder Vertical Counter
Clock Generator
Antiblooming Generator ABS0 ABS1 ABS2
ABIN
Serial Generator
GT3/SH2 GT1/SH3
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SN28837 1/2-INCH TIMER
Terminal Functions
TERMINAL NAME ABIN ABS0 Antiblooming levels these three terminals determine which five antiblooming modes selected: Mode ABS2 ABS1 ABS0 Operation pulses 2-MHz burst pulses 1-MHz burst pulses 1-MHz continuous pulses 2-MHz continuous pulses Mode used normal operation. BCP1 BCP2 CBLK CLK13M CSYNC Optical black clamp Optical black clamp Burst flag Composite blank 3.34-MHz clock (factory test point) 13-MHz clock (connect SN28838 color-subcarrier generator color operation) Clamp (signal processing) Clamp (signal processing) Composite sync Delay select When high, three serial transfer pulses occur early relative sample-and-hold pulses SH1, SH2, SH3. When low, three serial transfer pulses occur late relative sample-and-hold pulses. Field index Ground Exposure control: gates outputs (see description GPS). When high, timer operates normal-integration-time mode (tint connected internally operate imager variable-integration-time mode, must held user-defined logic circuit must inserted between vary integration time (see Figure TMS3473B parallel driver MIDSEL input switch GT1/SH3 used logic signal both gate TL1051 video preprocessor sample-and-hold channel TL1593 3-channel sample-and-hold circuit. gate TL1051 video preprocessor GT3/SH2 used logic signal both gate TL1050 video preprocessor sample-and-hold channel TL1593 3-channel sample-and-hold circuit. Horizontal counter reset Decoded count signal. HGATE test point used normal operation. used (tie high) pulse (for SECAM operation) Line switch (connect SN28838 color operation) connect Power down. logic level causes device enter power-consumption mode. Parallel-image-area gate clock Parallel-storage-area gate clock Standby mode select. When high, normal operation selected; when low, power-down mode selected. Subcarrier blank (for SECAM applications) DESCRIPTION
ABS1
ABS2
GT1/SH3 GT3/SH2 HGATE HIGH SCBLK
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SN28837 1/2-INCH TIMER
Terminal Functions (Continued)
TERMINAL NAME TESTA TESTB TESTC VCC1 VGATE Second field index Sample hold Serial clock Serial clock Serial clock Transfer-gate clock Test (factory test point) Test (factory test point) Test (factory test point) power Oscillator power Vertical-counter reset Vertical drive Vertical-dump speed. When high, vertical-dump frequency MHz; when low, vertical-dump frequency MHz. Real display area signal. test point used normal operation. Decoded count signal. VGATE test point used normal operation. Crystal oscillator DESCRIPTION
SN28837
NOTE: SN28837 designed with crystal oscillator. connect terminals directly external driver outputs.
Figure Connection External Crystal Oscillator SN28837
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SN28837 1/2-INCH TIMER
variable-integration-time mode
addition normal mode operation, SN28837 timing generator offers optional variable-integration mode with TC276 TC277 area-array image sensors. variable-integration mode selected applying logic level pin. This logic level disables vertical drive signal (VD) from controlling, internal timer, image-area storage-area parallel transfer signal (GP). Prior start integration period, charge that accumulated image area must transferred out. order flush this previous signal dark-current charge from image area, signal pulsed times. Each pulse generates pulses image-area storage-area gate transfer signals that shift unwanted charge into clearing drain. This clearing function should performed during high time signal (refer Figure through Figure 13). integration period continues long remains high. must held logic level prevent from controlling internally. integration ceases readout occurs when pulsed simultaneously; this accomplished taking high logic level. readout timing dependent vertical drive pulse; this means that total integration time multiple 1/50 second plus time interval between last pulse next pulse. image readout occurs within normal 1/50-second readout interval. integration time less than 1/50 second, normal output operation occurs; integration time greater than 1/50 second, frame buffer required order capture image. Integration times greater than 1/50 second result image degradation temperatures greater than 25°C dark-current generation. degradation seen decrease dynamic range (contrast) increase noise. recommended that image sensor cooled long-exposure operation. dark-current generation reduced factor each temperature decrease. sensor operates well 30°C.Cooling accomplished using thermoelectric Peltier cooler attached image sensor. Condensation header must prevented isolating cooled sensor from moist air. Vacuum isolation preferred; however, continual flushing nitrogen across header also prevent condensation.
tint Transfer Pulse
Flush Pulses
Figure Flush Transfer Pulses
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SN28837 1/2-INCH TIMER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Input voltage range, Output voltage range, Operating free-air temperature range, 30°C 75°C Storage temperature range 55°C 125°C Lead temperature (1/16 inch) from case seconds 260°C Continuous total power dissipation
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE voltage values with respect terminal.
recommended operating conditions
Supply voltage, High-level input voltage, Low-level input voltage, Operating frequency Power-up time Operating free-air temperature, 13.375 UNIT
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER GT3/SH2 GT1/SH3 other outputs GT3/SH2 GT1/SH3 other outputs TEST CONDITIONS UNIT
IDD(AV) Average supply current IDD(S) Standby supply current HCR, inputs Schmitt-trigger inputs with 0.1-V hysteresis. inputs except have pullup current sources.
switching characteristics over recommended operating free-air temperature range,
PARAMETER Rise time Fall time Frequency Pulse duration GT1/SH3 GT3/SH2 other outputs GT1/SH3 GT3/SH2 other outputs SH1, GT2, GT1/SH3, GT3/SH2 SH1, GT2, GT1/SH3, GT3/SH2 TEST CONDITIONS 4.458333 UNIT
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SN28837 1/2-INCH TIMER
Field 1246 1254 1262 1270 1278 1286 1294 1302 1310 1862 1870 Field 1875 1878
Vertical Scale CSYNC
1238
1886
1894
1902
1910
1918
1926
1255 1260 1265
1875
1880 1885 1890
1250
1300
1875
1925
CBLK
1248 1268 1872 1892
1250 1265 1875 1890
1250 1268 1286 1300 1875 1892 1910 1925
SCBLK
1268 1286 1892 1910
1250 1875
1248 1256 1874 1890
1250 1300 1298 1875 1872 1925 1924 1900
1248
BCP1
1248 1276 1872
BCP2
1243 1245 1312 1314 1870 1937 1939
VGATE HGATE
1248 1298 1872 1924 1242 Always Continuous 1314 1867
ABIN S1,S2,S3 SH1,GT3/SH2, GT1/SH3
1250 1276 1874 1900
NOTES: back pin. When high, VGATE output always low. field horizontal lines vertical counts. frame horizontal lines 1250 vertical counts. Period each count vertical counter
Figure Vertical Timing (First Fourth Fields)
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SN28837 1/2-INCH TIMER
2492 Field Field 2496
2488
Vertical Scale CSYNC
2496
CBLK
SCBLK
2498
2498
BCP1
2498
BCP2
2493 2495
2492
VGATE HGATE
2498
Always Continuous
PS,T S1,S2,S3 SH1, GT1/SH3, GT3/SH2
NOTES: back pin. When high, VGATE output always low. field horizontal lines vertical counts. frame horizontal lines 1250 vertical counts. Period each count vertical counter
Figure Vertical Timing (Second Third Fields)
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SN28837 1/2-INCH TIMER
(214)
Horizontal Scale
Continuous
HSYNC
CSYNC
CBLK
23.5
SCBLK
BCP1 BCP2
HGATE
S1,S2,S3
SH1,GT3/SH2, GT1/SH3
Note
horizontal scale clock), interval master clock periods. NOTES: Between horizontal scale, although appear coincident, leads leads line horizontal clocks
Figure Horizontal Timing
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SN28837 1/2-INCH TIMER
SOCS031B JULY 1991 Horizontal Scale CBLK
4.458333-MHz Pulse GT3/SH2 GT1/SH3
Output 0(1) (1):Not Use, (2):Half Dark, DA:Dark, DU:Dummy, A:Active Output SW-Y Output
(2)A
Dark
Dummy
Active
BCP1 BCP2
NOTE This chart shows early mode only. Late mode shown Figure
Figure Timing (Start
4-10
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SN28837 1/2-INCH TIMER
Early
37.4 Late
ns(S1/SH1)
GT3/SH2
GT1/SH3 NOTE SH1, GT3/SH2, GT1/SH3, are: Cycle time 224.3 Pulse width 74.8 Duty cycle
Figure Waveforms
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SN28837 1/2-INCH TIMER
CBLK
(214)
GT3/SH2 GT1/SH3 Output Outputs Held Until Next Pulse Output Outputs Held Until Next Pulse
SW-Y Output
ACTIVE NOTE This chart shows early mode only. Late mode shown Figure
Figure Timing (End
4-12
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SN28837 1/2-INCH TIMER
SOCS031B JULY 1991 Timing
Counter(T1) CBLK BCP1 BCP1 Mode 2-MHz Burst Mode 1-MHz Burst Mode Mode (0.9554 MHz) Always Free Running (1.9107 MHz)
ABIN
Timing INTGO ABCLR (mode mode ABIN (mode mode
ANTIBLOOMING MODE SELECTION MODE Don't care NOTES: mode mode duty cycle high low. Only timing from field even field shown. timing from even field field same that field even field minus H-to-V timing. input always high. ABS0 ABS1 ABS2 ABIN OUTPUT burst burst const const
Figure ABIN Timing
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SN28837 1/2-INCH TIMER
POWER-UP OPERATION Power (see Note Refresh Pulse (see Note
(see Note 1026 Pulses PS,T Pulses
S1,S2,S3
ABIN Note Refresh Pulses (see Note
NORMAL OPERATION
(see Note
1026 Pulses
Pulses
Pulses PS,T
S1,S2,S3
ABIN
NOTES: always back low. capacitor connected input (between ground). ABIN, when low. Refresh pulses (1026 pulses) generated even back pin.
Figure Operation Chart
4-14
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SN28837 1/2-INCH TIMER
Pulses (see Note PS,T Pulses (see Note
ABIN BCP1, BCP2 Clear Operation
Operation Mode
Normal Operation
NOTES: When goes low, pulses generated after goes high. When high, goes pulses generated steady-state level.
Figure Normal Timing Variable Integration
Counter Input (see Note Reset Window Counter(T1) CBLK Input (see Note NOTES: counter preset value when changes from high. Output signals changed clock after change counter through output latches.
Figure Operation
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SN28837 1/2-INCH TIMER
Counter Input Reset Window Counter
Input NOTE counter preset value when changes from high.
Figure Operation
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SN28837 1/2-INCH TIMER
MECHANICAL DATA
This plastic package consists circuit mounted lead frame encapsulated within electrically nonconductive plastic compound. compound will withstand soldering temperatures with deformation, circuit performance characteristics will remain stable when operated high-humidity conditions. package intended surface mounting, leads spaced 1,0-mm centers with 0,8-mm foot length. Leads require additional cleaning processing when used soldered assembly.
FS060 18,2 (0.717) 17,4 (0.685) 14,2 (0.559) 13,8 (0.543) Index Corner Chamfer Designation JEDEC PQFP-G44
used illustration save space)
(0.083) (0.075)
0,20 (0.008) 0,10 (0.004)
0,95 (0.037) 0,65 (0.026)
0,65 (0.026) 0,45 (0.018)
15,0 (0.591)
(0.055) 0,10 (0.004) (0.031) Seating Plane Detail
Detail LINEAR DIMENSIONS MILLIMETERS PARENTHETICALLY INCHES 7/94
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IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1995, Texas Instruments Incorporated
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