SLIT115 PowerFLEX Surface Mount Power Packaging SLIT115

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SLIT115 PowerFLEX Surface Mount Power Packaging SLIT115

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Printed U.S.A. 08-96
SLIT115
PowerFLEX
Surface Mount Power Packaging
SLIT115 September 1996
Printed Recycled Paper
IMPORTANT NOTICE Texas Instruments (TI) reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. warrants performance semiconductor products related software specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion products such applications understood fully risk customer. products such applications requires written approval appropriate officer. Questions concerning potential risk applications should directed through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used.
Copyright 1996, Texas Instruments Incorporated
INTRODUCTION
PowerFLEX
PowerFLEX
PowerFLEX Family
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PowerFLEX
INTRODUCTION
PowerFLEX
PowerFLEX
PowerFLEX Family
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PowerFLEXis package family that been designed offer customers surface-mountable power package. package designed cost compatible with much existing assembly equipment assembly factories. PowerFLEX package profile while retaining most power dissipation characteristics. PowerFLEX available 14-, 15-pin versions. Each version technical capabilities. PowerFLEX package will offered both surface-mount thru-hole lead configurations give customers same cost smaller area. Power semiconductor devices have historically been assembled packages with large form factors such TO-220. demands cost-effectiveness compactness several industries have compelled designers thin surface-mount packages power devices. address this trend, Texas Instruments recently developed type package PowerFLEX family that cost-effective, thermally enhanced, thin surface-mountable standard Surface Mount Technology (SMT) assembly line. PowerFLEX family comparable TO-220, DPAK, power Single-In-Line Package (SIP). consists 15-pin packages, accommodate sizes large 45.6K mils2. Thin, surface-mountable, thermally enhanced designs three distinguishing features boasted PowerFLEX family. body thickness PowerFLEX family less than maximum package length width (excluding lead length) largest package family (15-pin) only respectively. Moisture ingress protection, mechanical rigidity, locking mold compound lead frame achieved through special leadframe design. tab(s), which extension packages, used visual inspection site(s) surface-mount quality. exposed pads, similar that TO-220, enable majority heat dissipate directly into underlying printed circuit board heat sink. Silver flake filled epoxy used die-mount material PowerFLEX family cost stress considerations. Thermal performance enhanced utilizing effective printed circuit board (PCB) design, dominates thermal performance system. cost, profile, enhanced thermal design advantages PowerFLEX family make them package choice applications that space cost critical, while also requiring excellent power dissipation capability. These include hard disk drives, printers, office automation equipment, automotive engine body controllers, wireless communication units.
PowerFLEX trademark Texas Instruments Incorporated.
PowerFLEX
Introduction
TABLE CONTENTS
Reliability Tests Board-Mounted Temperature-Cycle Data Temperature Time Wafer Failures Temperature Time Bond Failures Reliability Test Conditions
Thermal Data General Rules Test Description Thermal Test Board Layout Calibration Curve Sensing Diode Test Setup Test Procedures Junction-To-Case Thermal Resistance, Junction-to-Case Thermal Resistance Void Percentage Power Junction-To-Ambient Thermal Resistance, References
Surface Mounting PowerFLEX Parts Design Assembly General Processing Safeguards References
Footprints Soldering PowerFLEX Footprints Packing Information Tube Specification Tape Reel Specification Package Outlines PowerFLEX Line-Up Package Codes Drawing Revisions Plastic Small-Outline Packages Plastic Flange-Mount Packages Plastic Single-In-Line Packages
PowerFLEX
LIST FIGURES
Figure Page HTSL Various Temperatures Thermal Equivalent Circuit Surface-Mounted Package Mounting Heatsink. Conceptual Example Total Thermal Impedance Individual Contributions Power Dissipation Corresponding Temperature Change Junction Thermal Test Board Layout Calibration Curve Sensing Diode Thermal Test Experimental Setup Thermal Impedance Measurement Transient Thermal Impedance Device 15-Pin PowerFLEX Package Transient Thermal Impedance Device 7-Pin PowerFLEX Package Transient Thermal Impedance Device 15-Pin PowerFLEX Package Thermal Resistance Function Power Area 15-Pin PowerFLEX Packages Thermal Impedance Device with Transistors Turned Various Duty Cycles Thermal Impednace Device with Transistor Turned Various Duty Cycles Junction-To-Case Thermal Resistance Percentage Voids 7-Pin PowerFLEX Package Junction-to-Case Thermal Resistance Power Dissipation 15-Pin Package Junction-to-Case Thermal Resistance Power Dissipation 7-Pin Package Junction-To-Ambient Thermal Resistances PowerFLEX Packages Under Still-Air Conditions Junction-to-Ambient Thermal Resistances PowerFLEX Packages Under Forced Conditions Transient Thermal Impedance Device 7-Pin PowerFLEX Package Mounted Printed Circuit Board Transient Thermal Impedance Device 15-Pin PowerFLEX Package Mounted Printed Circuit Board
PowerFLEX
LIST FIGURES continued
Figures Page Typical Profiles Used Reflow Soldering PowerFLEX Parts PowerFLEX Package Footprints Segmented 15-Lead Footprint 3-Lead Magazine (4072410) Magazine (4111776) 15-Lead Magazine (4072389) 7-Lead Magazine (4072390) 2-Lead Magazine (4072407) 14-Lead Magazine (4072409) Single-Sprocket Tape Dimensions Double-Sprocket Tape Dimensions Tape Format Reel Dimensions
LIST TABLES
Tables Page Temperature-Cycle Test Results Reliability Failure-Mechanism Acceleration Factors Reliability Test Conditions PowerFLEX Package Family Parameters Power DMOS Devices Typical Junction-To-Case Thermal Resistances PowerFLEX Packages Number Units Package Variable Tape Dimensions Variable Reel Dimensions
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PowerFLEX
RELIABILITY TEST
Board-Mounted Temperature-Cycle Data Temperature Time Wafer Failures Temperature Time Bond Failures Reliability Test Conditions
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BOARD-MOUNTED TEMPERATURE-CYCLE DATA Temperature cycle testing printed wiring board (PWB) assembly used evaluate capability assembly withstand mechanical stress resulting from differences thermal expansion coefficients between die, package, materials. testing also used soldered thermal connection between thermal copper trace FR4. degradation strength that connection evaluated performing Unit Pull Strength Test. assemblies were cycled between temperature extremes -55°C 125°C duration 1000 cycles.
Table Temperature-Cycle Test Results
TOTAL UNIT CYCLES FAILURES AVERAGE CHANGE UNIT PULL STRENGTH -1.5%
TEMPERATURE TIME WAFER FAILURES Major failure mechanisms device level reliability include gate oxide interlevel (and intralevel) oxide (ILO) integrity, electromigration metal lines, vias contacts, channel carriers, junction leakage, mobile ions. Dielectric breakdown major failure mechanism very large scale integration (VLSI) circuits become serious reliability issue device scaling. breakdown field oxide layer significantly lowered contamination defects existing oxide. Time-dependent dielectric breakdown (TDDB) methods used measure oxide integrity. TDDB test, devices stressed voltage until hard breakdown observed, time-to-failure (TF) recorded each device. Since oxide breakdown accelerated increasing electric field (voltage) across oxide, TDDB tests generally implemented different electric fields. stress fields normally chosen region Fowler-Nordheim tunneling such
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that linear approximation used predict oxide lifetime under operating conditions. acceleration exponent related following equation
t0exp(-yV/tox)
channel carrier effect becomes significant when feature size transistors shrinking into deep submicron region. higher electric field resulting from shorter channel length accelerates electrons (holes) very high energy states. Some these electrons (holes) lucky enough escape from channel region into either silicon oxide substrate. carriers generate phonon emission break bonds oxide/silicon interface oxide itself. Those injected into oxide also create traps oxide charges. channel carrier effect negative activation energy since electron (hole) mobility higher lower temperature. Electromigration phenomenon that occurs under influence temperature gradient excessive current density. mechanism atomic diffusion driven momentum exchange with conduction electrons. local divergence atom flux result excessive vacancy formation. These vacancies grow into voids, voids grow continuously until conductor fails. Electromigration occur metal lines, vias, contacts integrated circuit. Mobile ions which alkali ions result from Impurities chemicals contamination various device manufacturing processes. These alkali ions have high mobility drift oxide relatively applied voltages could make MOSFET threshold voltage unstable positive gate bias. junctions basic building blocks modern integrated circuits. properties junctions that generally examined forward reverse currents, reverse breakdown voltage, series resistance. these, reverse leakage currents were often used monitor quality junction.
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kinetics each failure mechanism described Arrhenius equation that bears following general form equation -(E/RT)
where rate constant, pre-exponential factor, activation energy which specific failure mechanism becomes active (eV), Avogadro constant (8.61x10-5 eV/K), absolute temperature (K). acceleration factor (AF) defined quotient failure rate stress condition (temperature, current, voltage, moisture, mechanical stress, etc.) over failure rate another stress condition. used convert failure rate obtained from stress condition failure rate another stress condition shown equation exp(E/R(1/T2 1/T1))
Methods employed measure failure rates these failure mechanisms varying stress condition (temperature voltage) while holding remaining stresses constant. Table lists parameters related each major failure mechanisms. acceleration exponent equation I0[exp(-qV/nkT)
where current, charge, applied voltage, Boltzmann constant absolute temperature respectively.
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Table Reliability Failure-Mechanism Acceleration Factors
FAILURE MECHANISM Gate Oxide TEMPERATURE Metal Line Vias Contacts Channel Carriers Mobile Ions Junctions Activation Energy Acceleration Factor Fitting Parameter -0.2 (20C-100C) 4890 0.18 4890 VOLTAGE PARM cm/MV cm/MV (2.5->3.5V) 50,700 50,700
Electromigration
TEMPERATURE TIME BOND FAILURE Major package level reliability includes various forms package crackings, chip crackings induced stress from packaging processes materials (mount materials molding compounds), delamination interfaces, ball/stitch bond liftoff, shift fracture, gold/aluminum (Au/Al) ball bond failure excessive Kirkendall voids which results insufficient high temperature storage lifetime (HTSL). HTSL metric measure effect molding compounds wire-bond reliability. brominated resin flame retardants synergistic brominated resin/antimony-oxide flame retardants were introducted into epoxy molding compounds mid-1970s. found that thermally-induced bromine release accelerates degradation Au/Al wire-bond strength through Kirkendall voiding mechanism gold-aluminum intermetallics. degradation intermetallic layers between gold wire aluminum-bond starts interface gold-rich intermetallic gold ball. Technology evolvement past decade been able slow down degradation introducing antimony oxide system using `ion getters' `freeze' free bromine ions molding compounds.
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Texas Instruments (TI) uses wire pull test method determine HTSL molding compound. this method, packages molded subject molding compound into ovens with capability controlling +/-2°C temperatures units packages pulled each read interval that varies from depending temperature. wire pull test performed decapped units. Testing that temperature discontinued when wire pull strength below predetermined failure value. acceleration factor activation energy each rate limiting process calculated using time-to-failure (TF) different temperatures through following relationships shown equations k1/k2 TF2/TF1 Rln(AF)/(1/T2 1/T1)
This data used predict HTSL different temperatures. Figure example HTSL experimental data commonly used molding compounds. From this data, HTSL different temperatures calculated results shown inset Figure
Grams 1000 1500 2000 Hours 2500 3000 3500 195°C 185°C 195°C Hours 185°C 1870 Hours (185°C 195°C) 3.495 2.31 Based 2.31 Projected 140°C Years 125°C 1454 Years 115°C 8258 Years 106°C Years
Figure HTSL Various Temperatures
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RELIABILITY TEST CONDITIONS
Table Reliability Test Conditions PowerFLEX Package Family
TEST TYPE Steady-State Life Biased Hast Autoclave Thermal Shock Solder Heat Solvent Resistance Solderability Lead Fatigue Lead Pull Lead Finish Adhesion Physical Dimensions Flammability Salt Atmosphere X-Ray Storage Life UL94V-0 695-2-2 View Only according CONDITIONS 155°C 130°C 121°C 150°C 260°C PSIG READ POINTS 1000 cycles
170°C Samples used these stresses were preconditioned Joint Electronic Device Committee (JEDEC) A113, Level
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THERMAL DATA
General Rules Test Description Thermal Test Board Layout Calibration Curve Sensing Diode Test Setup Test Procedures Junction-to-Case Thermal Resistance, Junction-to-Case Thermal Resistance Void Percentage Power Junction-to-Ambient Thermal Resistance, References
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GENERAL RULES Power dissipation from active elements integrated circuit device causes increase junction temperature which depends amount power dissipation thermal resistance between junction case ambient. relation among these thermal properties such thermal resistance, power dissipation, junction temperature analogous Ohm's Law. this analogy, temperature difference, power dissipation, thermal resistance correspond voltage drop, current, electrical resistance respectively. assumption implied this analogy that chip surface temperature case ambient temperature isothermal although reality this usually case. However, this analogy still holds true most applications. junction temperature, power dissipation, thermal resistance related equation
Pqjx
where thermal resistance between junction case ambient (°C/W); average temperatures junction case ambient respectively (°C), power dissipation (W). Junction-to-case thermal resistance, RJC, junction-to-ambient thermal resistance, RJA, common listed thermal resistances data books. very small when measurement directly under very high when measured places away from junction. Typically, ranges from less than °C/W °C/W depending measurement location, package type, active element size, size, die-attach material type quality, leadframe material thickness. major heat flow PowerFLEX-type package follows die-die mount-die path underlying heatsink since this path offers lowest thermal resistance. thermal resistance silver-filled polymer-based mount material major
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contributor junction-to-case thermal resistance this type package since this material poorest thermal conductivity compared other materials package. Assembly process control critical minimizing thermal resistance through optimum control thickness voiding attach layer. Figure thermal equivalent circuit steady state thermal behavior PowerFLEX type package mounted heatsink, where RJC, RCA, RCH, thermal resistances junction-to-case, case-to-ambient, case-to-heatsink, heatsink-to-ambient respectively. temperature junction, ambient, heatsink respectively.
Figure Thermal Equivalent Circuit Surface-Mounted Package Mounting Heatsink
junction-to-ambient thermal resistance (RJA) expressed
RqCHA
Case-to-ambient thermal resistance (RJA) generally very large compared other terms, hence equation simplified
RqJC RqCH RqHA
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(10)
also called contact thermal resistance whose value depends mounting pressure, thermal grease usage, interface roughness. about °C/W when thermal grease used proper mounting pressure applied. comparison junction-to-ambient thermal resistance (RJA) between packages like comparing oranges apples both packages have same heatsink configuration. resistance heat flow from junction ambient enhanced significantly when heatsink, such printed circuit board, effectively designed reduce heatsink-to-ambient thermal resistance (RHA). concept thermal resistance valid when peak junction temperature nearly equal average junction temperature, case high duty cycle long pulses. When applied pulses have duty cycle, peak junction temperature significantly higher than average junction temperature. Since device lifetime limiting factor peak junction temperature, thermal impedance ZJx, which analogus electrical impedance, should used instead thermal resistance, RJx.
(11)
where TJmax maximum junction temperature. singe pulse condition, junction-to-case thermal impedance PowerFLEX-type package directly mounted heatsink approximated series thermal impedances contributed from individual materials shown equation
(12)
where single pulse duration; steady state thermal resistance; thermal time constant individual component.
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Thermal time constant another electrical analogy. defined time thermal impedance material reach 63.2% steady-state thermal resistance. conceptual example shown Figure that curve thermal impedance versus pulse duration. This curve summation thermal impedance each material. cannot observe plateaus summation curve when dominant contributor that pulse duration period small time constant.
Total Thermal Impedance °C/W
Attach
Leadframe
Pulse Duration
Figure Conceptual Example Total Thermal Impedance Individual Contributions
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thermal impedance, ZJx, long train equal amplitude load pulses (Figure 4(a)) calculated from thermal impedance, ZJx(tp), single load pulse equation
Z(t) Z(tp)
(13)
where period load pulses, duty cycle equal tp/.
Time
Time
Figure Power Dissipation Corresponding Temperature Change Junction
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Test Description
Thermal Test Dies
Steady-state thermal measurements under forced airflow conditions were performed packages assembled using TI's thermal test dies. different sizes were used: 0.001 inch), while other mil, which reduction dimension from first one. sizes enables compare thermal performance packages with different active areas. Heat generated four banks resistors each test die; each bank electrical resistance 12.5 bipolar-type sensing diode that located center monitors junction temperature. power junction-to-ambient thermal resistance measurements using thermal test dies.
Power DMOS Devices
Four power DMOS devices were used this study reflect thermal performance actual power devices that assembled PowerFLEX packages. These devices power monolithic DMOS arrays that consist different numbers independent N-channel enhancement-mode DMOS transistors. Table lists parameters each device. calculations power area excluded bond area each transistor.
Table Parameters Power DMOS Devices
DEVICE TRANSISTORS POWER AREA TRANSISTOR MIL2) 6.50 1.93 2.15 7.87 TOTAL AREA MIL2) 31.3 21.3 25.0
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Thermal Test Board Layout types thermal test boards were used forced measurements. Both types boards have same layout shown Figure Each board made material with total thickness 0.062 inch dimension 8.25 8.25 with edge connectors opposite edges. first type 2-layer board with minimal copper traces electrically connected from each package edge connectors. 1-oz copper layers both sides test board with same dimension exposed were located each package position. Thermal vias were used thermal enhancement purposes their numbers depend sizes exposed pads. second type board same configuration first except that there additional 1-oz copper layers sandwiched laminates further enhance thermal performance. PowerFLEX packages tested were solder-mounted board simulate real printed circuit board environment.
Figure Thermal Test Board Layout
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Calibration Curve Sensing Diode Figure example calibration curve sensing diode thermal test die. sensing diode different temperatures were first measured slope versus temperature curve calculated. This slope used calculate junction temperature which another measured.
Base-To-Emitter Voltage
Slope 1.981 mV/°C
Temperature
Figure Calibration Curve Sensing Diode Thermal Test
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Test Setup
Cold Plate Method
cold plate method used measure junction-to-case thermal resistances referenced dynamic mode electrical test method described JEDEC JC15.1 Integrated Circuit Thermal Measurement Method Electrical Test
Method (Single Semiconductor Device)1. cold plate method measures
average thermal resistance from junction package surface that intimate contact with infinite heatsink.
Pressure Clamp Device Under Test (DUT) Wires Thermal Inpedance Tester
Copper Block
Figure Experimental Setup Thermal Impedance Measurement
Figure shows experimental setup cold plate method. this setup, device under test (DUT) pressure clamped
8-inch 8-inch 4-inch copper block that acted infinite heatsink. Silicone thermal grease applied between heatsink package. Tesec 9214-KT thermal impedance tester used these measurements. tester first measured drain-to-source voltage (VDS) active device (DMOS arrays) then switched heat forcing through predetermined amount power specific time period. tester then switched back measure active device again. measurement current ensure that small enough affect device characteristics. reflect actual junction temperature, delay time between switch-off heating power post-heating measurement only difference measurements, VDS, displayed tester used calculate device junction temperature that test condition.
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Test Procedures
Steady-State Thermal Measurements
Still-air Conditions
Still-air measurements were performed placing package-mounted test board 1-cubic foot chamber. board oriented with facing upward. ambient temperature measured approximately inches above test board with type thermocoupler.
Forced Airflow Conditions
Forced airflow measurements were made inside calibrated wind tunnel. overall wind tunnel dimensions were inches inches inches with test duct width inches. Measurements were performed ambient temperature. temperature velocity measurement positions were center duct about inches ahead test board avoid wake effect heating effect from test board package. board package orientation vertical located center region duct. package oriented with lateral axis transversing airflow. velocity monitored with hot-wire anemometer probe. velocities used these measurements were ft/min, ft/min ft/min. Temperatures were monitored with type (iron/constantan) thermocoupler.
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Junction-To-Case Thermal Resistance, Figure shows transient thermal response device 15-pin PowerFLEX package when mounted infinite heatsink. thermal resistance decreases upon increasing number transistors turned that effectively increases heat dissipation area. This figure also shows that thermal resistance PowerFLEX packages under 2°C/W capable being used high power dissipation applications.
Junction-to-Case Thermal Impedance °C/W
Transistors Transistors Transistor
0.001
0.01
Pulse Duration
Figure Transient Thermal Impedance Device 15-Pin PowerFLEX Package
Each curve corresponds different number transistors turned power Figure transient thermal responses device 7-pin 15-pin PowerFLEX package respectively. When applications short pulse duty cycle region, maximum power dissipation calculated according equation example, thermal impedance duty cycle 1-ms pulse train 0.6°C/W according Figure when device 7-pin PowerFLEX package used. maximum peak power dissipation when maximum junction temperature 150°C ambient temperature 105°C.
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P=5W Junction-to-Ambient Thermal Impedance °C/W
0.0001
0.001
0.01
Pulse Duration
Figure Transient Thermal Impedance Device 7-Pin PowerFLEX Package
P=5W Junction-to-Ambient Thermal Impedance °C/W
0.0001
0.001
0.01
Pulse Duration
Figure Transient Thermal Impedance Device 15-Pin PowerFLEX Package
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Figure junction-to-case thermal resistance (RJC) function power area 15-pin PowerFLEX packages. This figure summarizes data measured from devices 15-pin PowerFLEX package. indicated this figure, these thermal resistance data points fall same curve described same equation. This provide predict thermal resistance size when other assembly parameters held constant.
Junction-to-Case Thermal Resistance °C/W P=5W 5.12x-0.40
Active Area Square Mils)
Figure Thermal Resistance Function Power Area 15-Pin PowerFLEX Packages
Table lists thermal resistance each PowerFLEX package specific sizes. Power used cases
Table Typical Junction-To-Case Thermal Resistances PowerFLEX Packages
COUNT Size (mil2) (°C/W) Preliminary data 3/5/7 9/15
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When PowerFLEX package intimate contact with infinite heatsink, major heat dissipation path follows silicon-die attach-leadframe-heatsink path since offers lowest overall thermal resistance. junction-to-case thermal resistance (RJC) can, therefore, approximated summation resistances contributed from each individual component,
(14)
where thickness, heat dissipation area thermal conductivity each material respectively. above approximation true when package body small that heat dissipation natural convection through package surfaces negligible. this approximation, package size significant impact observed from Table that 3-/5-/7- 9-/15-pin packages approximately same when same device used. This approximation break down when heatsink changes from infinite type finite type such printed circuit board since other thermal paths contribute significant portion heat dissipation.
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Figure thermal impedances device with transistors turned various duty cycles. power applied both cases. curves various duty cycles were calculated based equation
Single Pulse Calculated Thermal Impedance °C/W Junction-to-Case 0.01 0.02 0.05 Direct current 0.001
0.01
Pulse Duration
Figure Thermal Impedance Device with Transistors Turned Various Duty Cycles
Measured Calculated Junction-to-Case Thermal Impedance °C/W 0.02 0.05 Direct current 0.0001
0.01 Pulse Duration
Figure Thermal Impedance Device with Transistor Turned Various Duty Cycles
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Junction-To-Case Thermal Resistance Void Percentage PowerFLEX packages silver-flake-filled polymer mount material. quality attach layer have impact junction-to-case thermal resistance (RJC) packages when properly controlled. Figure shows that voids degradation thermal performance PowerFLEX packages becomes significant when void percentage above percent.
Junction-to-Case Thermal Resistance °C/W
Void Percentage
Figure Junction-To-Case Thermal Resistance Percentage Voids 7-Pin PowerFLEX Package
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Power Figure junction-to-case thermal resistance versus power dissipation 15-pin 7-pin PowerFLEX packages respectively. thermal resistance observed first decrease rapidly with power, followed relatively constant zone, then increase again when very high powers were applied. initial high thermal resistance possibly related spot effect junction very low-input current. With increase input current, thermal resistance decreased rapidly reached constant value wide range power dissipation. increase junction-to-case thermal resistance very high power regimes related decrease junction-to-case thermal conductivities both silicon chip leadframe materials high temperatures.
15-Pin Powerflex Package, Voltage Each Device Transistor Turned Junction-to-Case Thermal Resistance °C/W Device
Device
Device
Power
Figure Junction-to-Case Thermal Resistance Power Dissipation 15-Pin Package
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Junction-to-Case Thermal Resistance °C/W Power Device Device 7-Pin Powerflex Package, Voltage Each Device Transistor Turned
Figure Junction-to-Case Thermal Resistance Power Dissipation 7-Pin Package
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Junction-to-Ambient Thermal Resistance, Figure junction-to-ambient thermal resistance, RJA, measured under still conditions. very strong function package size test board design. When heatsink changes from infinite finite type, direct heat dissipation through exposed leadframe becomes critically dependent heatsink efficiency. When heatsink effective dissipating heat, package size becomes important convection ambient what through package surfaces play more role heat dissipation. This clearly observed Figure packages mounted 2-layer board, thermal resistances smaller packages were much higher than those larger packages since 2-layer board effective 4-layer board heat dissipation. difference that significant packages mounted 4-layer board.
Junction-to-Ambient Thermal Resistance °C/W
2-Layer
4-Layer
2-Layer
Figure Junction-To-Ambient Thermal Resistances PowerFLEX Packages Under Still-Air Conditions
Also, Figure 18(a) PowerFLEX packages under forced airflow conditions. Although forced reduce each count, change much effective thermal test board design did. When airflow changed from still-air conditions ft/min airflow, each count reduced
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2-Pin 3-/5-/7-Pin 9-/15-Pin 14-Pin
4-Layer
30-40% 2-layer board that while reduced 4-layer board. This also reflects that heat transfer through package surfaces more important 2-layer board than 4-layer board. There little cooling available packages mounted printed circuit boards that inside portable electronic equipment. effectively remove heat dissipated devices, printed circuit board design become successful thermal management equipment design.
Junction-to-Ambient Thermal Resistance °C/W 9/15 3/5/7 Velocity (ft/min)
Packages mounted 2-layer board
Junction-to-Ambient Thermal Resistance °C/W 3/5/7 9/15 Velocity (ft/min)
Packages mounted 4-layer board Figure Junction-to-Ambient Thermal Resistances PowerFLEX Packages Under Forced Conditions
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Figure transient thermal responses device 7-pin 15-pin PowerFLEX package mounted 3-inch 4.5-inch board with 2-oz copper layer top. Equation used calculate maximum power applications requiring duty cycle short pulse train.
Junction-to-Ambient
Thermal Resistance °C/W
Power
0.0001 0.001
0.01
1000
Figure Transient Thermal Impedance Device 7-Pin PowerFLEX Package Mounted Printed Circuit Board
Junction-to-Ambient
Thermal Resistance °C/W
Power
0.0001 0.001
0.01
1000
Pulse Duration
Figure Transient Thermal Impedance Device 15-Pin PowerFLEX Package Mounted Printed Circuit Board
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REFERENCES JEDEC JC15.1 Integrated Circuit Thermal Measurement Method-Electrical Test Method (Single Semiconductor Device). B.W. Williams, Power Electronics Devices, Drivers, Applications Passive Components, Edition., McGraw-Hill, Inc., 1995.
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SURFACE MOUNTING PowerFLEX PARTS
Design Assembly General Processing Safeguards References
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DESIGN Over past decade, surface mount turned from into science with development general design rules practices. Some these more formal, such IPC-SM-782, Surface-Mount Land Pattern Design, while others found books (see References articles (see Reference in-house specifications (see Reference objective this article quickly review these rules note PowerFLEX packaging impacts them. interplay placement requirements, space thermal constraints, solderability, testability, reparability cleanability, finally reliability been given title Design Manufacturability (DFM). Such important parts cost targets, time-to-market requirements, type board III) backdrop part this discussion. surface mount land patterns, sometimes called footprints pads, some general observations about board layout will discussed. well designed board that follows basic surface mount technology (SMT) considerations greatly improves cost, cycle time, quality product. Boards designed with automation mind built automated equipment, which wastes money, cycle time, quality. board envelope dimensions type automated being used, usually includes both minimum maximum dimension. Many board shapes accommodated, front board should have straight square edge help machine sensors detect shaped boards small boards require panelization special assembly tooling process in-line. most desirable least costly shape rectangular with cutouts. Normally maximum module height taken inches total height. Fiducials, optical alignment targets that align module automated equipment, important subject that received little written attention. These targets should allow vision-assisted equipment accommodate shrink stretch board during processing. They also define coordinate
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system automated equipment such printing pick-and-place equipment. following general guidelines have been found most useful:
Automated equipment requires minimum fiducials, although three preferred. helpful when fuducials configuration orthogonal optimize stretch/shrink algorithms. When possible, lower left fiducial should design origin (coordinate 0,0). components should within inches fiducial guarantee placement accuracy. large boards panels, fourth fiducial should added. wide range fiducial sizes shapes used. recommended shape circle 0.064 inches diameter with annulus 0.126 ID/0.146 outer ring optional, other feature within 0.031 inch fiducial.
parallel board edges must have clear zone 0.125 inch where component lands fiducials placed. This area used conveyor transfer eliminates need tooling. cleared zone should along longest edges board, width should based machine handling capability. Panelization breakaway tabs used part this cleared zone. Panelization, mentioned above, needs defined addressed. process where material left attached board tabs with intention removing later after assembly. There reasons this. first build multiples board same time. This reduces touch labor associated with loading handling individual boards. also reduces amount machine time, machine does stop between boards loading. second reason panelization small odd-shaped boards. extra material takes place expensive tool fits board acceptable machine envelope. little single board panel with this approach. Even that level, save significant operator touch time tooling cost. Panelization should considered whenever either above conditions exists. Since PWBs already fabricated panels, panelization should extra effort board manufacturer.
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Since PowerFLEX parts fine pitch, many spacing considerations fine pitch layouts beyond scope this article. However, since interpackage spacing aspects DFM, question close safely components each other critical one. following list component layout considerations recommendations based experience:
minimum 0.02 inch should exist between lands adjacent components reduce risk shorting. recommended minimum space between surface mount device (SMD) component bodies equal height tallest component. This allows 45-degree soldering angle case manual work needed. Polarization symbols need provided discrete SMDs (diodes, tantalum capacitors, etc.) next positive pin. indicators features needed determine keying components. Space between lands (under components) backside discrete components should minimum 0.03 inch. open vias this space. Direction backside discretes wave solder should perpendicular direction through wave. Fine pitch components must allow step-down zone least inch outside lands. leadless chip carriers placed this zone. This allows proper step-down regions stencil manufacturing. stencil opening must have aspect ratio opening stencil thickness 1:1.5 (meaning maximum thickness stencil thirds opening size). recommended standard stencil sizes mils thick components discretes mils thick 31.5 pitch. components bottom side that exceed grams square inch surface area (contact area with board). Space permitting, symbolize reference designators within land pattern respective components. preferred have components oriented well ordered columns rows. Group similar components together whenever possible. Room testing needs allowed.
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actual design land areas addressed section thermal management. There sets designs included this report, standard footprints thermally enhanced footprints. Either footprints used, depending preference user. final step design together data package automated build. data package will vary slightly from application application, minimum will include:
Bill Materials Reference Designator List Component location data (X-Y data) Placement plot assembly drawing Bare board specifications Gerber/Artwork Aperture List
PowerFLEX
ASSEMBLY There probably more literature solders, solder pastes, printing them than other aspect surface mount technology. authors recommend Jennie Hwang's book (see Reference excellent source information this subject. PowerFLEX parts present unusual challenges either solder paste application placement. Parts shipped either tube tape-and-reel formats ease automated pick-and-place machines. Fluxes move toward no-clean systems another subject that created great deal literature without clear direction. PowerFLEX parts have been successfully mounted using mild (RA) fluxes without reliability problems. problems anticipated with current no-clean systems. Solder reflow conditions next critical step surface mount process. During reflow, solvent solder paste evaporates, flux cleans metal surfaces, solder particles melt, wetting metal surfaces takes place wicking molten solder, finally solidification solder into strong metallurgical bond completes process. desired result uniform layer solder strongly bonded both package with voids smooth, even fillet around package. Conversely, when steps carefully together, voids, gaps, uneven thickness, insufficient fillet occur. While exact cycle used depends type reflow system used, there several points successful cycles have common. first these warm-up period sufficient safely evaporate solvent. This done with pre-heat bake, hold cycle evaporation temperatures, even both, depending paste used. there less solvent paste (such high viscosity, high metal-content paste), then hold shorter. However, when hold long enough solvent out, fast allow evaporate, many negative things happen. These range from solder ball formation heating fast heating entrapped solder
PowerFLEX
leading embrittlement leaving enough time complete evaporation. significant number reliability problems with solder joints solved with warm step, needs careful attention. second thing successful cycles have common uniform heating across package board. Solder will wick hottest spot, uneven solder joint thickness indicator that profile needs adjusting. This more problem with some reflow methods, such infrared (IR) reflow, than with others such forced hot-air convection heating. type reflow method used will also affect third thing successful cycles have common, which balance between low, late, short temperature leading insufficient flux activation high, long temperature leading excessive flux activation oxidation. Heating solder fast before melts also paste, leading poor wetting. PowerFLEX parts have been successfully mounted using cycles shown below Figure Vapor phase reflow forced hot-air convection heating were used perform reflow operations. Visual inspections fillets showed good fillet formation.
Temperature TIME Forced Connection
Vapor Phase
Figure Typical Profiles Used Reflow Soldering PowerFLEX Parts
this point, brief discussion fillets needed. PowerFLEX leads plated with palladium (Pd) eliminate need solder dipping plating. This means that visual appearance joint will differ slightly from tin/lead
PowerFLEX
(Sn/Pb)-dipped lead. Since only solder available joint formation screened-down type, solder will probably cover joint. Also, joints tend somewhat duller appearance. Texas Instruments performed extensive testing showing joints strong stronger than Sn/Pb joints(6).
Thermal Management
Effective thermal management culmination many factors. Many these factors have been discussed elsewhere this monograph. Thermal management with PowerFLEX packages depends moving primary thermal management from package system. This, turn, requires that thermal connections between various parts system(i.e., thermal pad, thermal PWB, heatsink) efficient possible. This discussion considers ways make thermal package land area highly efficient.
primary enemy efficient transmittal heat from thermal package land area solder voiding. Therefore, need consider ways reduce eliminate voids solder. first these methods already been discussed. Proper reflow cycles first line defense against voiding. second package board cleanliness.
third method primary focus this discussion, footprint pattern PWB. Figure (see section Footprints Soldering) shows convention footprint pattern typical PowerFLEX package, this case lead package. Extensive experience shown that very difficult make solder joints with this type footprint that free trapped other void forming defects. solution recommended Texas Instruments shown Figure Figure land areas broken channels that allow gases escape. When width channels held about 0.02 inch, experience further shown that solder wets across channel
PowerFLEX
surface thermal form nearly continuous layer. This gives upside down fillet tunnel along channels that provides very efficient thermal path. When extra reliability desired, posts solder mask printed hold package surface. This effect increasing solder thickness height post imposes solder uniformity across entire joint.
PowerFLEX
GENERAL PROCESSING SAFEGUARDS During solder reflow process, packages assemblies subjected heat that, some cases, above rated temperature device. Therefore, precaution should taken carefully control both duration peak temperature that these devices receive. packages should always preheated, temperature differential between preheat peak temperature should never exceed 100°C. better practice keep this differential between 50°C 75°C. maximum soldering temperature should never exceed 260°C more than seconds. Care should exercised cool down well heat Forced cooling generate unacceptable thermal mechanical stresses solder joint, leading reduced joint lifetime early failure. very useful rule thumb allow least minutes unforced cooling. Rapid, jarring movement assembly during reflow process also cause package dislocation, stress buildup, other undesirable effects. heat across assembly should kept even possible, both solder thickness reasons discussed above keep built-in stress possible. more than 10°C should allowed, even especially) with heating. Wave soldering recommended PowerFLEX package attachment. Attaining level void-free attachment needed between thermal needed almost impossible with wave soldering techniques.
PowerFLEX
REFERENCES
Surface Mount Technology, ISHM Technical Monograph, Silver Spring, 1984
Prasad, Surface Mount Technology: Principles Practice, Nostrand Reinhold
Surface Mount Easy Steps, Magazine, Publishing Group, series monthly installments 1994
Curtis Clark, Design Guidelines Assembly, private communication Jennie Hwang, Solder Paste Electronics Packaging, Norstrand Reinhold, York, 1992 Douglas Romm, Palladium Lead Finish User's Manual, Texas Instruments, Dallas,
PowerFLEX
PowerFLEX
FOOTPRINTS SOLDERING
PowerFLEX Footprints
PowerFLEX
PowerFLEX FOOTPRINTS
0.4550 (11,56) 0.3875 (9,84) 0.3400 (8,64) 0.3930 (9,98) 0.3480 (8,84)
0.1190 (3,02) 0.0540 (1,37) 0.0000 (8,00) 0.0000 (0,00) 0.3840 (9,75) 0.3120 (7,92) 0.3740 (9,50) 0.3130 (7,95) 0.2060 (5,23) 0.1680 (4,27) 0.1060 (2,69) 0.0610 (1,55) 0.2400 (6,10) 0.1730 (4,39) 0.0720 (1,83) 0.0000 (0,00)
0.1290 (3,28) 0.0540 (1,37) 0.0000 (8,00)
0.3430 (8,71)
0.0310 (0,79)
0.3500 (8,89)
0.2110 (5,36)
0.0340 (0,86)
3-LEAD
5-LEAD
NOTE linear dimensions inches (mm).
0.3880 (9,86) 0.3390 (8,61)
0.4550 (11,56) 0.3930 (9,98) 0.3480 (8,84)
0.1705 (4,33) 0.0540 (1,37) 0.0000 (8,00) 0.2420 (6,15) 0.1900 (4,83) 0.0520 (1,32) 0.4390 (11,15) 0.4000 (10,16) 0.1990 (5,05) 0.1270 (3,23) 0.1290 (3,28) 0.0540 (1,37) 0.0000 (8,00) 0.5110 (12,98) 0.0000 (0,00) 0.3000 (7,62)
0.0380 (0,97)
0.0120 (0,30)
0.4770 (12,12)
2-LEAD
7-LEAD
NOTE linear dimensions inches (mm).
Figure PowerFLEX Package Footprints
PowerFLEX
0.1610 (4,09)
0.0000 (0,00)
PowerFLEX FOOTPRINTS
0.4645 (11,80) 0.4125 (10,48) 0.3295 (8,37) 0.3560 (9,04) 0.1455 (3,70) 0.0555 (1,41) 0.0015 (8,04) 0.7740 (19,66) 0.6370 (16,18) 0.4430 (11,25) 0.3680 (9,35) 0.2840 (7,21) 0.4900 (12,45) 0.0000 (0,00) 0.1180 (3,00) 0.0540 (1,37) 0.0000 (0,00) 0.3020 (7,67) 0.2380 (6,05)
0.1060 (2,96)
0.4480 (11,38)
0.2430 (6,17) 0.1930 (4,90)
0.0930 (2,36)
9-LEAD
0.1370 (3,48)
0.0680 (1,73)
14-LEAD
0.5180 (13,16) 0.4680 (11,89) 0.3860 (9,80)
0.2010 (5,11) 0.0870 (2,21) 0.0541 (1,37) 0.0270 (0,69) 0.0000 (0,00)
0.8000 (20,32)
0.6500 (16,51)
0.5600 (14,22)
0.4190 (10,64)
0.2400 (6,10)
0.3810 (9,68)
0.1500 (3,81)
15-LEAD
NOTE linear dimensions inches (mm).
Figure PowerFLEX Package Footprints (Continued)
0.0000 (0,00)
0.0550 (1,40) 0.0000 (0,00)
PowerFLEX
PowerFLEX FOOTPRINTS
15-LEAD
Figure Segmented Lead Footprint
PowerFLEX
PACKING INFORMATION
Tube Specification Tape Reel Specifications
PowerFLEX
TUBE SPECIFICATION
Delivery Method
PowerFLEX devices shipped either packing methods:
Integrated circuit (IC) tubes Embossed tape Reel
devices delivered either system. embossed tape reel method generally preferred automatic pick-and-place feed machines. tape made from antistatic/conductive material. cover tape, which peels back during use, thermally sealed carrier tape keep devices securely their cavities during shipping handling. tube magazine method shipping more versatile used with many different feeder applications.
tube method
Figures through show tube dimension diagrams.
PowerFLEX
0.579 (14,70)
0.120 (3,05) 0.090 (2,29) 0.050 (1,27) 0.488 (12,39) Places
0.343 (8,71) 20.00 (508,00)
0.768 (19,52)
0.343 (8,71)
0.022 (0,56) 0.065 (1,65)
0.121 (3,12) 0.119 (3,02)
Thru Places
NOTE linear dimensions inches (mm).
Figure 3-Lead Magazine (4072410)
PowerFLEX
0.520 (13,21)
0.205 (5,21)
0.400 (10,16) Places
0.100 (2,54)
0.250 (6,35) 0.800 (20,32) 20.40 (518,16)
0.370 (9,40)
0.025 (0,64) 0.025 (0,64) 0.050 (1,27)
0.121 (3,12) 0.119 (3,02)
Thru Places
NOTE linear dimensions inches (mm).
Figure Magazine (4111776)
PowerFLEX
0.413 (10,49) 0.125 (3,18) 0.095 (2,41) 0.050 (1,27) Sharp Corner Places 0.400 (10,16) Places
0.355 (9,02)
0.340 (8,64) 20.400 (518,16)
0.600 (15,24)
0.165 (4,19)
0.025 (0,64) 0.065 (1,65) 0.123 (3,12) 0.119 (3,02)
Thru Places
NOTE linear dimensions inches (mm).
Figure 15-Lead Magazine (4072389)
PowerFLEX
0.413 (10,49) 0.125 (3,18) 0.095 (2,41) 0.050 (1,27) Sharp Corner Places 0.400 (10,16) Places
0.355 (9,02)
0.340 (8,64) 20.400 (518,16)
0.600 (15,24)
0.165 (4,19)
0.025 (0,64) 0.065 (1,65) 0.123 (3,12) 0.119 (3,02)
Thru Places
NOTE linear dimensions inches (mm).
Figure 7-Lead Magazine (4072390)
0.291 (7,40) 0.125 (3,18) 0.095 (2,41) 0.050 (1,27) Sharp Corner Places 0.400 (10,16) Places
0.267 (6,78) 0.481 (12,22)
0.258 (6,55)
19.275 (489,58)
0.131 (3,33)
0.025 (0,64) 0.065 (1,65) 0.123 (3,12) 0.119 (3,02) Thru Places
NOTE linear dimensions inches (mm).
Figure 2-Lead Magazine (4072407)
PowerFLEX
0.219 (5,56) 0.105 (2,67) 0.075 (1,90) 0.050 (1,27) Sharp Corner Places 0.400 (10,16) Places
0.268 (6,80) 0.394 (9,99)
0.258 (6,55)
20.300 (515,62)
0.068 (1,73) 0.063 (1,60) 0.022 (0,56)
0.123 (3,12) 0.119 (3,02)
Thru Places
NOTE linear dimensions inches (mm).
Figure 14-Lead Magazine (4072409)
Number Units Package
Table shows many units tube each package type count.
Table Number Units Package
Pins/Pkg. 9/KTA 15/KTC 3/KTE 5/KTG 7/KTN 2/KTP 14/DBX Tube 4072389 4072389 4072390 4072390 4072390 4072407 4072409 Number Units
Packaging Method
tubes packed JIT-PAC standard size boxes maximum shipping efficiency recyclability.
PowerFLEX
1.75
0.10 2.00 0.05
Diameter
0.40
Cover Tape Carrier Tape Embossment Diameter Direction Feed
NOTES:
Tape widths Camber Standard 481-A. Minimum bending radius Standard 481-A. linear dimensions millimeters.
Figure Single-Sprocket Tape Dimensions
1.75
0.10 2.00 0.05
+0.1 -0.0 Diameter
0.40
Cover Tape Carrier Tape Embossment Diameter +0.1 -0.0 Diameter Direction Feed 0.10
NOTES:
Tape widths Camber Standard 481-A. Minimum bending radius Standard 481-A. linear dimensions millimeters.
Figure Double-Sprocket Tape Dimensions
PowerFLEX
TAPE REEL SPECIFICATION Embossed Tape Reel
Overall Tape Specifications
tape reel packaging used with PowerFLEX devices full compliance with Standard 481-A, Taping Surface Mount Components Automatic
Placement. static-inhibiting materials used carrier tape manufacturing
provides device protection from static damage, while rigid, dust-free polystyrene reels provide mechanical protection clean room compatibility with dereeling equipment currently available most high-speed automated placement systems.
Tape Format
Variables used Figure Table definitions variables follows: tape width, pocket pitch, pocket width, pocket length, pocket depth, maximum tape depth, width between pocket holes, distance between drive hole centerline pocket. dimensions given millimeters.
Trailer Components) Components Leader Components)
Required Component Count
NOTES:
Carrier tape conductive with resistivity value less than square. Cover tape sealed over entire length carrier tape. linear dimensions millimeters.
Figure Tape Format
PowerFLEX
Table Variable Tape Dimensions
DIMENSIONS (mm) PACKAGE TYPE WIDTH POCKET PITCH POCKET WIDTH (Ao) 9.95 10.95 11.65 8.95 13.15 POCKET LENGTH (Bo) 6.05 9.35 19.55 11.25 19.55 POCKET DEPTH (Ko) 2.60 2.60 2.60 2.25 2.60 MAXIMUM TAPE DEPTH 2.30 2.30 2.30 1.95 2.30
2/5/7KT 9KTA 14DBX 15KTC TOLERANCES
7.50 11.50 14.20 11.50 14.20 28.40 28.40
Reel Dimensions
Variables used Figure Table definitions variables follows: distance between flanges, maximum reel width, diameter reel hub.
13.0 20.2
Bar-Code Label Width
NOTE linear dimensions millimeters.
Figure Reel Dimensions Table Variable Reel Dimensions
DIMENSIONS (mm) PACKAGE TYPE TAPE WIDTH REEL DIAMETER REEL DIAMETER PARTS REEL 2500 1000 1000 REEL TOTAL THICKNESS
3-Pin 3-/5-/7-Pin 9-Pin 14-Pin 15-Pin
PowerFLEX
Device Insertion
Devices inserted toward outer periphery tape placing side with device name face side with heatsink exposed face down.
Packaging Method
Once taping been completed, leader should fixed reel with tape. product name, number, quantity, date code recorded reel cardboard used tape delivery. Each reel separately packed cardboard tape delivery.
PowerFLEX
PowerFLEX
PACKAGE OUTLINES
PowerFLEX Line-up Package Codes Drawing Revisions Plastic Small Outline Packages
(R-PDSO-G14) (R-PDSO-G20)
Plastic Flange Mount Packages
(R-PSFM-G9) (R-PSFM-G15) (R-PSFM-T3) (R-PSFM-G5) (R-PSFM-G7) (R-PSFM-T3)
Plastic Single-In-Line Packages
(R-PSSO-F3) (R-PDSO-G20)
PowerFLEX
PowerFLEX LINE-UP
PINS PITCH PACKAGE TYPE 0.180/0.090 0.100 0.067 0.050 0.075 0.050 R-PDSO-G14 0.050
Surface Mount
R-PSFM-G2 Surface Mount
R-PSFM-G3 R-PSFM-G5
R-PSFM-G7
R-PSFM-G9
R-PSFM-G15
.282 .238 .075
.355 .370 .075
.355 .370 .075
.355 .370 .075
.380 .770 .075
.380 .770 .075
R-PSFM-T3 Straight Leads
R-PSFM-T3
R-PSFM-T5
R-PSFM-T7
R-PSFM-T9
JEDEC Code Code WxLxT
.282 .238 .075
.355 .370 .075
.355 .370 .075
.355 .370 .075
.380 .770 .075
R-PSFM-T5 Formed Leads
R-PSFM-T7 K
R-PSFM-T15
.355 .370 .075
.355 .370 .075
.380 .770 .075
Samples Available Planning
PowerFLEX
PACKAGE CODES DRAWING REVISIONS Surface Mount
Flat Form Packaging Tool Data Book 72361P-4 7-2361-6 7-2362-4 KTA9PK 4073383 Tube each 4072389 .075 150x150 SIZE PITCH
Flat Form Packaging Tool Data Book 72360P-4 7-2360-6 7-2363-4 KTC15PK 4073385 Tube each 4072389 .050 250x200 SIZE PITCH
Flat Form Packaging Tool Data Book 7-2384P 7-2384-6 7-2379-4 KTE3PK 4073375 Tube each 4072390 .100 190x190 SIZE PITCH
Flat Form Packaging Tool Data Book 7-2385P 7-2385-5 7-2381-4 KTG5PK 4073387 Tube each 4072390 .067 190x190 SIZE PITCH
PowerFLEX
Flat Form Packaging Tool Data Book 7-2369P 7-2369-8 7-2378-4 KTN7PK 4073387 Tube each 4072390 SIZE PITCH
Flat Form Packaging Tool Data Book 4073388 Tube each 4072407 7-2392P-2 7-2392-2 7-2395-5 SIZE PITCH
Flat Form Packaging Tool Data Book 7-2368-6-S1 7-2368-6-S2 7-2366-5 DBX14PK1 4072404 Tube each 4072409 SIZE PITCH
Flat Form Packaging Tool Data Book 72361P-4 7-2361-6 7-2364 KTB9PK 4073384 Tube each 411776 SIZE PITCH
PowerFLEX
Flat Form Packaging Tool Data Book 72360P-4 7-2360-6 7-2365 KTD15PK 4073386 Tube each 411776 SIZE PITCH
Flat Form Packaging Tool Data Book 7-2384P 7-2384-6 7-2380-3 KTF3PK 4073376 Tube each 4072410 SIZE PITCH
Flat Form Packaging Tool Data Book 7-2385P 7-2385-5 7-2382-3 KTH5PK 4073378 Tube each 4072410 SIZE PITCH
Flat Form Packaging Tool Data Book 7-2385P 7-2385-5 7-2383-3 KTJ5PK 4073379 Tube each SIZE PITCH
PowerFLEX
Flat Form Packaging Tool Data Book 7-2369P 7-2369-8 7-2373-3 KTL7PK 4073381 Tube each 4072410 SIZE PITCH
KFlat Form Packaging Tool Data Book 7-2369P 7-2369-8 7-2374-3 KTM7PK 4073382 Tube each SIZE PITCH
Flat Form Packaging Tool Data Book 4073389 Tube each 4072408 7-2392P 7-2392 7-2396-1 SIZE PITCH
PowerFLEX
(R-PDSO-G14)
PLASTIC SMALL-OUTLINE PACKAGES
0.050 (1,27)
0.018 (0,46) 0.014 (0,35)
0.010 (0,25)
Thermal (see Note
0.345 (8,76) 0.325 (8,26) 0.110 (2,79)
0.254 (6,45) 0.248 (6,30)
0.431 (10,94) 0.421 (10,69)
0.010 (0,25) 0.010 (0,25) Gage Plane 0.005 (0,13) 0.001 (0,03)
0.035 (0,89) 0.025 (0,64)
0.068 (1,73) Seating Plane 0.004 (0,10) 4072404/B 01/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. package thermal performance enhanced bonding thermal external thermal plane. solderable electrically thermally connected backside die.
PowerFLEX
(R-PDSO-G20)
0.020 (0,51) 0.014 (0,35)
PLASTIC SMALL-OUTLINE PACKAGES
0.050 (1,27)
0.010 (0,25)
Thermal 0.150 (3,81) (see Note
0.170 (4,31)
0.299 (7,59) 0.293 (7,45) 0.430 (10,92) 0.411 (10,44) 0.010 (0,25)
0.510 (12,95) 0.500 (12,70)
Gage Plane 0.010 (0,25) +2°- 0.050 (1,27) 0.016 (0,40)
Seating Plane 0.004 (0,10) 0.000 (0,00) 0.004 (0,10) 4073226/B 01/96
0.096 (2,43)
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. thermal performance enhanced bonding thermal external thermal plane. This solderable electrically thermally connected backside leads
PowerFLEX
(R-PDSO-G20)
0,30 0,19
PLASTIC SMALL-OUTLINE PACKAGES
0,65
0,13 Thermal (3,18 (see Note
2,41 NOM)
0,15 4,50 4,30 6,70 6,10 Gage Plane
0,25 6,80 6,40 0,75 0,50
Seating Plane 1,20 0,10 0,00 0,10
4073225/B 01/96
NOTES:
linear dimensions millimeters. This drawing subject change without notice. package thermal performance enhanced bonding thermal external thermal plane. This solderable electrically thermally connected backside leads
PowerFLEX
(R-PSFM-G9)
PLASTIC FLANGE-MOUNT PACKAGES
0.080 (2,03) 0.070 (1,78) 0.766 (19,45) 0.756 (19,20) 0.188 (4,78) 0.050 (1,27) 0.040 (1,02) 0.010 (0,25)
0.290 (7,37)
0.385 (9,78) 0.375 (9,52) 0.345 (8,76) 0.335 (8,51)
Thermal (see Note
0.450 (11,43) 0.430 (10,92)
0.075 (1,91) 0.600 (15,24)
0.031 (0,79) 0.025 (0,64) 0.010 (0,25)
Seating Plane 0.004 (0,10)
0.005 (0,13) 0.001 (0,03) 0.772 (19,60)
0.045 (1,14) 0.035 (0,89) Gage Plane 0.010 (0,25) 4073383/C 02/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. heatsink area approximately mils. Dimensions include mold protrusions, exceed 0.006 (0.15).
PowerFLEX
(R-PSFM-G15)
PLASTIC FLANGE-MOUNT PACKAGES
0.080 (2,03) 0.070 (1,78) 0.766 (19,45) 0.756 (19,20) 0.050 (1,27) 0.345 (8,76) 0.335 (8,51) 0.040 (1,02) 0.010 (0,25)
0.290 (7,37)
0.302 (7,67)
0.385 (9,78) 0.510 (12,95) 0.492 (12,45) 0.375 (9,52) 0.450 (11,43) 0.430 (10,92)
Thermal (see Note
Seating Plane 0.050 (1,27) 0.700 (17,78) 0.031 (0,79) 0.025 (0,63) 0.010 (0,25) 0.005 (0,13) 0.001 (0,03) 0.772 (19,60) 0.004 (0,10)
0.045 (1,14) 0.035 (0,89)
Gage Plane 0.010 (0,25)
4073385/B 01/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. heatsink area approximately mils.
PowerFLEX
(R-PSFM-T3)
PLASTIC FLANGE-MOUNT PACKAGES
0.080 (2,03) 0.070 (1,78) 0.366 (9,31) 0.356 (9,05) 0.220 (5,59) 0.050 (1,27) 0.040 (1,02) 0.010 (0,25)
0.295 (7,49) 0.420 (10,67) 0.410 (10,41)
0.360 (9,14) 0.350 (8,89) 0.320 (8,13) 0.310 (7,87)
Thermal (see Note
0.025 (0,63) 0.031 (0,79) Seating Plane 0.004 (0,10) 0.005 (0,13) 0.001 (0,03)
0.100 (2,54) 0.200 (5,08)
0.010 (0,25)
0.010 (0,25) Gage Plane
0.041 (1,04) 0.031 (0,79)
0.010 (0,25) 4073375/B 01/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. center lead electrical contact with thermal tab.
PowerFLEX
(R-PSFM-G5)
PLASTIC FLANGE-MOUNT PACKAGES
0.080 (2,03) 0.070 (1,78) 0.366 (9,31) 0.356 (9,05) 0.220 (5,59) 0.050 (1,27) 0.040 (1,02) 0.010 (0,25)
0.295 (7,49) 0.420 (10,67) 0.410 (10,41)
0.360 (9,14) 0.350 (8,89) 0.320 (8,13) 0.310 (7,87)
Thermal (see Note
0.067 (1,72) 0.268 (6,81)
0.031 (0,79) 0.025 (0,63) 0.010 (0,25) Seating Plane 0.004 (0,10) 0.005 (0,13) 0.001 (0,03)
0.010(0,25) Gage Plane
0.041 (1,04) 0.031 (0,79)
0.010(0,25) 4073377/B 01/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. center lead electrical contact with thermal tab.
PowerFLEX
(R-PSFM-G7)
PLASTIC FLANGE-MOUNT PACKAGES
0.080 (2,03) 0.070 (1,78) 0.366 (9,31) 0.356 (9,05) 0.220 (5,59) 0.050 (1.27) 0.040 (1.02) 0.010 (0,25)
0.295 (7,49) 0.420 (10,67) 0.410 (10,41) 0.320 (8,13) 0.310 (7,87)
0.360 (9,14) 0.350 (8,89)
Thermal (see Note
0.031 (0,79) 0.025 (0,63) 0.300 (7,62) 0.010 (0,25) 0.005 (0,13) 0.001 (0,03) Seating Plane 0.004 (0,10)
0.050 (1,27)
0.010 (0,25) Gage Plane
0.041 (1,04) 0.031 (0,79)
0.010 (0,25) 4073387/A 01/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. center lead electrical contact with thermal tab.
PowerFLEX
(R-PSFM-T3)
PLASTIC FLANGE-MOUNT PACKAGES
0.243 (6,17) 0.233 (5,91) 0.230 (5,84) 0.220 (5,58) 0.125 (3,17) Heatsink 0.115 (2,92)
0.080 (2,03) 0.070 (1,70) 0.050 (1,27) 0.040 (1,02) 0.013 (0,33) 0.007 (0,17)
0.200 (5,08) 0.247 (6,27) 0.237 (6,02) 0.381 (9,68) 0.371 (9,42)
0.287 (7,29) 0.277 (7,03)
(See Note
0.030 (0,76) 0.090 (2,29) 0.031(0,79) 0.025(0,63) 0.180 (4,57) 0.010 (0,25) 0.005(0,13) 0.001(0,02) Seating Plane 0.004 (0,10)
0.002 (0,05) Offset 0.047 (1,19) Gage Plane 0.037 (0,94)
0.010 (0,25)
4073388/B 01/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. heatsink area approximately mils.
PowerFLEX
(R-PSSO-F3)
PLASTIC SINGLE-IN-LINE PACKAGES
4,60 4,40 0,40 1,80
1,60 1,40
2,60 2,40
4,25
0,80
0,48 0,53 1,50
0,44
4040234 03/95
NOTES:
linear dimensions millimeters. This drawing subject change without notice. center lead electrical contact with tab.
PowerFLEX
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Copyright 1996, Texas Instruments Incorporated

SLIT115 PowerFLEX Surface Mount Power Packaging SLIT115

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