DC96U4- 04/21/97 NOTICE This presentation single chapte

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Section
DC96U4-
04/21/97
NOTICE
This presentation single chapter from 1996 Mixed Signal Products Seminar. This presentation includes notes which read notes page view.
Texas Instruments
Seminar
DC96U4-
04/21/97
TLC2543 Single Supply,
Functional Block Diagram
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10
14-CHANNEL ANALOG INPUT CONTROL LOGIC INPUT ADDRESS REGISTER
ANALOG INPUTS
CLOCK
SAMPLE HOLD
12-BIT
OUTPUT DATA REGISTER
PARALLEL SERIAL CONVERTER
SERIAL DATA
SELF-TEST REFERENCE
VREF
VREF
Texas Instruments
Seminar
Figure TLV2543 Supply, Functional Block Diagram
TLV/TLC2543
functional block diagram TLV/TLC2543 shown Figure 2-6. includes analog multiplexer which allows inputs selected serial data bus. This offers on-board sample-hold, on-chip system clock programmable power-down mode well numerous other programmable features. This single-supply operates very power typical, max) while delivering 12-bits resolution KSPS throughput rate. software-programmable power-down mode enables device only consume maximum typical) current. This allows reduction power when conversion needed without requiring cost extra device. built-in 14-channel provides inputs single-ended analog input signals plus three internal test modes. onboard conversion clock further simplifies system design. This high level functionality system integration assures lowest possible total system cost 12-bit data acquisition system. generic serial interface provides easy interface virtually types processors equipped with 4-wire serial interface. available both (TLV2543) (TLC2543) versions.
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WIRE INTERFACE
DATA INPUT
TLV/TLC2543 Single Supply, Successive Approximation
Features
Single (TLV2543) (TLC2543) supply 12-bit resolution 66-kSPS sampling rate analog input channels Integrated sample/hold supply current (typ), (max) Power down current (typ), (max) On-Chip System Clock compatible serial interface Serially programmable operation modes
Differentiators
Analog Inputs Software Programmable Operational Modes Compatible Versions Operating Current Application Report Available
Texas Instruments
Seminar
Figure TLV/TLC2543 Single Supply, 12-Bit
TLV/TLC2543
TLV/TLC2543 also maximizes design/manufacturing flexibility offering same pinout pin-compatible versions (TLC542, TLV/TLC1543 TLV/TLV2543 respectively). This compatibility used easily upgrade existing 10-bit design using TLV/TLC1543 with 12-bit TLV/TLC2543. after completing system integration, determined acceptable, more cost effective version (TLC1543) used production. Manufacturers will able build family products with different price points comparable each feature based single platform offer upgradability higher performance later Battery powered process monitoring testing implemented with this low-power low-cost high-performance achieve longer battery life. Next generation cellular phone manufacturers that require higher quality digitizer interfaces benefit from small SSOP package lots input channels available temperature, battery voltage, panel brightness management other system variables. Other applications include pixel conversion color printers, offset adjust instrumentation, datalogging many many others. TLV/TLC2543 available 20-pin DIP, SSOP packages.
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Driving Inherent Sample Hold Capacitor Switched Capacitor ADCs
Driving source needs charge within during sampling time Time available charge within ln(2 resolution) 10-bit converter, 12-bit converter
ANALOG INPUT SOURCE Input Equivalent Circuit
(Max)
(Max)
Time constant (TC)
Texas Instruments
Seminar
Figure Driving Input Switched Capacitor Filter
Switched Capacitor ADCs
Switched capacitor ADCs offer inherent sample-hold function their input. This avoids need provide external sample-hold care should taken ensure that sufficient time allowed during sampling phase conversion process allow input sample-hold capacitor charge required level accuracy. minimum time required charging particular level accuracy calculated shown Figure 2-9. sample period needs extended due, example, increased source impedance, this achieved slowing down clock ADC. Unfortunately this will also have effect increasing data transfer time. small sample hold capacitor allows relatively high source impedance used. instance with TLC2543, clock cycles required sampling. clock this gives available charging time charge will require time constants ADC. Therefore: charging time where charging time period charging time R1). Solving this (charging time/ maximum source impedance. This foil highlights that inherent sample hold Switched-Capacitor ADCs quite easy use. control source impedance well enough drive capacitor.
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"Interfacing ADCs DSPs µProcessors"
Serial Interface
TMS320 Serial Port
Data Latched Edge Synchronous Data Transfer (Fsync) Requires Requires Consecutive Clocks Data Register
3-Wire "SPI
Data Latched Edge (SPI Default) Requires Various Data Register Size Stopped While Loading Data
Parallel Interface
ADCs Memory Mapped Will Require External Address Decoder from Processor from Processor Need Wait States Eliminate Data Conflicts Must Have Tri-State Data Outputs
Texas Instruments
Seminar
Figure 2-10 Interfacing ADCs DSPs µProcessors Data Converters interfaced variety processor data ports. parallel interface, differences between DSPs minimal. interfaces will require memory mapped scheme with address decoding usually connection /RD, /EOC pins between processor ADC. There variety serial ports available today with TMS320Cxxx Serial Peripheral Interface (SPI) being major serial ports. table 2-10 tries highlight some general differences between serial ports. There specific processors from various vendors that have some differences. TMS320 family, above table shows baseline serial ports. Newer DSPs have enhanced serial ports that have different data register size. Synchronous Serial Port Buffered Serial Port 8/10/12/16 Enhanced Serial Port support
ADCs DACs with Frame Sync input (slave mode DSP) have ability synchronize with command from DSP. This equivalent handshaking signal.
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Glueless Interface Microprocessors
TLV2543 MC68B11 Interface
pressure temperature pressure temperature
REF+
TLV2543
CLOCK DATA INPUT DATA REFGND
MC68B11E9
SCK/PD4 MOSI/PD3 MISO/PD2 SS/PD5
Texas Instruments
Seminar
Figure 2-11 Glueless Interface Microprocessor
Microcontroller Interface
TLV2543 easily interfaced supply microcontrollers (such MC68B11) which include serial peripheral interface (SPI) port. interface connections MC68B11 shown figure 2-11.
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TLV2543 TMS320C3x Interface
TMS320LC31 Serial Port
TMS320LC31 TCLK1 CLOCK CLKX CLKR
TLV2543
AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 AIN8 AIN9 AIN10
Analog Inputs
DATA INPUT DATA
Texas Instruments
Seminar
Figure 2-12 Glueless Interface
Interface: TLV2543 TMS320LC31
TLV2543 easily interfaced TMS320C3x family DSPs. This interface implemented using circuit shown Figure 2-12. Notice that (End Convert) signal TLV2543 connected external flag input TMS320C3x signifies when valid data ready read into data receive (DR) `C3x.
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Memory Mapped DSP/Microprocessor
TLC1550 10-bit TMS320C50
TLC1550
74ALS138
TMS320C50
INT1
Analog Input
D0-D9
Texas Instruments
Seminar
Figure 2-13 TLC1550 10-bit TMS320C50 Parallel Interface Higher speed interfacing between achieved using converter with parallel data output structure. example such device TLC1550 10-bit successive approximation ADC. typical interface TLC1550 TMS320C50 shown Figure 2-13.
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Decision Tree
General Purpose Converters
MSPS
Supply
6-Bit 8-Bit TL5501 TLC5510 TLC5733 TLC5540
kSPS
MSPS
kSPS
Supply
10Bit 12-Bit TLV1549 TLV2543 TLV1543 12-Bit 18-Bit
Supply
8-Bit TLV5510*
Single Supply
8-Bit 10-Bit TLC0820A TLC1550 8-Bit
Single Supply
10-Bit
TLC54X TLC154X TLC2543 TLC320AD57 TLC083X TLC320AD58
Product Preview
Texas Instruments
Seminar
Figure 2-14 Decision Tree above decision tree condensed version showing types ADCs offered internal architecture that used. Note that TI's ADCs shown this table; please consult 1995 Data Acquisition Circuits Data Book complete listing products.
Flash
TL5501
Semi-Flash
TLC0820A TLC5510 TLC5733 TLC5540 TLV5510*
Sigma-Delta
TLC320AD57 TLC320AD58
TLC083X TLC1550 TLV1549 TLV2543 TLV1543 TLC54X TLC154X TLC2543
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2-10
bit, 20MSPS Semi-Flash
TLC5510
Features
Integral Nonlinearity 0.75 (max) Differential Linearity Error (max) Maximum Conversion Rate MSPS (min) Signal Noise Ratio Analog Input Bandwidth Internal Reference Resistors Single-Supply Operation Power Consumption (typ) Characterized Operating Temperature: TLC5510I -20° Sony CXD1175 compatible
Differentiators
Latch-up free Analog input down Available Internal Sample Hold
Applications
Digital Video Signal Processing Video Teleconferencing demodulation Imaging Systems
Texas Instruments
Seminar
Figure 2-15 TLC5510 Bit, MSPS TLC5510INSLE 8-bit, MSPS provides combination high speed, power price. implementing CMOS, multi-stage, semi-flash architecture TLC5510 provides significantly lower power consumption cost than traditional flash architectures, while maintaining conversion rates MSPS accuracy LSB. This part designed easily interfaced DSP. parallel data outputs capable high-impedance mode. internal resistor network provided generate reference from supply only conversion clock must supplied. TLC5510 consumes power, requires only supply, internal provided surface mount package. TLC5510INSLE characterized operation from -20°C 75°C.
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2-11
TLC5510/TLC5540 Block Diagram
Resistor Reference Divider
REFB REFT REFBS AGND AGND VDDA REFTS ANALOG
nom.
nom.
Lower Sampling Comparators Bit) Lower Sampling Comparators Bit)
Lower Encoder Bit)
Lower Data Latch
D1(LSB)
nom.
Lower Encoder Bit) Upper Data Latch D8(MSB)
Upper Sampling Comparators Bit)
Clock Generator
Upper Encoder Bit)
Texas Instruments
Seminar
Figure 2-16 TLC5510/TCL5540 Block Diagram Figure 2-16 shows block diagram both TLC5510 TLC5540 semi-flash ADCs Note that upper sampling comparators bits) requires only block lower sampling comparator bits) requires blocks. upper block converts MSBs which require fast settling time. lower bits "ping-pong" between blocks with each block converting every other sample. This done meet settling time requirement MSPS ADCs. TLC5510 also latch free. TI's strength CMOS processing produced CMOS that tolerant power supply variation. many CMOS ADCs, difference between VDDA VDDD becomes large, internal diode will forward bias causing effective short ground latching ADC. These competitive ADCs place more stringent requirement quality (and lack noise spikes) both supplies. TLC5510 allows VDDA VDDD delta non-issue system design considerations, within given specifications data sheet.
DC96U4-
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2-12
TLC5510 Interface
TLC5510
TMS320C5x
ALS138
X2/CLKIN
Texas Instruments
Seminar
Figure 2-17 TLC5510 Flash Interfaces TLC5510 8-bit flash directly interfaced TMS320C5x shown figure 2-17. With repeated block move instruction (BLDD), possible read sample from TLC5510 store into internal memory instruction cycle, thus achieving MSPS data transfer with clocked MHz. analog input sampled falling edge CLK. converted digital data appears outputs D[1:8] clocks later. This delay know clock latency. Once past initial clock latency, digital output data output rising edge each clock. TMS320C5x 16-bit fixed-point family DSPs utilizing advanced Harvard architecture with separate strobes program (/PS), data (/DS) space (/IS), each them with address range. TLC5510 connected lower bits `C5x data bus; signal connected with read signal (/RD) active when external memory accessed. corresponding strobe signal stays during consecutive reads. When strobe (/IS) active, TLC5510 accessed through memory mapped space. interconnect line length should short possible. line matching series resistor signal used reduce overshoot ringing.
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2-13
TLC5510 used Camera Application
VDDA
TLC5510
640x480
Correlated Double Sample
2.3V
Latch
Area
Analog Input
REFT Semi Flash REFB Clock Generation
Signal Processing ASIC
Texas Instruments
Seminar
Figure 2-18 TLC5510 used Camera Application Figure 2-18 highlights some advantages semi-flash architecture TLC5510. applications using charge coupled device (CCD) sensor, common correlated double sampler (CDS) process signal. will sample both reference voltage active video then output difference two. This typically (minimum intensity) (maximum intensity). Since TLC5510 allows analog inputs output directly connected input ADC. Several competitive ADCs require analog input This type then requires user level shifting stage which increases system cost complexity. TLC5510 also provides internal reference resistors that Vref+ 2.3V Vref- AGND created using external components.
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bit, MSPS Semi-Flash
TLC5540
Features
Maximum Conversion Rate MSPS (min) Signal Noise Ratio Input) Analog Input Bandwidth (typ) Internal Sample Hold Internal Reference Resistors Integral Linearity (max) Differential Linearity 0.75 (max) Power Consumption (typ) Single-Supply Operation
Differentiators
Wide Bandwidth Undersampling Latch Free Analog Input Down Available Compatible With 5510
Applications
Digital Video Teleconferencing Demodulation Cellular Base Station Video Signal Processing
Texas Instruments
Seminar
Figure 2-19 TLC5540 Semi-Flash Bit, MSPS TLC5540 semi-flash architecture with same block diagram shown Figure 2-16. This part direct replacement TLC5510 allowing designers flexibility changing sampling rate without changing pwb's system timing. This part also follows industry standard pinout. single-supply CMOS consumes only power MSPS. also fully characterized specifications such SNR, SFDR effective bits.
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2-15
TLC5540 Dynamic Performance
Effective Number Bits Input Frequency
-0.5
Analog Input Bandwidth
ENOB Effective Number Bits
Gain
MSPS
MSPS
-1.5
-2.5
ANALOG -3.5 Wave Sine
-4.5
Frequency (MHz)
Frequency (MHz)
Nyquist Based Sampling
Undersampling Applications
Texas Instruments
Seminar
Figure 2-20 TLC5540 Dynamic Performance
TLC5540 Dynamic Performance
TLC5540 combines high speed with power consumption cost deliver price/performance point high speed (video grade) applications. traditional Nyquist-based applications, TLC5540 delivers effective bits MSPS. undersampling applications, wide analog input bandwidth eliminates costly analog down converter components.
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TLC5540 Linearity Performance
Differential Nonlinearity Integral Nonlinearity -0.2 -0.4 -0.6 -0.8 -0.2 -0.4 -0.6 -0.8 Digital Output Code Digital Output Code
Texas Instruments
Seminar
Figure 2-21 TLC5540 Linearity Performance
TLC5540 Linearity Performance
Figure 2-21 shows typical Differential Non-linearity (DNL) Integral Non-linearity (INL) TLC5540. error with MSPS indicates very distortion step width ADC.
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TLC5733 3-Channel, MSPS
Functional Block Diagram
CLPV CLPV
OUTPUT DATA LATCH
AD1-8
CLAMP CIRCUIT
MULTIPLEXER OUTPUT FORMAT
OUTPUT DATA LATCH
BD1-8
CLAMP CIRCUIT
CLPV EXTCLP CLPEN NTSC/PAL
OUTPUT DATA LATCH
CD1-8
CLAMP CIRCUIT
CONTROL INT/EXT CLAMP CIRCUIT
CLOCK GENERATOR
OUTPUT FORMAT SELECTOR TEST
MODE0 MODE1 TEST
INIT
Texas Instruments
Seminar
Figure 2-22
TLC5733 3-Channel, MSPS Functional Block Diagram
functional block diagram TLC5733 3-channel, 8-bit, MSPS, Semi-Flash shown Figure 2-22. TLC5733 contains feed-back type high-precision clamp circuit each channel video (YUV) applications clamp pulse generator that detects COMPOSITE SYNC pulses automatically. clamp pulse also supplied externally. resistors connected between terminals RBA, RBB, each nominally They allow full scale input signal range each (sections trimmed nominal value volts video signals. This done connecting external resistor between positive analog supply (AVCC) another between ground section Similar resistor connections used establish voltage sections
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2-18
Features
TLC5733 Triple, Semi-Flash, 8-bit, MSPS
8-bit resolution channels Accepts inputs Programmable Y:U:V formats 4:4:4, 4:2:2 4:1:1 Maximum conversion rate MSPS (min) Analog input bandwidth Integral linearity 0.75 (max) Differential linearity (max) Automatic clamp insertion (YUV mode) accuracy Digital Feedback Clamp Programmable formats
Differentiations
Seminar
Texas Instruments
Figure 2-23 TLC5733 Triple, Semi-Flash, 8-bit, MSPS advantages modified semi-flash converter method further emphasized TLC5733 which includes three such ADCs single Each converter operates MSPS. three channel device programmed accept either analog video signals. mode TLC5733 produces output data 4:4:4, 4:2:2 4:1:1 format. applications, output available 4:4:4 format. mode TLC5733 offers automatic clamp pulse generating facility. This detects whether composite sync pulse occurred correct time interval automatically inserts clamp pulse correct time. digital clamp optimized NTSC component TLC5733 designed low-power single-supply operation characterized over temperature range.
Applications
Digital Television Camcorders Digital Video recording
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2-19
TLC5733 Clamp Timing
COMPOSITE SYNC Noise Gate Noise Gate Internal Clamp Pulse NTSC/PAL Counter Reset
TIME INTERVAL NTSC CLOCKS TIME (µs) 60.6 4.05 0.42 3.77 3.58 CLOCKS 1075 4.43
Missing COMPOSITE SYNC therefore Noise Gate generated
NTSC/PAL Counter Count
TIME (µs) 60.7 3.27 0.34 5.25 4.74
(color subcarier)
Texas Instruments
Seminar
Figure 2-24 TLC5733 Clamp Timing previously mentioned, TLC5733 deliver output data 4:4:4, 4:2:2 4:1:1 form. Figure 2-24 shows timing diagram automatic clamp insertion using composite sync signal. TLC5733 contains clamp insertion facility which detects presence position time composite sync pulse. composite sync pulse detected incorrectly positioned time, clamp pulse automatically inserted correct time. This facility programmed NTSC timing placing high level voltage respectively NT/PAL pin.
DC96U4-
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2-20
TLC0820A 8-bit, Semi-Flash
Functional Block Diagram
Analog Input
4-BIT FLASH MSBs)
OUTPUT LATCH 3-STATE BUFFERS
4-BIT
DIGITAL OUTPUTS D0-D7
4-BIT FLASH LSBs)
Ref+ Ref-
Texas Instruments
Seminar
Figure 2-25 TLC0820A 8-bit, Semi-Flash TLC0820 Advanced LinCMOSSemi-Flash 8-bit analog-to-digital converter consisting 4-bit flash converters, 4-bit digital-to-analog converter, summing (error) amplifier, control logic result latch circuit. on-chip track-and-hold circuit 100ns sample window allows these devices convert continuous analog signals having slew rates mV/µs without external sampling components. TTL-compatible 3state output drivers modes operation allow interfacing variety processors.
Features
8-Bit Resolution Differential Reference Inputs Parallel Microprocessor Interface (max) Conversion Access Time External Clock Oscillator Components Required On-Chip Track-and-Hold Single Supply Direct Replacement National Semiconductor ADC0820C/CC Analog Devices AD7820K/B/T
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