NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM NM27C020 high sp
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
NM27C020 high speed Megabit CMOS UV-EPROM manufactured Fairchild's advanced sub-micron technology. Utilizing architecture, this advanced CMOS process delivers high speeds while consuming power. NM27C020 provides microprocessor-based systems extensive storage capacity large portions operating systems application software. 100ns access time provides no-wait-state operation with high-performance CPUs. NM27C020 offers single chip solution code storage requirements 100% firmware-based equipment. Frequentlyused software routines quickly executed from EPROM storage, greatly enhancing system utility. NM27C020 manufactured using Fairchild's advanced CMOS EPROM technology, member high density Fairchild EPROM series family which range densities 4Mb.
Features
High performance CMOS access time Simplified upgrade path -VPP "Don't Care" during normal read operation Manufacturers identification code JEDEC Standard Configuration 32-pin CERDIP package 32-pin PLCC package 32-pin PDIP package
Block Diagram
Output Enable, Chip Enable, Program Logic
Data Outputs
Output Buffers
Decoder
2,097,152-Bit Cell Matrix
Address Inputs
Decoder
DS010835-1
1999 Fairchild Semiconductor Corporation NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Connection Diagrams
27C080 27C040 27C010 27C512 27C256 27C256 27C512 27C010 27C040 27C080
Note:
XX/VPP XX/VPP
XX/VPP
XX/PGM XX/PGM OE/VPP CE/PGM CE/PGM CE/PGM
OE/VPP CE/PGM
DS010835-10
Compatible EPROM configurations shown blocks adjacent NM27C020 pins.
Commercial Temperature Range (0°C +70°C) ±10%
Parameter/Order Number
NM27C020 NM27C020
versions guaranteed function slower speeds.
Names
-A17 Addresses Chip Enable Output Enable Outputs Program Don't Care (During Read)
Access Time (ns)
Extended Temperature Range (-40°C +85°C) ±10%
Parameter/Order Number
NM27C020
Access Time (ns)
PLCC Configuration
View
DS010835-3
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Connection Diagrams (Continued)
Ordering Information
Fairchild Memory EPROM CMOS
Access Time Operating Temp Blank Commercial Temp. Extended Temp. Packaging Ceramic PLCC PDIP Memory Size Mbit
DS010835-9
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Absolute Maximum Ratings (Note
Storage Temperature Input Voltage Except with Respect Ground (Note VPPand with Respect Ground Supply Voltage with Respect Ground Protection -65°C +125°C
Output Voltages with Respect Ground (Note
-0.6V
Operating Range
-0.6V -0.6V +14V -0.6V >2000V
Range
Commercial Industrial
Temperature
+70°C -40°C +85°C
Tolerance
±10%
Read Characteristics Over Operating Range with
Symbol
ISB1(Note ISB2 (Note
Parameter
Input Level Input High Level Output Voltage Output High Voltage Standby Current (CMOS) Standby Current (TTL) Active Current
Test Conditions
-0.5
-0.4
Units
-400 0.3V Inputs VOUT 5.5V Commercial Industrial
Supply Current Read Voltage Input Load Current Output Leakage Current
Read Characteristics Over Operating Range with
Symbol
tACC (Note
Parameter
Address Output Delay Output Delay Output Delay Output Disable Output Float Output Hold from Addresses, Whichever Occurred First
Units
Note Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods time affect device reliability. Note supply current IPP. maximum current value with Outputs unloaded. Note This parameter only sampled 100% tested. Output Float defined point where data longer driven-see timing diagram. Note CMOS inputs: 10.3V, 10.3V.
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Read Characteristics (Continued)
Frequency
DS010835-7
Frequency (MHz) Temperature
DS010835-8
Temperature (IC)
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Capacitance +25°C, (Note
Symbol
COUT
Parameter
Input Capacitance Output Capacitance
Conditions
VOUT
Units
Test Conditions
Output Load Gate (Note 0.45V 2.4V Input Rise Fall Times Input Pulse Levels
Timing Measurement Reference Level (Note Inputs 0.8V Outputs 0.8V
Waveforms (Notes
ADDRESS
0.8V
Address Valid
0.8V
(Note
0.8V
(Note
(Note
Valid Output
OUTPUT
0.8V
Hi-Z
(Note
Hi-Z
DS010835-4
Note This parameter only sampled 100% tested. Note delayed tACC after falling edge without impacting tACC. Note compare level determined follows: High TRI-STATE®, measured VOH1 (DC) 0.10V; TRI-STATE, measured VOL1 (DC) 0.10V. Note TRI-STATE attained using Note power switching characteristics EPROMs require careful device decoupling. recommended that least ceramic capacitor used every device between GND. Note outputs must restricted 1.0V avoid latch-up device damage. Note Gate: -400 includes fixture capacitance. Note connected except during programming. Note Inputs outputs undershoot -2.0V Max.
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Programming Characteristics (Notes
Symbol
tOES tCES tVPS tVCS tOUT
Parameter
Address Setup Time Setup Time Setup Time Data Setup Time Setup Time Setup Time Address Hold Time Data Hold Time Output Enable Output Float Delay Program Pulse Width Data Valid from Supply Current during Programming Pulse Supply Current Temperature Ambient Power Supply Voltage Programming Supply Voltage Input Rise, Fall Time Input Voltage Input High Voltage Input Timing Reference Voltage Output Timing Reference Voltage
Condition
Units
6.25 12.5
12.75
6.75 13.0
0.45
Note Fairchild's standard product warranty applies only devices programmed specifications described herein. Note must applied simultaneously before removed simultaneously after VPP. EPROM must inserted into removed from board with voltage applied VCC. Note maximum absolute allowable voltage which applied during programming 14V. Care must taken when switching supply prevent overshoot from exceeding this maximum specification. least capacitor required across VPP, suppress spurious voltage transients which damage device. Note During power must brought high either coincident with before power applied
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Programming Waveforms (Note
Program ADDRESS
0.8V
Program Verify
Address
DATA
0.8V
Data Stable
Hi-Z
Data Valid
6.25V
12.75V
0.8V
0.8V
0.8V
DS010835-5
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Turbo Programming Algorithm Flow Chart
6.5V 12.75V ADDRESS FIRST LOCATION
PROGRAM 50µs PULSE INCREMENT
DEVICE FAILED
FAIL
VERIFY BYTE
PASS
LAST ADDRESS
INCREMENT ADDRESS
ADDRESS FIRST LOCATION
VERIFY BYTE INCREMENT ADDRESS
PASS
FAIL
PROGRAM PULSE
LAST ADDRESS
CHECK BYTES 1ST: 6.0V 2ND: 4.3V
Note: standard National Semiconductor Algorithm also used will have longer programming time. DS010835-6
FIGURE
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Functional Description
DEVICE OPERATION
modes operation device listed Table should noted that inputs modes levels. power supplies required VPP. power supply must 12.75V during three programming modes, must other three modes. power supply must 6.5V during three programming modes, other three modes.
most efficiently these control lines, recommended that decoded used primary device selecting function, while made common connection devices array connected READ line from system control bus. This assures that selected memory devices their power standby modes that output pins active only when data desired from particular memory device.
Programming
CAUTION: Exceeding (VPP) will damage device. Initially, after each erasure, bits device "1's" state. Data introduced selectively programming "0's" into desired locations. Although only "0's" will programmed, both "1's" "0's" presented data word. only change ultraviolet light erasure. part programming mode when power supply 12.75V VIH. required that least capacitor placed across VPP, ground suppress spurious voltage transients which damage device. data programmed applied bits parallel data output pins. levels required address data inputs TTL. When address data stable, active low, program pulse applied input. program pulse must applied each address location programmed. EPROM programmed with Turbo Programming Algorithm shown Figure Each Address programmed with series pulses until verifies good, maximum pulses. Most memory cells will program with single pulse. (The standard National Semiconductor Algorithm also used will have longer programming time.) EPROM must programmed with signal applied input. Programming multiple EPROM parallel with same data easily accomplished simplicity programming requirements. Like inputs parallel EPROM connected together when they programmed with same data. level pulse applied input programs paralleled EPROM.
Read Mode
part control functions, both which must logically active order obtain data outputs. Chip Enable (CE) power control should used device selection. Output Enable (OE) output control should used gate data output pins, independent device selection. Assuming that addresses stable, address access time (tACC) equal delay from output (tCE). Data available outputs after falling edge assuming that been addresses have been stable least tACC -tOE.
Standby Mode
EPROM standby mode which reduces active power dissipation over 99%, from 0.55 EPROM placed standby mode applying CMOS high signal input. When standby mode, outputs high impedance state, independent input.
Output OR-Tying
Because part usually used larger memory arrays, Fairchild provided 2-line control function that accommodates this multiple memory connections. 2-line control function allows for: lowest possible memory power dissipation, complete assurance that output contention will occur.
MODE SELECTION
modes operation NM27C020 listed Table single power supply required read mode. inputs levels except device signature.
TABLE Modes Selection Pins Mode
Read Output Disable Standby Programming Program Verify Program Inhibit
Note VIH.
(Note
12.75V 12.75V 12.75V
5.0V 5.0V 5.0V 6.25V 6.25V 6.25V
Outputs
DOUT High DOUT High
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Functional Description (Continued)
Program Inhibit
Programming multiple EPROM's parallel with different data also easily accomplished. Except like inputs (including parallel EPROM common. level program pulse applied EPROM's with 12.75V will program that EPROM. high level input inhibits other EPROM's from being programmed.
range. After programming, opaque labels should placed over EPROM window prevent unintentional erasure. Covering window will also prevent temporary functional failure generation photo currents. recommended erasure procedure EPROM exposure short wave ultraviolet light which wavelength integrated dose (i.e., intensity exposure time) erasure should minimum 15W-sec/cm2. device should placed within inch lamp tubes during erasure. device should placed within inch lamp tubes during erasure. erasure system should calibrated periodically. distance from lamp device should maintained inch. erasure time increases square distance from lamp. distance doubled erasure time increases factor Lamps lose intensity they age. When lamp changed, distance changed, lamp aged, system should checked make certain full erasure occurring. Incomplete erasure will cause symptoms that misleading. Programmers, components even system designs have been erroneously suspected when incomplete erasure problem.
Program Verify
verify should performed programmed bits determine whether they were correctly programmed. verify performed with 12.75V. must VCC, except during programming program verify.
MANUFACTURER'S IDENTIFICATION CODE
part manufacturer's indentification code programming. When device inserted EPROM programmer socket, programmer reads code then automatically calls specific programming algorithm part. This automatic programming control only possible with programmers which have capability reading code. Manufacturer's Identification code, shown Table specifically identifies manufacturer device type. code NM27C020 "8F8E," where "8F" designates that made Fairchild Semiconductor, "8E" designates Megabit bytewide part. code accessed applying ±0.5V address Addresses control pins held VIL, except Address held manufacturer's code, held device code. code read eight data pins, Proper code access only guaranteed 25°C 5°C.
SYSTEM CONSIDERATION
power switching characteristics EPROMs require careful decoupling devices. supply current, ICC, three segments that interest system designer: standby current level, active current level, transient current peaks that produced voltage transitions input pins. magnitude these transient current peaks dependent output capacitance loading device. associated transient voltage peaks suppressed properly selected decoupling capacitors. recommended that least ceramic capacitor used every device between GND. This should high frequency capacitor inherent inductance. addition, least bulk electrolytic capacitor should used between each eight devices. bulk capacitor should located near where power supply connected array. purpose bulk capacitor overcome voltage drop caused inductive effects board traces.
ERASURE CHARACTERISTICS
erasure characteristics device such that erasure begins occur when exposed light with wavelengths shorter than approximately 4000 Angstroms should noted that sunlight certain types fluorescent lamps have wavelengths
TABLE Manufacturer's Identification Code Pins
Manufacturer Code Device Code
(12)
(26)
(21)
(19)
(18)
(17)
(16)
(15)
(14)
(13)
Data
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.660 0.590-0.620
0.025
0.585
100°
0.008-0.012 +0.025 -0.060
0.685 0.030-0.055 WINDOW SIZE CONFIGURATION DETERMINED DEVICE SIZE
0.005 0.225 0.125
0.050-0.060
0.10 0.175
0.015 -0.060 86°-94° 0.150
0.060-0.100
0.090-0.110
0.015-0.021
32-Lead EPROM Ceramic Dual-In-Line Package Order Number NM27C020Q Package Number J32AQ
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
1.64 1.66 (41.66 42.164)
0.062 (1.575)
0.490 0.550 (12.446 13.97)
IDENT
0.580 (14.73) 0.600 0.620 (15.240 15.748)
0.050 (1.270)
0.125 0.165 (3.175 4.191)
0.145 0.210 (3.683 5.334)
90°-105° 0.008 0.015 (0.203 0.381) 0.040 0.090 (1.016 2.286)
86°- 0.018 ±0.003 (0.457 ±0.078)
0.015 (0.381) 0.120 0.150 (3.048 3.81)
0.100 ±0.010 (2.540 ±0.254) 0.035 0.07 (0.889 1.778)
32-Lead PDIP Package Order Number NM27C020N
NM27C020 Rev.
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NM27C020 2,097,152-Bit (256K Erasable CMOS EPROM
Physical Dimensions inches (millimeters) unless otherwise noted
0.485-0.495 [12.32-12.57] 0.007[0.18] 0.449-0.453 [11.40-11.51] -A0.045 [1.143] 0.000-0.010 [0.00-0.25] Polished Optional 0.549-0.553 [13.94-14.05] -B0.585-0.595 [14.86-15.11] 0.541-0.545 [13.74-13-84] 0.007[0.18] 0.002[0.05] 0.106-0.112 [2.69-2.84] 0.023-0.029 [0.58-0.74]
Base Plane
0.015 [0.38]
[10.16]
0.400
0.490-0530 [12.45-13.46] 0.015[0.38] D-E,
-E0.002[0.05] 0.007[0.18] 0.007[0.18]
0.050 detail -J0.007[0.18] 0.078-0.095 [1.98-2.41] -C0.004[0.10] 0.020 [0.51] 0.005 [0.13] 0.0100 [0.254] D-E, 0.013-0.021 [0.33-0.53]
0.123-0.140 [3.12-3.56]
0.118-0.129 [3.00-3.28] 0.010[0.25] D-E,
0.042-0.048 45°X [1.07-1.22]
0.026-0.032 [0.66-0.81] 0.007[0.18]
D-E,
32-Lead PLCC Package Order Number NM27C020V Package Number VA32A
0.045 [1.14] 0.025 [0.64] 0.025 [0.64] 0.006-0.012 [0.15-0.30] 0.019-0.025 [0.48-0.64]
Detail Typical Rotated
0.030-0.040 [0.76-1.02]
0.021-0.027 [0.53-0.69]
0.065-0.071 [1.65-1.80]
0.053-0.059 [1.65-1.80]
0.031-0.037 [0.79-0.94]
0.027-0.033 [0.69-0.84]
Section Typical
Life Support Policy
Fairchild's products authorized critical components life support devices systems without express written approval President Fairchild Semiconductor Corporation. used herein: Life support devices systems devices systems which, intended surgical implant into body, support sustain life, whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user.
Fairchild Semiconductor Americas Customer Response Center Tel. 1-888-522-5372 Fairchild Semiconductor Europe Fax: 1793-856858 Deutsch Tel: 8141-6102-0 English Tel: 1793-856856 Tel: 1-6930-3696 Italiano Tel: 2-249111-1
critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness.
Fairchild Semiconductor Hong Kong 8/F, Room 808, Empire Centre Mody Road, Tsimshatsui East Kowloon. Hong Kong Tel; +852-2722-8338 Fax: +852-2722-8383
Fairchild Semiconductor Japan Ltd. Natsume Bldg. 2-18-6, Yushima, Bunkyo-ku Tokyo, 113-0034 Japan Tel: 81-3-3818-8840 Fax: 81-3-3818-8841
Fairchild does assume responsibility circuitry described, circuit patent licenses implied Fairchild reserves right time without notice change said circuitry specifications.
NM27C020 Rev.
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