High Speed CMOS Parallel FIFO M67206 implements first-in first-ou

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High Speed CMOS Parallel FIFO M67206 implements first-in first-ou

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M67206
High Speed CMOS Parallel FIFO
M67206 implements first-in first-out algorithm, featuring asynchronous read/write operations. FULL EMPTY flags prevent data overflow underflow. Expansion logic allows unlimited expansion word size depth with timing penalties. Twin address pointers automatically generate internal read write addresses, external address information required TEMIC FIFOs. Address pointers automatically incremented with write read pin. bits wide data used data communications applications where parity error checking necessary. Retransmit reset Read pointer zero without affecting write pointer. This very useful retransmitting data when error detected system. Using array eight transistors memory cell fabricated with state lithography named SCMOS, M67206 combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability M67206 processed according methods latest revision (class and/or 9000.
Features
First-in first-out dual port memory 16384 organisation Fast Flag access times Commercial Industrial automotive Military Wide temperature range 67206L power 67206V very power Fully expandable word width depth Asynchronous read/write operations Empty, full half flags single device mode Retransmit capability Bi-directional applications Battery back-up operation data retention compatible Single power supply High Performance SCMOS Technology
MATRA Rev. April.
M67206
Interface
Block Diagram
16384
16384
Configuration
plastic mils ceramic mils mils PLCC
(top view)
INDEX
(top view)
Preview
FL/RT XO/HF
FL/RT XO/HF
MATRA Rev. April.
M67206
Names
NAMES
I0-8 Q0-8 Inputs Outputs Write Enable Read Enable Reset Empty Flag
DESCRIPTION
NAMES
XO/HF FL/RT
DESCRIPTION
Full Flag Expansion Out/Half-Full Flag Expansion First Load/Retransmit Power Supply Ground
Signal Description
Data
Data inputs data pointers first location. reset required after power-up before write operation enabled. Both Read Enable Write Enable inputs must high state during period shown Figure (i.e. tRSS before rising edge should change until tRSR after rising edge Half-Full Flag (HF) will reset high After Reset (RS)
Reset (RS)
Reset occurs whenever Reset (RS) input taken state. Reset returns both internal read write Figure Reset
(tRR)
Notes
change status during reset, flags will valid tRSC. around rising edge
Write Enable
write cycle initiated falling edge this input Full Flag (FF) set. Data set-up hold times must maintained rise time leading edge Write Enable (W). Data stored sequentially array, regardless current read operation. Once half memory filled, during falling edge next write operation, Half-Full Flag (HF) MATRA Rev. April. will remain this state until difference between write read pointers less than equal half total available memory device. Half-Full Flag (HF) then reset rising edge read operation. prevent data overflow, Full Flag (FF) will low, inhibiting further write operations. completion
M67206
valid read operation, Full Flag (FF) will high after TRFF, allowing valid write begin. When FIFO stack full, internal write pointer blocked from that external changes will have effect full FIFO stack.
Expansion (XI)
This input dual-purpose pin. Expansion (XI) connected indicate operation single device mode. Expansion (XI) connected Expansion (XO) previous device Depth Expansion Daisy Chain modes.
Read Enable
read cycle initiated falling edge Read Enable provided that Empty Flag (EF) set. data accessed first in/first basis, with standing current write operations. After Read Enable goes high, Data Outputs will return high impedance state until next Read operation. When data FIFO stack been read, Empty Flag (EF) will low, allowing "final" read cycle, inhibiting further read operations whilst data outputs remain high impedance state. Once valid write operation been completed, Empty Flag (EF) will high after tWEF valid read then initiated. When FIFO stack empty, internal read pointer blocked from that external changes will have effect empty FIFO stack.
Full Flag (FF)
Full Flag (FF) will low, inhibiting further write operations when write pointer location less than read pointer, indicating that device full. read pointer moved after Reset (RS), Full Flag (FF) will after 16384 writes.
Empty Flag (EF)
Empty Flag (EF) will low, inhibiting further read operations when read pointer equal write pointer, indicating that device empty.
Expansion Out/Half-Full Flag (XO/HF) First Load/Retransmit (FL/RT)
This dual-purpose input. Depth Expansion Mode, this connected ground indicate that first loaded (see Operating Modes). Single Device Mode, this acts retransmit input. Single Device Mode initiated connecting Expansion (XI) ground. M67206 made retransmit data when Retransmit Enable Control (RT) input pulsed low. retransmit operation will internal read point first location will affect write pointer. Read Enable Write Enable must high state during retransmit. retransmit feature intended when number writes equals less than depth FIFO occured since last cycle. retransmit feature compatible with Depth Expansion Mode will affect Half-Full Flag (HF), accordance with relative locations read write pointers. This dual-purpose output. single device mode, when Expansion (XI) connected ground, this output acts indication half-full memory. After half memory filled falling edge next write operation, Half-Full Flag (HF) will will remain until difference between write read pointers less than equal half total memory device. Half-Full Flag (HF) then reset rising edge read operation. Depth Expansion Mode, Expansion (XI) connected Expansion (XO) previous device. This output acts signal next device Daisy Chain providing pulse next device when previous device reaches last memory location.
Data Output
DATA output 9-bit wide data. This data high impedance condition whenever Read high state.
MATRA Rev. April.
M67206
Functional Description
Operating Modes Single Device Mode
single M67206 used when application requirements 16384 words less. M67206 Single Device Configuration when Expansion Figure Block Diagram Single 16384
(HALF-FULL FLAG) WRITE DATAIN READ
(XI) control input grounded (see Figure 2.). this mode Half-Full Flag (HF), which active output, shared with Expansion (XO).
67206
DATAOUT
FULL FLAG (FF) RESET (RS)
(EF) EMPTY FLAG (RT) RETRANSMIT
EXPANSION (XI)
Width Expansion Mode
Word width increased simply connecting corresponding input control signals multiple devices.
Status flags (EF, detected from device. Figure demonstrates 18-bit word width using M67206. word width attained adding additional M67206.
Figure Block Diagram 16384 FIFO Memory Used Width Expansion Mode.
DATAIN READ WRITE FULL FLAG RESET (RS) DATAOUT Note Flag detection accomplished monitoring signals either (any) device used width expansion configuration. connect output control signals together. (FF)
67206
67206
(EF) EMPTY FLAG (RT) RETRANSMIT
MATRA Rev. April.
M67206
Table Reset retransmit Single Device Configuration/Width Expansion Mode
INPUTS MODE
Reset Retransmit Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero Increment(4)
Write Pointer
Location Zero Unchanged Increment(4)
Note Pointer will increment flag high.
Table Reset First Load Truth Table Depth Expansion/Compound Expansion Mode
INPUTS MODE
Reset First Device Reset Other Devices Read/Write
INTERNAL STATUS
OUTPUTS
Read Pointer
Location Zero Location Zero
Write Pointer
Location Zero Location Zero
Note connected previous device. Figure
Depth Expansion (Daisy Chain) Mode
M67206 easily adapted applications which require more than 16384 words. Figure demonstrates Depth Expansion using three M67206. depth achieved adding additional 67206. M67206 operates Depth Expansion configuration following conditions first device must designated connecting First Load (FL) control input ground. other devices must have high state. Expansion (XO) each device must connected Expansion (XI) next device. Figure External logic needed generate composite Full Flag (FF) Empty Flag (EF). This requires that EF's (i.e. must generate correct composite EF). Figure
Retransmit (RT) function Half-Full Flag (HF) available Depth Expansion Mode.
Compound Expansion Module
quite simple apply expansion techniques described above together create large FIFO arrays (see Figure 5.).
Bidirectional Mode
Applications which require data buffering between systems (each system being capable Read Write operations) created coupling M67206 shown Figure Care must taken ensure that appropriate flag monitored each system (i.e. monitored device which monitored device which use). Both Depth Expansion Width Expansion used this mode.
MATRA Rev. April.
M67206
Data Flow Through Modes
types flow-through modes permitted read write flow-through mode (Figure 18.), FIFO flow-through write flow-through mode. read stack allows single word data written flow-through mode (Figure 17.) FIFO stack allows immediately after single word data been read single word read after word been written from full FIFO stack. line causes empty FIFO stack. data enabled reset, line, being low, causes again (tWEF after leading edge which anticipation data word. word known first write edge remains until loaded into FIFO stack leading edge line raised from high, after which line must toggled when order write will into three-state mode after tRHZ line data into FIFO stack increment write will show pulse indicating temporary reset then will pointer. set. interval which low, more words written FIFO stack (the subsequent writes after first write edge will reset Empty Flag) however, same word (written first write edge) presented output read pointer will incremented low. toggling remaining words written FIFO will appear output accordance with read cycle timings. Figure Block Diagram 49152 FIFO Memory (Depth expansion).
67206
FULL
67206
EMPTY
67206
Figure Compound FIFO Expansion.
67206 DEPTH EXPANSION BLOCK 67206 DEPTH EXPANSION BLOCK 67206 DEPTH EXPANSION BLOCK Q(N-8) Q(N-8)
I(N-8)
I(N-8)
Notes depth expansion block section Depth Expansion Figure Flag detection section Width Expansion Figure
MATRA Rev. April.
M67206
Figure Bidirectional FIFO Mode.
67206
SYSTEM
SYSTEM
67206
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC GND) Input Output voltage applied (GND (Vcc Storage temperature
OPERATING RANGE
Military Automotive Industrial Commercial
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
67206-10 Parameter Description Version
67206-12
67206-15
AUTO
AUTO
UNIT
VALUE
ICCOP
Operating supply current Standby supply current Power down current
ICCSB
ICCPD (10)
MATRA Rev. April.
M67206
Parameters (continued)
67206-20 Parameter Description Version
67206-25
67206-30 ONLY
ONLY
2000
AUTO
UNIT
VALUE
ICCOP
Operating supply current Standby supply current Power down current
ICCSB
ICCPD (10)
Notes
measurements made with outputs open. FL/RT VIH. input Vcc.
M67206 PARAMETER
(11) (12) (13) (13) (13)
DESCRIPTION
Input leakage current Output leakage current Input voltage Input high voltage Input high voltage IND, AUTO,
10/- 12/- 15/- 20/-25/-
UNIT
VALUE
(14) (14) (15) (15) Notes
Output voltage Output high voltage Input capacitance Output capacitance
Vcc. VIH, VOUT VCC. -0.3 pulse width input VIH= 2.6V (Com), VIH= 2.8V (Mil, Auto, Ind) min, This parameter sampled tested MHz.
MATRA Rev. April.
M67206
Test Conditions
Input pulse levels Input rise/Fall times Input timing reference levels Output reference levels Output load Figure Figure Output Load.
OUTPUT
includes scope capacitance
SYMBOL (16)
SYMBOL (17)
PARAMETER
67206
M67206 COM, MIL, IND, AUTO
M67206 COM, MIL, IND, AUTO
M67206 COM, IND, AUTO
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ TWLWL TWLWH TWHWL TDVWH TWHDX TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset Reset HF/FF high Read Read high high Read width after high Write high high Write Write Read high high Write width after high tRPW tRLZ tWLZ tRHZ tWPW tRSC tRSS tRSR tRTC tRTS tRTR Read cycle time Access time Read recovery time Read pulse width (19) Read data (20) Write data (20, Data valid from read high Read high data high (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time
WRITE CYCLE
RESET CYCLE
RETRANSMIT CYCLE
MATRA Rev. April.
M67206
SYMBOL (16) SYMBOL (17) PARAMETER M67206 COM, IND, AUTO MIN.
READ CYCLE TRLRL TRLQV TRHRL TRLRH TRLQX TWHQX TRHQX TRHQZ TWLWL TWLWH TWHWL TDVWH TWHDX TRSLWL TRSLRSH TWHRSH TRSHWL TRTLWL TRTLRTH TWHRTH TRTHWL FLAGS TRSLEFL TRSLFFH TRLEFL TRHFFH TEFHRH TWHEFH TWLFFL TWLHFL TRHHFH TFFHWH tEFL tHFH, tFFH tREF tRFF tRPE tWEF tWFF tWHF tRHF tWPF Reset Reset HF/FF high Read Read high high Read width after high Write high high Write Write Read high high Write width after high tRPW tRLZ tWLZ tRHZ tWPW tRSC tRSS tRSR tRTC tRTS tRTR Read cycle time Access time Read recovery time Read pulse width (19) Read data (20) Write data (20, Data valid from read high Read high data high (20) Write cycle time Write pulse width (19) Write recovery time Data set-up time Data hold time Reset cycle time Reset pulse width (19) Reset set-up time Reset recovery time Retransmit cycle time Retransmit pulse width (19) Retransmit set-up time (20) Retransmit recovery time
M67206 only MIN. MAX.
M67206 COM, IND, AUTO MIN. MAX.
UNIT
MAX.
WRITE CYCLE
RESET CYCLE
RETRANSMIT CYCLE
MATRA Rev. April.
M67206
SYMBOL (16) SYMBOL (17) PARAMETER 67206 M67206 COM, MIL, IND, AUTO M67206 COM, MIL, IND, AUTO M67206 COM, IND, AUTO UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL tXOL tXOH tXIR tXIS Read/Write Read/Write high pulse width recovery time set-up time
SYMBOL (16) SYMBOL (17)
PARAMETER
M67206 COM, IND, AUTO (PREVIEW) MIN. MAX.
M67206 ONLY MIN.
UNIT
MAX.
EXPANSION TWLXOL TWHXOH TXILXIH TXIHXIL TXILRL Notes tXOL tXOH tXIR tXIS Read/Write Read/Write high pulse width recovery time set-up time
symbol. symbol. Timings referenced test conditions. Pulse widths less than minimum value allowed. Values guaranteed design, currently tested. Only applies read data flow-through mode. parameters tested only.
Figure Asynchronous Write Read Operation.
MATRA Rev. April.
M67206
Figure Full Flag from Last Write First Read.
Figure Empty Flag from Last Read First Write.
Figure Retransmit.
Note
change status during Retransmit, flags will valid tRTC.
MATRA Rev. April.
M67206
Figure Empty Flag Timing
Figure Full Flag Timing
Figure Half-Full Flag Timing.
HALF FULL OFFSET LESS HALF FULL OFFSET LESS
MORE THAN HALF FULL
MATRA Rev. April.
M67206
Figure Expansion Out.
Figure Expansion
Figure Read Data Flow Through Mode.
MATRA Rev. April.
M67206
Figure Write Data Flow Through Mode.
MATRA Rev. April.
M67206
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67206L SPEED FLOW
ceramic mils plastic mils rectangular PLCC mils side brazed Flat pack pins mils Dice form
Commercial Industrial Automotive Military Space
-40° -40° -55° -55°
+70°C +85°C +125°C +125°C +125°C
67206 16384 FIFO power Very power
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX
standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
Military Space Versions
Please check availability
following table gives package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
Access Time (ns)
process 672064
flows
process 67206E
flows Space flows
product production call sales office availibility
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. April.

High Speed CMOS Parallel FIFO M67206 implements first-in first-ou

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