CMOS Dual Port with Semaphore M671342 very power CMOS dual port s

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CMOS Dual Port with Semaphore M671342 very power CMOS dual port s

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M671342
CMOS Dual Port with Semaphore
M671342 very power CMOS dual port static organised 4096 with full hardware support semaphore signaling between ports. M671342 device provide independant ports with separate control, address pins that permit independant, asynchronous access reads writes location memory. Only simultaneous write ports same location allowed. semaphores available chip assist arbitrating between ports. automatic power down feature controlled permits on-chip circuitry each port order enter very stand power mode. Using array eigh transistors (8T) memory cell fabricated with state lithography named SCMOS, 671342 combines extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability M671342 processed according methods latest revision (class and/or 9000.
Features
Fast Access Time 18/20/25/30/35/45 Wide Temperature Range -55°C +125°C 671342 Power 671342 Very Power Full On-Chip Hardware Support Semaphore Signaling Between Ports Fully Asynchronous Operation From Either Port Battery Back-up Operation Data Retention Compatible Single Power Supply Version Also Available, Please Consult Sales Available 52-pin Popular Hermetic Plastic Packages
Figure Block Diagram
R/WL I/O7L I/O0L A11L COLUMN COLUMN R/WR I/O7R I/O0R
SELECT
MEMORY ARRAY
SELECT
A11R
SEMAPHORE ARBITRATION
SEML
SEMR
MATRA Rev. Fev.
M671342
Names
Left Port
R/WL A0L-11L I/O0L-7L SEML
Right Port
R/WR A0R-11R I/O0R-7R SEMR
Names
Chip select Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Power Ground
Functional Description
Configuration
R/WR SEMR SEML R/WL
I/O0L I/O1L I/O2L I/O3L
LCC-52 PLCC-52
I/O7R
Truth Table
Table Contention Read/Write Control
Inputs
Outputs Mode
D0-7
DATAOUT Port Disabled Power Down Mode Data Semaphore Flag Output Port Output Disabled
Note A11L A11R HIGH, LOW, Don't Care, High Impedance Low-to-High transition.
MATRA Rev. Fev.
M671342
Functional Description
671342 ports with separate control, address pins that permit independent read/write access memory location. Both ports identical function standard CMOS static RAMs read from written same time, with only possible conflict arising from simultaneous writing non-semaphore location. semaphores, available 671342, protected against such ambiguous situations used system program avoid conflicts memory dual-port RAM. These devices have automatic power-down feature controlled CS.CS controls on-chip power-down circuitry which causes port concerned into stand-by mode when selected high). When port selected access full memory array permitted. Each port Output Enable control (OE). read mode, port's turns Output drivers when LOW. Non-conflicting READ/WRITE conditions illustrated table semaphore enable. pins control on-chip-power-down circuitry that permits port concerned into stand-by mode when selected. This conditions shown table where both high. Systems best able exploit 671342 based around multiple processors controllers typically very high-speed, software controlled software-intensive systems. These systems benefit from performance enhancement offered 671342 hardware semaphores, which provide lock-out mechanism without need complex programming. Software handshaking between processors offers maximum level system flexibility permitting shared resources allocated varying configurations. 671342 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using semaphores rather than more usual methods hardware arbitration that neither processor ever incurs wait states. This prove considerable advantage very high speed systems.
Semaphore Logic Functional Description
671342 extremely fast dual-port CMOS static with additional locations dedicated binary semaphore flags. These flags allow either processors left right side dual-port claim priority over other functions defined system software. example, semaphore flag used oner processor inhibit other from accessing portion dual-port other shared resource. dual-port fast access time, ports completely independent each another. This means that activity left port cannot slow access time right port. ports identical function standard CMOS static RAMs read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE operation non-semaphore location. Semaphores protected against such ambiguous situations used system program prevent conflicts non-semaphore segment dual-port RAM. devices have automatic power-down feature controlled dual-port select SEM,
Semaphore Flags Work
semaphore logic eight latches independent dual-port RAM. These latches used pass flag token, from port other indicate that shared resource use. semaphore provide hardware context "Token Passing Allocation" method assignment. This method uses state semaphore latch token indicating that shared resource use. left processor needs resource, requests token setting latch. processor then verifies that latch been reading latch been processor assumes control over shared resource. latch been set, left processor established that right processor latch first, token using shared resource. left processor then either repeatedly query status semaphore, abandon request token perform another operation whilst occasionally attempting gain control token through test operation. Once right side relinquished token left side will able take control shared resource.
MATRA Rev. Fev.
M671342
semaphore flags active low. token requested writing zero semaphore latch, relinquished again when same side writes latch. eight semaphore flags located separate memory space from dual-port 671342. address space accessed placing input (which acts chip select semaphore flags) using other control pins (address, R/W) normally used accessing standard static RAM. Each flags unique address accessed either side through address pins A0-A2. None other address pins effect when accessing semaphores. Only data used when writing semaphore. level written unused semaphore location, flag will zero that side other side (see table semaphore only modified side showing zero. Once writen this location from same side, flag will both sides (unless request pending from other side) semaphore then written either side. effect side writing zero semaphore location locking other side reason semaphore logic interprocessor communication. thorough discussion this feature follows below). zero written semaphore location from locked-out side will stored semaphore request latch that side until semaphore relinquished side having control. When semaphore flag read value distributed data bits that flag reads data bits flag zero reads zeros. read value latched into output register side when semaphore select (SEM) output enable (OE) signals active. This prevents semaphore changing state middle read cycle result write issued other side. Because this latch, repeated read semaphore flag test loop must cause either signal (SEM inactive, otherwise output will never change. semaphore must WRITE/READ sequence order ensure that system level conflict will occur. processor requests access shared resources attempting write zero semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, processor will detect this status subsequent read (see table example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written successfully that location will assume control over resource concerned. processor right side then attempts write zero same semaphore flag will fail, will verified subsequent read returning from semaphore location right side READ/WRITE sequence been used instead, system conflict problems could have occurred during interval between read write cycles. must noted that failed semaphore request needs followed either repeated reads writing same location. simple logic diagram semaphore flag figure illusrates reason this quite clearly. semaphore request latches feed into semaphore flag. first latch send zero semaphore flag will force side semaphore flag other side high. This status will maintained until written same semaphore request latch. Sould zero written other side's semaphore request latch meantime, semaphore flag will flip over this second side soon written first side's request latch. second side's flag will stay until semaphore request latch changed one. Thus, clearly, semaphore flag requested processor requesting longer requires access resource, entire system hang until written semaphore request latch concerned. Semaphore timing becomes critical when both sides request same token attempting write zero same time. Semaphore logic specially conceived resolve this problem. logic ensures that only side will receive token simultaneous requests made. first side make request will receive token where request arrive same time. Where they arrive same time, logic will assign token arbitrarily ports. should noted, however, that semaphores alone guarantee that access resource secure. with powerful programming technique, errors introduced semaphores misused misinterpreted. Code integrity utmost performance when semaphores being used instead slower, more restrictive hardware-intensive systems. Semaphore initialization automatic must therefore incorporated power initialization procedures. Since semaphore flag containing zero must reset one, initialization should write request flags from both sides ensure that they will available when required.
MATRA Rev. Fev.
M671342
Using Semaphores Some examples
Perhaps simplest application semaphores their resource markers 671342's dual-port RAM. necessary split into blocks which dedicated serving either left right port time. Semaphore used indicate which side controlling lower segment memory semaphore defined indicating upper segment memory. take control resource, this case lower dual-port RAM, left port processor would then write zero into semaphore flag then read back. successful taking token (reading back zero rather than one), left processor could then take control lower RAM. right processor attempts perform same function take control resource after left processor already done will read back response attempted write zero into semaphore this point software choose attempt gain control second segment writing then reading zero semaphore successful, will lock left processor. Once left side completed task will write semaphore then attempt access semaphore semaphore still occupied right side, left side abandon semaphore request perform other operations until able write then read zero semaphore right processor performs same operation with semaphore this protocol would then allow processes swap blocks dual-port between another. blocks have particular size, even variable size depending complexity software using semaphore flags. eight semaphores could used divide dual-port other shared resources into eight parts. Semaphores even assigned different meanings each side, rather than having common meaning described above example. Semaphores useful form arbitration systems such disk interfaces where must locked segment memory during data transfer operation, device cannot tolerate wait states. semaphores used, both device access assigned memory segments, without need wait states, once devices have determined which memory area barred CPU. Semaphores also useful applications where memory WAIT state available both sides. semaphore handshake been performed, both processors access their assigned segments full speed. Another application complex data structures. Block arbitration very important this case, since processor responsible building updating data structure whilst other processor reads interprets major error condition created interpreting processor reads incomplete data structure. Some sort arbitration between different processors therefore necessary. building processor requests access block, locks then able enter block update data structure. Once update completed data structure released. This allows interpreting processor, return read complete data structure, thus ensuring consistent data structure.
MATRA Rev. Fev.
M671342
Table Example Semaphore Procurement Sequence
Function
Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore
Left
Right
Semaphore free
Status
Left Port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left port semaphore token Semaphore free
Note This table denotes sequence events only semaphores M671342
Figure M671342 Semaphore Logic
MATRA Rev. Fev.
M671342
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND) Input output voltage applied (GND (VCC Storage temperature Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
Operating Supply Voltage
Military Industrial Commercial Automotive
Operating Temperature
Parameters
671342-18 Parameter Description
Standby supply current (Both ports level inputs) Standby supply current (Both ports CMOS level inputs) Operating supply current (Both ports active) Operating supply current (One port active port standby)
671342-20
671342-25
671342-30 Unit Value
Version
only
1000 1000 1000
ICCSB
ICCSB1
ICCOP
ICCOP1
Parameters (continued)
671342-35 Parameter Description
Standby supply current (Both ports level inputs) Standby supply current (Both ports CMOS level inputs) Operating supply current (Both ports active) Operating supply current (One port active port standby)
671342-45
Version
1000
1000
Unit
Value
ICCSB ICCSB1 ICCOP
ICCOP1 Notes
Both ports active Maximum frequency Outputs open port active fMAX) Output open port stand-by CMOS Level Inputs
MATRA Rev. Fev.
M671342
Parameter
VIH(6)
Description
Input/Output leakage current Input voltage Input high voltage Output voltage (I/O0-I/O15) Output high voltage Input capacitance Output capacitance
671342 -18/-20/-25/-30/-35/-45
Unit
Value
Notes VCC, VIH, Vout -0.3 pulse width min,
Data-retention Mode
CMOS RAMs designed with battery backup mind. Data retention voltage supply current guaranteed over temperature. following rules insure data retention Chip select (CS) must held high during data retention within must kept between during power power down transitions. begin operation after reaches minimum operating voltage (4.5 volts).
Timing
Parameter
ICCDR1 ICCDR2
Test Conditions
@VCCDR @VCCDR
Unit
Notes VCC, Read cycle time
Test Conditions Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load figures
MATRA Rev. Fev.
M671342
Figure Output Load. Figure Output Load (for tHZ, tOW).
Electrical Characteristics
Over Full Operating Temperature Supply Voltage Range
Read Cycle Parameter Symbol Sym(4)
TAVAVR TAVQV TELQV TGLQV TAVQX TELQZ TEHQZ TSOP TWDD TDDD Notes tACS tAOE tSOP tWDD tDDD Read cycle time Address access time Chip Select access time Output enable access time Output hold from address change Output time Output high time Chip Select power time Chip disable power down time flag update pulse SEM) Write pulse data delay Write data valid read data delay
M671342-1 M671342-2 M671342-2 M671342-3 M671342-3 M671342-4 only Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
Transition measured from high impedance voltage with load (figures This parameters guaranteed tested access VIL, VIH. access semaphore VIH, VIL. Refer table symbol symbol Port-to-port delay through cells from writing port reading port, refer Timing Waveforms Read with Port-to-port delay
MATRA Rev. Fev.
M671342
Timing Waveform Read Cycle Either Side
Timing Waveform Read Cycle Either Side
Notes
high read cycles. Device continuously enabled, VIL. This waveform cannot used semaphore reads. Addresses valid prior coincident with transition low. VIL. access RAM, VIL, VIH. access semaphore, VIH, VIL. Refer table
Timing Waveform Read with Port-to-Port Delay
ADDRR MATCH R/WR
DATAIN VALID
ADDRL
MATCH tWDD
DATAOUT tDDD
VALID
Notes Write cycle parameters should adhered order ensure proper writing. Device continuously enabled both ports.
MATRA Rev. Fev.
M671342
Electrical Characteristics
Over Full Operating Temperature Supply Voltage Range
Write Cycle Parameter Symbol Sym(5)
TAVAVW TELWH TAVWH TAVWL TWLWH TWHAX TDVWH TGHQZ TWHDX TWLQZ Write cycle time Chip select write Address valid write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid write Output high time Data hold time Write enable output high Output active from write flag write read time flag contention window
M671342-1 M671342-2 M671342-2 M671342-3 M671342-3 M671342-4 only Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Unit
TWHQX TSWRD TSPS
tSWRD tSPS
Notes Transition measured from high impedance voltage with load (figures This parameters guaranteed tested access VIL, VIH. access semaphore VIH, VIL. This condition must valid entire time. specification must device supplying write data under operating conditions. Although values will vary over voltage remperature, actual will always smaller than actual tOW. Symbol. Symbol.
MATRA Rev. Fev.
M671342
Timing Waveform Write Cycle Controlled Timing
Timing Waveform Write Cycle Controlled Timing
Notes
must high during adress transitions. write occurs during overlap (tSW tWP) R/W. measured from earlier R/W) going high write cycle. During this period, pins output state, input signals must applied. transition occurs simultaneously with after transition, outputs remain high impedance state. Transition measured from steady state with load (including scope jig). This parameter sampled tested. during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. high during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIL, VIH.
MATRA Rev. Fev.
M671342
Timing Waveform Semaphore Read after Write Timing, Either Side(1)
Note duration above timing (both write read cycle).
Timing Waveform Semaphore Contention(1,
Notes VIL, VIH, semaphore Flag released from both sides (reads ones from both sides) cycle start. Either side left side right, side right side left. This parameter measured from point where R/WA SEMA goes high until R/WB SEMB goes high. tSPS violated, semaphore will fall positively side other, there guaranteed which side will obtain flag.
MATRA Rev. Fev.
M671342
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 671342V SPEED FLOW
version version
pins PLCC CDIL48 mils LCC48 SB48 mils Flat Pack pins mils DUAL PORT Commercial Industrial Military Space -40° -55° -55° +70°C +85°C +125°C +125°C POWER VERY POWER
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX
standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
VERY POWER TOLERANT
Military Space Versions
following tables give package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
Access Time (ns)
process 67134
/883
process 67134E
/883 ESA-SCC
product production call sales office availibility
MATRA Rev. Fev.

CMOS Dual Port with Semaphore M671342 very power CMOS dual port s

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