CMOS Dual Port with Interrupt Flag M671321/671421 very power CMOS
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M671321/M671421
CMOS Dual Port with Interrupt Flag
M671321/671421 very power CMOS dual port static RAMs organized 2048 They designed used stand-alone dual port combination MASTER/SLAVE dual port bits more width systems. MASTER/SLAVE dual port approach memory system applications results full speed, error free operation without need additional discrete logic. Master slave devices provide independent ports with separate control, address pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits onchip circuitry each port order enter very stand power mode. Using array eight transistors (8T) memory cell fabricated with state lithography named SCMOS, M671321/671421 combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability 671321/1421 processed according methods latest revision (class and/or 9000. M67132/M67142 parameters. specification AC.DC
Features
Fast access time 671321L/671421L power 671321V/671421V very power Expandable data bits more using master/slave devices when using more than device. chip arbitration logic BUSY output flag master 671321) BUSY input flag slave 671421) flag port port communication Fully asynchronous operation from either port Battery backup operation data retention compatible Single Power Supply
3.3V versions. Please consult sales.
MATRA Rev. Fev.
M671321/M671421
Interface
Block Diagram
A10L
A10R
Notes 671321 (MASTER) BUSY open drain output requires pull resistor 671421 (SLAVE) BUSY input Open drain output requires pull resistor
Configuration
PLCC (top view)
Names
LEFT PORT
R/WL I/O0L BUSYL INTL
RIGHT PORT
R/WR I/O0R BUSYR INTR
NAMES
Chip select Write Enable Output Enable Address Data Input/Output Busy Flag Interrupt Flag Power Ground
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. Fev.
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