CMOS Dual Port M67132/67142 very power CMOS dual port static RAMs

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CMOS Dual Port M67132/67142 very power CMOS dual port static RAMs

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M67132/M67142
CMOS Dual Port
M67132/67142 very power CMOS dual port static RAMs organized 2048 They designed used stand-alone dual port combination MASTER/SLAVE dual port bits more width systems. TEMIC MASTER/SLAVE dual port approach memory system applications results full speed, error free operation without need additional discrete logic. Master slave devices provide independent ports with separate control, address pins that permit independent, asynchronous access reads writes location memory. automatic power down feature controlled permits onchip circuitry each port order enter very stand power mode. Using array eight transistors (8T) memory cell fabricated with state lithography named SCMOS, M67132/142 combine extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability 67132/142 processed according methods latest revision (class and/or 9000.
Features
Fast Access Time Preliminary Commercial only 67132L/67142L Power 67132V/67142V Very Power Expandable Data Bits More Using Master/Slave Devices when Using More than Device. Chip Arbitration Logic BUSY Output Flag Master BUSY Input Flag Slave Fully Asynchronous Operation from Either Port Battery Backup Operation Data Retention Compatible Single Power Supply
3.3V versions also available. Please consult sales. Versions with interrupt also available. Please consult sales.
MATRA Rev. April.
M67132/M67142
Interface
Configuration
(top view), plastic, ceramic mils PLCC (top view) PLCC (top view)
VQFP (top view)
Block Diagram
A10L
A10R
MATRA Rev. April.
M67132/M67142
Names
LEFT PORT
R/WL I/O0L BUSYL
RIGHT PORT
R/WR I/O0R BUSYR
NAMES
Chip select Write Enable Output Enable Address Data Input/Output Busy Flag Power Ground
Functional 67132/M67142 ports with separate control, address pins that permit independent read/write access memory location. These devices have automatic power-down feature controlled controls on-chip power-down circuitry which causes port concerned into stand-by mode when selected high). When port selected access full memory array permitted. Each port Output Enable control (OE). read mode, port's turns Output drivers when LOW. Non-conflicting READ/WRITE conditions illustrated table control logic arbitrates between left right addresses access (refer table inhibited port's BUSY flag will reset when port granted access completes operation both arbitration modes.
Data Width Expansion
Master/Slave Description Expanding data width more bits dual-port system means that several chips active simultaneously. every chip hardware arbitrator, addresses each chip arrive same time chip activate BUSY signal while another activates BUSY signal. Both sides busy CPUs will wait indefinitely their port become free. overcome this "Busy Lock-Out" problem, developed MASTER/SLAVE system which uses single hardware arbitrator located MASTER. SLAVE BUSY inputs which allow direct interface MASTER with external components, giving speed advantage over other systems. When dual-port RAMs expanded width, SLAVE RAMs must prevented from writing until BUSY input been settled. Otherwise, SLAVE chip begin write cycle during conflict situation. opposite, write pulse must extend hold time beyond BUSY ensure that write cycle occurs once conflict resolved. This timing inherent dual-port memory systems where more than chip active same time. write pulse SLAVE must inhibited MASTER's maximum arbitration time. conflict then occurs, write SLAVE will inhibited because MASTER's BUSY signal.
Arbitration Logic
arbitration logic will resolve address match chip select match down minimum determine which port access. cases, active BUSY flag will inhibited port. BUSY flags required when both ports attempt access same location simultaneously.Should this conflict arise, on-chip arbitration logic will determine which port access BUSY flag inhibited port. BUSY speeds that allow processor hold operation with associated address data. should noted that operation invalid port which BUSY LOW. inhibited port will given access when BUSY goes inactive. conflict will occur when both left right ports active addresses coincide. on-chip arbitration determines access these circumstances. modes arbitration provided addresses match valid before on-chip control logic arbitrates between access before address match, on-chip
MATRA Rev. April.
M67132/M67142
Truth Table
Table Contention Read/Write Control(4)
LEFT RIGHT PORT(1)
Notes
D0-7
DATAIN DATAOUT
FUNCTION
Port Disabled Power Down Mode. ICCSB ICCSB1 Data Port Written into memory(2) Data Memory Output Port(3) High Impedance Outputs
A10L A10R. BUSY data written. BUSY data valid, tWDD tDDD timing. HIGH, LOW, DON'T CARE, HIGH IMPEDANCE.
Table Arbitration(5)
LEFT PORT
RIGHT PORT
FLAGS BUSYL
FUNCTION BUSYR
A10L
A10R
A10R
A10L
FUNCTION
Contention Contention Contention Contention
ADDRESS ARBITRATION WITH BEFORE ADDRESS MATCH LV5R RV5L Same Same LV5R RV5L Same Same L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
ARBITRATION WITH ADDRESS MATCH BEFORE LL5R RL5L LW5R LW5R Notes A10R A10R A10R A10R LL5R RL5L LW5R LW5R A10L A10L A10L A10L L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
DON'T CARE, LOW, HIGH. LV5R Left Address Valid before right address. RV5L Right address Valid before left address. Same Left Right Addresses match within each other. LL5R Left before Right RL5L Right before left LW5R Left Right within each other.
MATRA Rev. April.
M67132/M67142
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND) -0.3 Input output voltage applied (GND -0.3 (VCC Storage temperature -65°C 150°C Notice Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device.This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extented periods affect reliability.
OPERATING RANGE
Military Automotive Commercial Industrial
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
67132/142-30 67132/142-35 67132/142-45 67132/142-55 Parameter Description Versio Preliminary 1000 1000 Unit Value AUTO AUTO AUTO 2000 1000 2000 1000 2000
ICCSB ICCSB1 ICCOP ICCOP1 Notes
Standby supply current (Both ports level inputs) Standby supply current (Both ports CMOS level inputs) Operating supply current (Both ports active) Operating supply current (One port active port standby)
Both ports active Maximum frequency Outputs open VIH. port active MAX) Output open port stand-by CMOS Level inputs
PARAMETER
II/O(10) VIL(11) VIH(11) VOL(12) VOL(13) VOH(12) CIN(17) COUT(17) Notes
DESCRIPTION
Input/Output leakage current Input voltage Input high voltage Output voltage Open drain output voltage (BUSY) Output high voltage Input capacitance Output capacitance
67132-30/35/45/55 67142-30/35/45/55
UNIT
VALUE
VCC, VIH, Vout VCC. pulse width min,
MATRA Rev. April.
M67132/M67142
Data-Retention Mode
CMOS RAMs designed with battery backup mind. Data retention voltage supply current guaranteed over temperature. following rules insure data retention Chip select (CS) must held high during data retention within VCCDR. must kept between during power power down transitions. begin operation after reaches minimum operating voltage (4.5 volts).
Timing
PARAMETER TEST CONDITIONS (14)
ICCDR1 ICCDR2 VCCDR VCCDR
AUTO
UNIT
Notes Vcc, Vcc. Read cycle time.
Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Figure Output Load. Output Reference Levels Output Load figures
Figure Output load. (For tHZ, tLZ, tWZ, tOW)
MATRA Rev. April.
M67132/M67142
Parameters
READ CYCLE PARAMETER SYMBOL SYMBOL (19) (20) TAVAVR TAVQV TELQV TGLQV TAVQX TELQZ TEHQZ Notes (*). (**). tACS tAOE Read cycle time Address access time Chip Select access time (18) Output enable access time Output hold from address change Output time (16, Output high time (16, Chip Select power time (17) Chip disable power down time (17) M67132-30(*) M67142-30(*) MIN. MAX. M67132-35(**) M67142-35(**) MIN. MAX. M67132-45 M67142-45 M67132-55 67142-55
MIN. MAX. MIN. MAX. UNIT
PRELIMINARY
Transition measured from high impedance voltage with load (figures This parameter guaranteed tested. access VIL. symbol. symbol. Commercial only, available DIP. package available commercial only.
Timing Waveform Read Cycle Either Side (21,
Timing Waveform Read Cycle Either Side (21,
Notes
high read cycles. Device continuously enabled, VIL. Addresses valid prior coincident with transition low. access RAM, VIL.
MATRA Rev. April.
M67132/M67142
Parameters
WRITE CYCLE PARAMETER SYMBOL SYMBOL (30) (31) TAVAVW TELWH TAVWH TAVWL TWLWH TWHAX TDVWH TGHQZ TWHDX TWLQZ TWHQX Notes Write cycle time Chip select write (28) Address valid write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid write Output high time (26, Data hold time (29) Write enable output high (26, Output active from write (26, M67132-30(*) M67142-30(*) MIN. MAX. M67132-35(**) M67142-35(**) MIN. MAX. M67132-45 M67142-45 M67132-55 67142-55
MIN. MAX. MIN. MAX. UNIT
PRELIMINARY
Transition measured from high impedance voltage with load (figures This parameter guaranteed tested. access VIL. This condition must valid entire time. specification must device supplying write data under operating conditions. Although values vary over voltage temperature, actual will always smaller than actual tOW. symbol. symbol. (*). Commercial only, available DIP. (**). package available commercial only.
MATRA Rev. April.
M67132/M67142
Timing Waveform Write Cycle Controlled Timing (32,
Timing Waveform Write Cycle Controlled Timing (32,
Notes
must high during address transitions. write occurs during overlap (tSW tWP) R/W. measured from earlier going high write cycle. During this period, pins output state, input signals must applied. transition occurs simultaneously with after transition, outputs remain high impedance state. Transition measured from steady state with load (including scope jig). This parameter sampled tested. during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. high during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIL.
MATRA Rev. April.
M67132/M67142
Parameters
SYMBOL PARAMETER M67132-30(*) M67142-30(*) MIN. BUSY TIMING M67132 only) (For PRELIMINARY tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD BUSY Access time address BUSY Disable time address BUSY Access time Chip Select BUSY Disable time Chip Select Write Pulse data delay (40) Write data valid read data delay (40) Arbitration priority set-up time (41) BUSY disable valid data Note Note Note Note MAX. M67132-35(**) M67142-35(**) MIN. MAX. M67132-45 M67142-45 MIN. MAX. M67132-55 67142-55 MIN. MAX. UNIT
BUSY TIMING (For 67142 only) tWDD tDDD Notes Write BUSY input (43) Write hold after BUSY (44) Write pulse data delay (45) Write data valid read data delay (45)
Port-to-port delay through cells from writing port reading port, refer "Timing Waveform Read with BUSY (For M67132 only)". ensure that earlier ports wins. tBDD calculated parameter greater tWDD (actual) tDDD (actual). ensure that write cycle inhibited during contention. ensure that write cycle completed after contention. Port-to-port delay through cells from writing port reading port, refer "Timing Waveforms Read with Port port delay (For M67132 only)". (*). Commercial only, available DIP. (**). package commercial only.
MATRA Rev. April.
M67132/M67142
Timing Waveform Read with BUSY (46, (For M67132)
Notes
ensure that earlier port wins. Write cycle parameters should adhered ensure proper writing. Device continuously enabled both ports. reading port.
Timing Waveform Write with Port-to-port (50, (For M67142 only)
Notes
Assume BUSY writing port, reading port. Write cycle parameters should adhered ensure proper writing. Device continuously enabled both ports.
MATRA Rev. April.
M67132/M67142
Timing Waveform Write with BUSY (For M67132)
Timing Waveform Contention Cycle Arbitration (For M67132 only)
MATRA Rev. April.
M67132/M67142
Timing Waveform Contention Cycle Address Valid Abritration (For M67132 only) (53) Left Address Valid First
Right Address Valid First
Note
Master/Slave Dual-port Memory Systems
Note
arbitration M67142 (SLAVE). BUSY inhibits write M67142 (SLAVE).
MATRA Rev. April.
M67132/M67142
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67132V SPEED FLOW
ceramic mils side-brazed mils PLCC plastic mils VQFP Flat pack pins mils CQPJ52 Dice form Commercial Industrial Automotive Military Space -40° -40° -55° -55° +70°C +85°C +125°C +125°C +125°C
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX
standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
67132 67142
Master Slave power Very power
MATRA Rev. April.
M67132/M67142
Military Space Versions
following tables give package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
Access Time (ns)
process 67132
flows (including SMD5962-87002) flows
process 67132E
Space flows (including SCC9301033)
Temp. range
Packages
Consumption
Access Time (ns)
process 67142
flows (including SMD5962-87002) flows
process 67142E
Space flows (including SCC9301033)
product production call sales office availibility
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. April.

CMOS Dual Port M67132/67142 very power CMOS dual port static RAMs

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