CMOS Dual Port M67005 very power CMOS dual port static organized

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CMOS Dual Port M67005 very power CMOS dual port static organized

Datasheet Thumbnail

Top Searches for this datasheet

M67005
CMOS Dual Port
M67005 very power CMOS dual port static organized 8192 M67005 designed used stand-alone dual port combination MASTER/SLAVE dual port more width systems. Using TEMIC MASTER/SLAVE dual port approach memory system applications results full speed, error free operation without need additional discrete logic. Master slave devices provide independant ports with separate control, address pins that permit independant, asynchronous access reads writes location memory. automatic power down feature controlled permits onchip circuitry each port order enter very stand-by power mode. Using array eight transistors (8T) memory cell fabricated with state lithography named SCMOS, M67005 combines extremely standby supply current (typ with fast access time over full temperature range. versions offer battery backup data retention capability with typical power consumption less than military/space applications that demand superior levels performance reliability M67005 processed according methods latest revision (class and/or 9000.
Features
Fast access time preview commercial only Wide temperature range 67005L power 67005V very power Expandable data bits more using master/slave chip select when using more than device chip arbitration logic Versatile select master slave busy output flag master busy input flag slave flag port port communication Full hardware support semaphore signaling between ports Fully asynchronous operation from either port Battery back operation data retention compatible Single power supply
versions also available. Please consult sales.
MATRA Rev. April.
M67005
Interface
Block Diagram
Note
(MASTER) BUSY output. (SLAVE) BUSY input.
Names
LEFT PORT
R/WL I/O0L SEML INTL BUSYL
RIGHT PORT
R/WR I/O0R SEMR INTR BUSYR
NAMES
Chip select Read/Write Enable Output Enable Address Data Input/Output Semaphore Enable Interrupt Flag Busy Flag Master Slave Select Power Supply Ground
MATRA Rev. April.
M67005
Configuration
Notes
pins must connected power supply. pins must connected ground supply.
MATRA Rev. April.
M67005
Functional Description
M67005 ports with separate control, address pins that permit independent read/write access memory location. These devices have automatic power-down feature controlled controls on-chip power-down circuitry which causes port concerned into stand-by mode when selected high). When port selected access full memory array permitted. Each port Output Enable control (OE). read mode, port's turns Output drivers when LOW. Non-conflicting READ/WRITE conditions illustrated table interrupt flag (INT) allows communication between ports systems. user chooses interrupt function, memory location (mail message center) assigned each port. left port interrupt flag (INTL) when right port writes memory location 1FFE (HEX). left port clears interrupt reading address location 1FFE. Similarly, right port interrupt flag (INTR) when left port writes memory location 1FFF (hex), right port must read memory location 1FFF order clear interrupt flag (INTR). message 1FFE 1FFF user-defined. interrupt function used, address locations 1FFE 1FFF reserved mail boxes become part RAM. table interrupt function. control logic arbitrates between left right addresses access (refer table inhibited port's BUSY flag will reset when port granted access completes operation both arbitration modes.
Data Width Expansion Master/Slave Description
Expanding data width more bits dual-port system means that several chips active simultaneously. every chip hardware arbitrator, addresses each chip arrive same time chip activate BUSY signal while another activates BUSY signal. Both sides busy CPUs will wait indefinitely their port become free. overcome this "Busy Lock-Out" problem, developed MASTER/SLAVE system which uses single hardware arbitrator located MASTER. SLAVE BUSY inputs which allow direct interface MASTER with external components, giving speed advantage over other systems. When dual-port RAMs expanded width, SLAVE RAMs must prevented from writing until BUSY input been settled. Otherwise, SLAVE chip begin write cycle during conflict situation. opposite, write pulse must extend hold time beyond BUSY ensure that write cycle occurs once conflict resolved. This timing inherent dual-port memory systems where more than chip active same time. write pulse SLAVE must inhibited MASTER's maximum arbitration time. conflict then occurs, write SLAVE will inhibited because MASTER's BUSY signal.
Arbitration Logic
arbitration logic will resolve address match chip select match down minimum determine which port access. cases, active BUSY flag will inhibited port. BUSY flags required when both ports attempt access same location simultaneously.Should this conflict arise, on-chip arbitration logic will determine which port access BUSY flag inhibited port. BUSY speeds that allow processor hold operation with associated address data. should noted that operation invalid port which BUSY LOW. inhibited port will given access when BUSY goes inactive. conflict will occur when both left right ports active addresses coincide. on-chip arbitration determines access these circumstances. modes arbitration provided addresses match valid before on-chip control logic arbitrates between access before address match, on-chip
Semaphore Logic
M67005 externaly fast dual-port CMOS static with additional address locations dedicated binary semaphore flags. These flags allow processors left right side dual-port claim priority over other functions defined system software. example, semaphore flag used processor inhibit other from accessing portion dual-port other shared resource.
MATRA Rev. April.
M67005
dual-port fast access time, ports completely independent another. This means that activity left port cannot slow access time right port. ports identical function standard CMOS static RAMs read from, written same time with only possible conflict arising from simultaneous writing simultaneous READ/WRITE operation non-semaphore location. Semaphores protected against such ambiguous situations used system program prevent conflicts non-semaphore segment dual-port RAM. devices have automatic power-down feature controlled dual-port select SEM, semaphore enable. pins control on-chip-power-down circuitry that permits port concerned into stand-by mode when selected. These conditions shown table where both high. Systems most suitable M67005 based upon multiple processors controllers typically very high-speed, software controlled software-intensive systems. These systems benefit from performance enhancement offered M67005 hardware semaphores, which provide lock-out mechanism without need complex programming. Software handshaking between processors offers maximum level system flexibility permitting shared resources allocated varying configurations. M67005 does semaphore flags control resources through hardware, thus allowing system designer total flexibility system architecture. advantage using sempahores rather than more usual methods hardware arbitration that neither processor ever incurs wait states. This prove considerable advantage very high speed systems. set, left processor established that right processor latch first, token using shared resource. left processor then either repeatedly query status semaphore, abandon request token perform another operation whilst occasionally attempting gain control token through test operation. Once right side relinquished token left side will able take control shared resource. semaphore flags active low. token requested writing zero semaphore latch, relinquished again when same side writes latch. eight semaphore flags located separate memory space from dual-port M67005. address space accessed placing input (which acts chip select semaphore flags) using other control pins (Address, R/W) normally used accessing standard static RAM. Each flags unique address accessed either side through address pins A0-A2. None other address pins effect when accessing semaphores. Only data used when writing semaphore. level written unused semaphore location, flag will zero that side other side (see table semaphore only modified side showing zero. Once written this location from same side, flag will both sides (unless request pending from other side) semaphore then written either side. effect side writing zero semaphore location locking other side reason semaphore logic interprocessor communication. thorough discussion this feature follows below). zero written semaphore location from locked-out side will stored semaphore request latch that side until semaphore relinquished side having control. When semaphore flag read value distributed data bits that flag reads data bits flag zero reads zeros. read value latched into output register side when sempahore select (SEM) output enable (OE) signals active. This prevents semaphore changing state middle read cycle result write cycle issued other side. Because this latch, repeated read semaphore flag test loop must cause either signal (SEM inactive, otherwise output will never change.
Semaphore Flags Work
semaphore logic eight latches independent dual-port RAM. These latches used pass flag token, from port other indicate that shared resource use. semaphores provides hardware context with "Token Passing Allocation" method assignment. This method uses state semaphore latch token indicating that shared resource use. left processor needs resource, requests token setting latch. processor then verifies that latch been reading latch been processor assumes control over shared resource. latch been
MATRA Rev. April.
M67005
semaphore must WRITE/READ sequence order ensure that system level conflict will occur. processor requests access shared resources attempting write zero semaphore location. semaphore already use, semaphore request latch will contain zero, semaphore flag will appear one, processor will detect this status subsequent read (see table example, assume processor writes zero left port free semaphore location. subsequent read, processor will verify that written succesfully that location will assume control over resource concerned. processor right side then attempts write zero same semaphore flag will fail, will verified subsequent read returning from semaphore location right side READ/WRITE sequence been used instead, system conflict problems could occurred during interval between read write cycles. must noted that failed semaphore request needs followed either repeated reads writing same location. simple logic diagram semaphore flag figure illustrates reason this quite clearly. semaphore request latches deed into semaphore flag. first latch send zero semaphore flag will force side semaphore flag other side high. This status will maintained until written same semaphore request latch. Should zero written other side's semaphore request latch meantime, semaphore flag will flip over this second side soon written first side's request latch. second side's flag will stay until semaphore request latch changed one. Thus, clearly, semaphore flag requested processor requesting longer requires access resource, entire system hang until written semaphore request latch concerned. Semaphore timing becomes critical when both sides request same token attempting write zero same time. Semaphore logic specially conceived resolve this problem. logic ensures that only side will receive token simultaneous requests made. first side make request will receive token where request arrive same time. Where they arrive same time, logic will assign token arbitrarily ports. should noted, however, that semaphores alone guarantee that access resource secure. with powerful programming technique, errors introduced semaphores misused misinterpreted. Code integrity utmost performance when semaphores being used instead slower, more restrictive hardware-intensive systems. Semaphore initialization automatic must therefore incorporated power initialization procedures. Since semaphore flag containing zero must reset one, initialization should write request flags from both sides ensure that they will available when required.
Using Semaphores Some Examples
Perhaps simplest application semaphores their resource markers M67005's dual-port RAM. necessary split into blocks which dedicated serving either left right port time. Semaphore used indicate which side controlling lower segment memory semaphore defined indicating upper segment memory. take control ressource, this case lower dual-port RAM, left port processor would then write zero into semaphore flag then read back. succesful taking token (reading back zero rather than one), left processor could then take control lower RAM. right processor attempts perform same function take control resource after left processor already done will read back response attempted write zero into semaphore this point software choose attempt gain control second segment writing then reading zero semaphore successful, will lock left processor. Once left side completed task will write semaphore then attempt access semaphore semaphore still occupied right side, left side abandon semaphore request perform other operations until able write then read zero semaphore right processor performs same operation with semaphore this protocol would then allow processes swap blocks dual-port between another. blocks have particular size, even variable size depending complexity software using semaphore flags. eight semaphores could used divide dual-port other shared resources into eight parts. Semaphores even assigned different meanings each side, rather than having common meaning described above example.
MATRA Rev. April.
M67005
Semaphores useful form arbitration systems such disk interfaces where must locked segment memory during data transfer operation, devices tolerate wait states. semaphores used, both device access assigned memory segments, cannot without need wait states, once devices have determined which memory area barred CPU. Semaphores also useful applications where memory WAIT state available both sides. Once semaphore handshake been performed, both processors access their assigned segments full speed. Figure Another application complex data structures. Block arbitration very important this case, since processor responsible building updating data structure whilst other processor reads interprets major error condition created interpreting processor reads incomplete data structure. Some sort arbitration between different processors therefore necessary. building processor request access block, locks then able enter block update data structure. Once update completed data structure released. This allows interpreting processor, return read complete data structure, thus ensuring consistent data stucture.
16-Bit Master/Slave Dual-Port Memory Systems.
Note
arbitration M67005 (SLAVE). BUSY-IN inhibits write M67005 SLAVE.
Figure M67005 Semaphore Logic.
MATRA Rev. April.
M67005
Truth Table
Table Contention Read/Write Control.
INPUTS
Note
OUTPUTS
I/O-I/O7
Hi-Z DATAOUT Hi-Z DATAIN DATAOUT DATAIN
MODE
Deselect Power Down Read Data Sema. Flag Outputs Disabled Write Into Sema. Flag Read Memory Write Memory Allowed
A12L A12R.
Table Arbitration Options.
INPUTS OPTION
Busy Logic Master Busy Logic Slave Interrupt Logic Semaphore Logic*
OUTPUTS
BUSY
Output signal Input Signal Hi-Z
Output signal
Inputs Signals Semaphore Flags test (Write read) operations.
Table Interrupt Flag.
LEFT PORT R/WL
Notes
RIGHT PORT INTL
L(3) H(2)
AOL-A12L
1FFF 1FFE
R/WR
AOR-A12R
1FFF 1FFE
INTR
L(2) H(3)
FUNCTION
Right INTR Flag Reset Right INTR Flag Left INTL Flag Reset Left INTL Flag
Assumes BUSYL BUSYR BUSYL then BUSYR then HIGH, LOW, DON'T CARE, CHANGE.
MATRA Rev. April.
M67005
Table Arbitration
LEFT PORT
RIGHT PORT
FLAGS BUSYL
A12L
A12R
A12R
A12L
BUSYR
FUNCTION
Contention Contention Contention Contention
ADDRESS ARBITRATION WITH BEFORE ADDRESS MATCH LV5R RV5L Same Same LV5R RV5L Same Same L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
ARBITRATION WITH ADDRESS MATCH BEFORE LL5R RL5L LW5R LW5R Notes A12R A12R A12R A12R LL5R RL5L LW5R LW5R A12L A12L A12L A12L L-Port Wins R-Port Wins Arbitration Resolved Arbitration Resolved
Flags Don't Care. DON'T CARE, LOW, HIGH. LV5R Left Address Valid before right address. RV5L Right Address Valid before left address. Same Left Right Addresses match within each other. LL5R Left before Right RL5L Right before left LW5R Left Right within each other.
Table Example Semaphore Procurement Sequence.
FUNCTION
Action Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Right Port Writes Semaphore Right Port Writes Semaphore Left Port Writes Semaphore Left Port Writes Semaphore Note
LEFT
RIGHT
STATUS
Semaphore free Left Port semaphore token change. Right side write access semaphore Right port obtains semaphore token change. Left port write access semaphore Left port obtains semaphore token Semaphore free Right port semaphore token Semaphore free Left Port semaphore token Semaphore free
This table denotes sequence events only semaphores M67005.
MATRA Rev. April.
M67005
Electrical Characteristics
Absolute Maximum Ratings
Supply voltage (VCC-GND) -0.3 Input output voltage applied (GND (VCC Storage temperature Notice Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device.This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extented periods affect reliability.
OPERATING RANGE
Military Automotive Industrial Commercial
OPERATING SUPPLY VOLTAGE
OPERATING TEMPERATURE
Parameters
67005-30 67005-35 67005-45 67005-55 67005-25 67005 Version UNIT VALUE PREVIEW
Parameter
Description
ICCSB
Standby supply current (Both ports level inputs) Standby supply current (Both ports CMOS level inputs) Operating supply current (Both ports active) Operating supply current (One port active port standby)
ICCSB1
ICCOP ICCOP1
Notes
SEMR SEML SEMR SEML Both ports active Maximum frequency Outputs open port active fMAX) Output open port stand-by CMOS Level Inputs SEMR SEML (*). Commercial only.
PARAMETER
II/O(5) VIL(6) VIH(6) VOL(7) VOH(7) IN(8) OUT(8) Notes
DESCRIPTION
Input/Output leakage current Input voltage Input high voltage Output voltage (I/O0-I/O15) Output high voltage Input capacitance Output capacitance
67005-25/30/35/45/55
UNIT
VALUE
Vcc, VIH, Vout Vcc. -0.3 pulse width min, Guaranteed tested.
MATRA Rev. April.
M67005
Data-Retention Mode
CMOS RAMs designed with battery backup mind. Data retention voltage supply current guaranteed over temperature. following rules insure data retention Chip select (CS) must held high during data retention within must kept between during power power down transitions. begin operation after reaches minimum operating voltage (4.5 volts).
Timing
PARAMETER TEST CONDITIONS
AUTO
UNIT
ICCDR1 ICCDR2 Notes
VCCDR VCCDR VCC, VCC. Read cycle time.
Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Figure Output Load. Output Reference Levels figures Output Load
Figure Output Load (for tHZ, tLZ, tWZ, tOW).
MATRA Rev. April.
M67005
Parameters
READ CYCLE SYMBOL SYMBOL TAVAVR TAVQV TELQV TBLQV TGLQV TAVQX TELQZ TEHQZ TSOP Notes tACS tABE tAOE tSOP (*). PARAMETER 67005 67005 67005 M67005 M67005
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT PREVIEW
Read cycle time Address access time Chip Select access time Byte enable access time Output enable access time Output hold from address change Output time Output high time Chip Select power time Chip disable power down time flag update pulse
Transition measured from high impedance voltage with load (figures This parameter guaranteed tested. access VIL, VIH. access semaphore VIH, VIL. Refer table symbol. symbol. Commercial only.
Timing Waveform Read Cycle Either Side
Timing Waveform Read Cycle Either Side
MATRA Rev. April.
M67005
Parameters
WRITE CYCLE PARAMETER SYMBOL SYMBOL TAVAVW TELWH TAVWH TAVWL TWLWH TWHAX TDVWH TGHQZ TWHDX TWLQZ TWHQX TSWRD TSPS Notes tSWRD tSPS Write cycle time Chip select write Address valid write Address Set-up Time Write Pulse Width Write Recovery Time Data Valid write Output high time Data hold time Write enable output high Output active from write flag write read time flag contention window 67005 67005 67005 M67005 M67005
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT PREVIEW
Transition measured from high impedance voltage with load (figures This parameter guaranteed tested. access VIL, VIH. acceess semaphore VIH, VIL. This condition must valid entire time. specification must device supplying write data under operating conditions. Although values will vary over voltage temperature, actual will always smaller than actual tOW. symbol. symbol. (*). Commercial only.
MATRA Rev. April.
M67005
Timing Waveform Write Cycle Controlled Timing
Timing Waveform Write Cycle Controlled Timing
Notes
must high during address transitions. write occurs during overlap (tSW tWP) R/W. measured from earlier R/W) going high write cycle. During this period, pins output state, input signals must applied. transition occurs simultaneously with after transition, outputs remain high impedance state. Transition measured from steady state with load (including scope jig).This parameter sampled tested. during controlled write cycle, write pulse width must larger (tWZ tDW) allow drivers turn data placed required tDW. high during controlled write cycle, this requirement does apply write pulse short specified tWP. access RAM, VIL. VIH.
MATRA Rev. April.
M67005
Parameters
SYMBOL PARAMETER 67005 67005 67005 M67005 M67005
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. UNIT BUSY TIMING 67005 only) (For Master tBAA tBDA tBAC tBDC tWDD tDDD tAPS tBDD BUSY Access time address BUSY Disable time address BUSY Access time Chip Select BUSY Disable time Chip Select Write Pulse data delay Write data valid read data delay Arbitration priority set-up time BUSY disable valid data PREVIEW Note Note Note Note Note
BUSY TIMING (For Slave 67005 only) tWDD tDDD Notes Write BUSY input Write hold after BUSY Write pulse data delay Write data valid read data delay
Port-to-port delay through cells from writting port reading port, refer "Timing Waveform Read with BUSY (For Master 67005 only)". ensure that earlier ports wins. tBDD calculated parameter greater tWDD tWPP (actual) tDDD tDWP (actual). ensure that write cycle inhibited during contention. ensure that write cycle completed after contention. Port-to-port delay through cells from writing port reading port, refer "Timing Waveforms Read with Port-to-port delay (For Slave 67005 only)". (*). Commercial only.
MATRA Rev. April.
M67005
Timing Waveform Read with BUSY (For Master 67005)
Notes
ensure that earlier port wins. Write cycle parameters should adhered ensure proper writing. Device continuously enabled both ports. reading port.
Timing Waveform Write with Port-to-Port (For Slave 67005 Only)
Notes
Assume BUSY writing port, reading port. Write cycle parameters should adhered ensure proper writing. Device continuously enabled both ports.
MATRA Rev. April.
M67005
Timing Waveform Write with BUSY (For Slave M67005)
Timing Waveform Contention Cycle Arbitration (For Master M67005 only)
MATRA Rev. April.
M67005
Timing Waveform Contention Cycle Address Valid Arbitration (For Master 67005 only) Left Address Valid First
Right Address Valid First
Note
MATRA Rev. April.
M67005
Waveform Interrupt Timing
Notes
timing same left right ports. Port either left right port. Port port opposite from Interrupt truth table. Timing depends which enable signal asserted last. Timing depends which enable signal de-asserted first.
Parameters
INTERRUPT TIMING SYMBOL tINS tINR Address set-up time Write recovery time Interrupt time Interrupt reset time 67005 PREVIEW 67005 67005 M67005 M67005
PARAMETER
UNIT
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
(*).Commercial only.
MATRA Rev. April.
M67005
Timing Waveform Semaphore Read after Write Timing, Either Side
Note
duration above timing (both write read cycle).
Timing Waveform Semaphore Contention
Notes
VIL, CSIR VIH, semaphore Flag released from both sides (reads ones from both sides) cycle start. Either side left side right, side right side left. This parameter measured from point where R/WA SEMA goes high until R/WB SEMB goes high. tSPS violated, semaphore will fall positively side other, there guaranted which side will obtain flag.
MATRA Rev. April.
M67005
Ordering Information
TEMPERATURE RANGE PACKAGE DEVICE 67005V SPEED FLOW
CERQUAD GRID ARRAY PLCC CQFP68 MQFPF68 Dice form Commercial Industrial Automotive Military Space -40° -40° -55° -55° +70°C +85°C +125°C +125°C +125°C
blank /883 P883 SB/SC SHXXX FHXXX EHXXX MHXXX LHXXX
standards Class PIND test 9000 level Special customer request Flight models (space) Engineering models (space) Mechanical parts (space) Life test parts (space) Tape reel Tape reel pack pack
Dual Port power Very power
Military Space Versions
following table gives package/consumption/access time/process flow available combinations
Temp. range Packages Consumption
Access Time (ns)
process 67005
flows
process 67005E
flows Space flows
product production call sales office availibility
information contained herein subject change without notice. responsibility assumed TEMIC using this publication and/or circuits described herein possible infringements patents other rights third parties which result from use.
MATRA Rev. April.

CMOS Dual Port M67005 very power CMOS dual port static organized

Top Searches for this datasheet

Other recent searches