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&!-),9 -)#/2/#/.42/,,%3 3%2)%3 (!2$7!2% -!.5!, &!-),9 -)#2/#


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&!-),9 -)#/2/#/.42/,,%3
3%2)%3 (!2$7!2% -!.5!,
&!-),9 -)#2/#/.42/,,%23 3ERIES (ARDWARE -ANUAL %DITION &EBRUARY &5*)435 ,)-)4%$
2IGHTS 2ESERVED #IRCUIT DIAGRAMS UTILIZING &UJITSU PRODUCTS INCLUDED MEANS ILLUSTRATING TYPICAL SEMICONDUCTOR APPLICATIONS #OMPLETE INFORMATION SUFFICIENT CONSTRUCTION PURPOSES NECESSARILY GIVEN INFORMATION CONTAINED THIS DOCUMENT BEEN CAREFULLY CHECKED BELIEVED RELIABLE (OWEVER &UJITSU ASSUMES RESPONSIBILITY INACCURACIES INFORMATION CONTAINED THIS DOCUMENT DOES CONVEY LICENSE UNDER COPYRIGHTS PATENT RIGHTS TRADEMARKS CLAIMED OWNED &UJITSU &UJITSU RESERVES RIGHT CHANGE PRODUCTS SPECIFICATIONS WITHOUT NOTICE PART THIS PUBLICATION COPIED REPRODUCED FORM MEANS TRANSFERRED THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT &UJITSU
02%&!#4HE SERIES MICROCONTROLLERS RANGE MICROCONTROLLER 4HEY GENERAL PURPOSE HIGH SPEED PRODUCTS &AMILY SERIES SINGLE CHIP MICROCONTROLLERS OPERATING VOLT AGES BITS CONVERTER 5!24 4HIS MANUAL COVERS FUNCTIONS OPERATIONS SERIES MICROCONTROLLERS 2EFER &AMILY 3OFTWARE -ANUAL INSTRUCTIONS
4ABLE #ONTENTS
'%.%2!, &EATURES 0RODUCT 3ERIES "LOCK $IAGRAM !SSIGNMENT $ESCRIPTION (ANDLING $EVICES (!2$7!2% #/.&)'52!4)/.
-EMORY 3PACE !RRANGEMENT $ATA -EMORY 3PACE )NTERNAL 2EGISTERS #LOCK #ONTROL "LOCK )NTERRUPT #ONTROLLER
2ESOURCES
0ORTS 4IMER 4IMER 0ULSE WIDTH #OUNT 4IMER 4IMER 5!24 3ERIAL %XTERNAL )NTERRUPT #ONTROLLERDRIVER 4IME BASE 4IMER 7ATCHDOG 4IMER 2ESET
/0%2!4)/. #LOCK 0ULSE 'ENERATOR 2ESET )NTERRUPT POWER #ONSUMPTION -ODES 3TATES 3LEEP 3TOP 2ESET ).3425#4)/.3 ,EGEND 4RANSFER )NSTRUCTIONS /PERATION )NSTRUCTIONS "RANCH )NSTRUCTIONS /THER )NSTRUCTIONS &AMILY )NSTRUCTION -!3+ /04)/.3
2ESET /PERATION 2ESET 3OURCES
!00%.$)8 !PPENDIX !PPENDIX 7RITING %02/-
4ABLES
4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4ABLE 4YPES &UNCTIONS 3ERIES -ICROCONTROLLERS $ESCRIPTION $ESCRIPTION %XTERNAL 4ABLE 2ESET )NTERRUPT 6ECTORS /PERATING -ODE POWER #ONSUMPTION -ODES 3ELECTION /SCILLATION 3TABILIZATION 4IME 3OURCES 2ESET ,IST 0ORT &UNCTIONS /PERATION -ODES 5!24 #LOCK $IVISION 2ATIO )NPUT #LOCK "AUD 2ATE 'ENERATOR 3ELECTION "AUD 2ATE 7HEN $EDICATED "AUD 2ATE 'ENERATOR 5SED )NTERRUPT 3OURCES )NTERRUPT 6ECTORS POWER #ONSUMPTION -ODE %ACH #LOCK -ODE 3TATE -ASK /PTIONS
&IGURES
"LOCK $IAGRAM !SSIGNMENT 0ITCH !SSIGNMENT -"06 -1&0 0ITCH #IRCUITS -EMORY 3PACE 3ERIES -ICROCONTROLLERS !RRANGEMENT $ATA -EMORY 3PACE !RRANGEMENT $ATA DURING %XECUTION )NSTRUCTION 3TRUCTURE 0ROCESSOR 3TATUS 2ULE 4RANSLATING 2EAL !DDRESSES 'ENERAL PURPOSE 2EGISTER !REA 2EGISTER "ANK #ONFIGURATION )NTERRUPT PROCESSING &LOWCHART 0ORTS 0ORT 0ORT 0ORT 4IMER /PERATION 0ULSE /UTPUT -EASUREMENT (IGH 0ULSE 7IDTH /PERATION .OISE #LEARING #IRCUIT 2$2& &LAG 4IMING /2&% &LAG 4IMING 2$2& &LAG 4IMING /2&% &LAG 4IMING 4$2% &LAG 4IMING -ODE 4RANSFER $ATA &ORMAT 3YSTEM #ONFIGURATION 7HEN -ODE 5SED #OMMUNICATION &LOWCHART 7HEN -ODE 5SED 3HIFT 3TART3TOP 4IMING )NPUT/UTPUT 3HIFT 4IMING #ONTROLLER$RIVER "LOCK $IAGRAM %XAMPLE 7AVEFORM #ORRESPONDING $ATA $ISPLAY %XAMPLE 7AVEFORM #ORRESPONDING $ATA $ISPLAY %XAMPLE 7AVEFORM #ORRESPONDING $ATA $ISPLAY #ONNECTION %XAMPLES 3UPPLY 0OWER $RIVING "UILT 6OLTAGE $IVIDING RESISTORS #LOCK 0ULSE 'ENERATOR /UTLINE 2ESET /PERATION 2ESET 6ECTOR 3TRUCTURE )NTERRUPT PROCESSING &LOWCHART
'%.%2!,
SERIES SINGLE CHIP COMPACT MICROCONTROLLER USING CORE WHICH OPERATE HIGH SPEEDS VOLTAGES 4HEY CONTAIN RESOURCES SUCH TIMERS 5!24 SERIAL INTERFACES EXTERNAL INTERRUPTS INCLUDING PIXEL CONTROLLERDRIVER THEY BEST SUITED PANELS
&EATURES
(IGH SPEED PROCESSING EVEN VOLTAGES -INIMUM INSTRUCTION EXECUTION TIME CORE )NSTRUCTION SYSTEM MOST SUITED CONTROLLER -ULTIPLICATION DIVISION INSTRUCTIONS ARITHMETIC OPERATION )NSTRUCTION TEST BRANCH INSTRUCTION MANIPULATION INSTRUCTION CONTROLLERDRIVER -AXIMUM SEGMENT OUTPUTS COMMON OUTPUTS "UILT DRIVER SPLIT RESISTOR 4HREE CHANNEL TIMER UNIT TIMER USABLE BOTH RELOAD TIMER TIMER PULSE WIDTH COUNT TIMER USABLE BOTH RELOAD TIMER TIME BASED COUNTER SERIAL INTERFACES SYNCHRONOUS SERIAL INTERFACE TRANSFER DIRECTION SELECTED COMMUNICATE WITH VARIOUS EQUIPMENT 5!24 TRANSFERS POSSIBLE %XTERNAL INTERRUPT INPUT CHANNELS CHANNELS USED CLEAR POWER CONSUMPTION MODES EDGE DETECTION FUNCTION PROVIDED POWER CONSUMPTION MODES 3TOP MODE /SCILLATION STOPS MINIMIZE CURRENT CONSUMPTION 3LEEP MODE STOPS REDUCE CURRENT CONSUMPTION ABOUT
NORMAL
'%.%2!,
0RODUCT 3ERIES
4ABLE LISTS TYPES FUNCTIONS SERIES MICROCONTROLLERS 4ABLE 4YPES &UNCTIONS 3ERIES -ICROCONTROLLERS
-ODEL NAME #LASSIFICATION TIMER PROGRAMMABLE BITS )NTERNAL 02/- WRITABLE GENERAL PURPOSE WRITERS BITS BITS BYTES BITS ALSO USED SEGUMENT
USED RESOURCES ALSO USED EXTERNAL INTERRUPT -AXIMUM -"06 0IGGYBACK%VALUATION DEVELOPMENT PRODUCT BITS )NTERNAL BITS
-ASS PRODUCED PRODUCT -ASK PRODUCT BITS )NTERNAL BITS .UMBER BASIC INSTRUCTIONS )NSTRUCTION LENGTH )NSTRUCTION LENGTH $ATA LENGTH -INIMUM INSTRUCTION EXECUTION TIME )NTERRUPT PROCESSING TIME )NPUT PORT OPEN DRAIN )NPUT PORT OPEN DRAIN PORT #-/3 )NPUT PORT 4OTAL BITS )NTERNAL
CAPACITY CAPACITY
FUNCTION
0ORT
TIMER
RELOAD TIMER OPERATION TOGGLE OUTPUT POSSIBLE RESOLUTION OPERATION /PERATION CLOCK PULSE WIDTH COUNT TIMER OUTPUT RELOAD TIMER OPERATION PULSE WIDTH MEASUREMENT CONTINUOUS MEASUREMENT (IGH WIDTH MEASUREMENT CYCLE MEASUREMENT /PERATION CLOCK LENGTH SELECTABLE FROM LEAST SIGNIFICANT FIRST MOST SIGNIFICANT FIRST TRANSFER CLOCK EXTERNAL TRANSFERS POSSIBLE INTERNAL BAUD RATE GENERATOR INTERNAL #OMMON OUTPUT 3EGMENT OUTPUT /PERATION MODE CONTROLLER DISPLAY CAPACITY DRIVER SPLIT RESISTOR BIAS DUTY BIAS DUTY BIAS DUTY BITS BUILT EXTERNAL RESISTOR SELECTABLE
0ULSE WIDTH COUNT TIMER
3ERIAL 5!24
CONTROLLER DRIVER
%XTERNAL INTERRUPT 3TANDBY MODE 0ACKAGE /PERATION VOLTAGE
EDGE SELECTABLE SERVING PULSE WIDTH COUNT TIMER INPUT 3LEEP MODE STOP MODE
-"-#! PAKAGE
%02/-
-ASK OPTION
6ARIES ACCORDING CONDITIONS SUCH FREQUENCY
/PERATION LESS ASSURED EACH PRODUCT
'%.%2!,
"LOCK $IAGRAM
)NTERNAL -AIN OSCILLATOR CIRCUIT
4IME BASE TIMER
#LOCK CONTROL
TIMER
007-
%XTERNAL INTERRUPT 2ESET CIRCUIT PULSE WIDTH COUNT TIMER .OISE CLEAR 007#).4
0ORT OPEN DRAIN PORT
0ORT
SERIAL
03#+
0).4/ 0ORT
%XTERNAL INTERRUPT 5!24 )NPUT PORT #-/3 PORT
BITS
OPEN DRAIN PORT
03%' 03%'
0ORT
03%' 03%'
BITS CONTROLLER DRIVER
/THER PINS
"LOCK $IAGRAM
'%.%2!,
!SSIGNMENT
03#+ 007#).4 0070 0).4
6IEW
!SSIGNMENT 0ITCH
'%.%2!,
03#+ 007#).4 0070
03%' 03%' 03%' 03%' 03%' 03%' 03%' 03%' 03%' 03%'
6)%7
!SSIGNMENT -"06 -1&0 0ITCH
ASSIGNMENT PACKAGE -"06 ONLY
NAME NAME NAME NAME
CONNECTION +EEP OPEN
'%.%2!,
$ESCRIPTION
4ABLE LISTS FUNCTIONS &IGURE SHOWS INPUTOUTPUT CIRCUITS 4ABLE $ESCRIPTION
NAME #IRCUIT TYPE &UNCTION
#LOCK OSCILLATOR PINS /PERATION MODE SELECT PINS 4HESE PINS CONNECTED DIRECTLY 2ESET 4HIS CONSISTS OPEN DRAIN OUTPUT WITH PULL RESISTOR HYSTERESIS INPUT LEVEL FROM THIS VOLTAGE THIS PORT GENERATES 2%3%4 CONDITION CHANNEL OPEN DRAIN TYPE GENERAL PURPOSE PORTS !LSO SERVE ,#$# CONTROLLER SEGMENT OUTPUTS 3WITCHING BETWEEN PORT OUTPUT SEGMENT OUTPUT PERFORMED MASK OPTION EVERY BITS CHANNEL OPEN DRAIN TYPE GENERAL PURPOSE PORTS !LSO SERVE ,#$# CONTROLLER SEGMENT OUTPUTS 3WITCHING BETWEEN PORT OUTPUT SEGMENT OUTPUT PERFORMED MASK OPTION EVERY BITS CHANNEL OPEN DRAIN TYPE GENERAL PURPOSE PORTS PULL RESISTOR OPTION PROVIDED 'ENERAL PURPOSE INPUT PORT !LSO SERVES EXTERNAL INTERRUPT INPUT INPUT HYSTERESIS TYPE RESISTOR OPTION PROVIDED 'ENERAL PURPOSE INPUT PORTS INPUT HYSTERESIS TYPE RESISTOR OPTION PROVIDED 'ENERAL PURPOSE PORTS PULL RESISTOR OPTION PROVIDED 'ENERAL PURPOSE PORT 3ERVES TIMER TOGGLE OUTPUT PULL RESISTOR OPTION PROVIDED 'ENERAL PURPOSE PORT !LSO SERVES PULSE WIDTH COUNT TIMER INPUT EXTERNAL INTERRUPT INPUT INPUTS HYSTERESIS TYPE PULL RESISTOR OPTION PROVIDED 'ENERAL PURPOSE PORT !LSO SERVES SERIAL 5!24 DATA INPUT INPUT HYSTERESIS TYPE PULL RESISTOR OPTION PROVIDED 'ENERAL PURPOSE PORT !LSO SERVES SERIAL 5!24 DATA OUTPUT PULL RESISTOR OPTION PROVIDED 'ENERAL PURPOSE PORT !LSO SERVES SERIAL 5!24 CLOCK INPUTOUTPUT INPUT TERESIS TYPE PULL RESISTOR OPTION PROVIDED ,#$# CONTROLLER SEGMENT OUTPUT #ONTINUE
03%' 03%' 03%' 03%' 0).4
0070 07#).4
03#+
'%.%2!,
4ABLE $ESCRIPTION #ONTINUED
NAME #IRCUIT TYPE &UNCTION ,#$# CONTROLLER COMMON OUTPUT DRIVER POWER SUPPLY 0OWER PINS 0OWER PINS
4ABLE $ESCRIPTION %XTERNAL %XTERNAL %02/- PINS -"06
NAME (IGH LEVEL OUTPUT &UNCTION
ADDRESS OUTPUT
DATA INPUT POWER SUPPLY
DATA INPUT
OUTPUT ENABLE (IGH LEVEL OUTPUT STANDBY MODE ADDRESS OUTPUT OUTPUT ENABLE LEVEL ALWAYS OUTPUT ADDRESS OUTPUT ADDRESS OUTPUT ADDRESS OUTPUT %02/- POWER SUPPLY INTERNAL CONNECTION +EEP OPEN
'%.%2!,
#LASSIFICATION
#IRCUIT
2EMARKS #RYSTAL OSCILLATOR &EEDBACK RESISTOR !BOUT
3TANDBY CONTROL SIGNAL
#-/3 INPUT
/UTPUT PULL RESISTOR !BOUT
(YSTERESIS INPUT
OPEN DRAIN OUTPUT #-/3 INPUT
SEGMENTOUTPUT OPTIONAL
#-/3 OUTPUT #-/3 INPUT (YSTERESIS INPUT 2ESOURCE INPUT
PULL RESISTOR OPTIONAL
#IRCUITS #ONTINUE
'%.%2!,
#LASSIFICATION
#IRCUIT
2EMARKS OPEN DRAIN OUTPUT
#-/3 INPUT
PULL RESISTOR OPTIONAL 5NAVAILABLE PRODUCT ,#$# OUTPUT
(YSTERESIS INPUT
PULL RESISTOR OPTIONAL 5NAVAILABLE PRODUCT
#IRCUITS #ONTINUED
'%.%2!,
(ANDLING $EVICES
0REVENTING LATCH #-/3 LATCH OCCUR VOLTAGE HIGHER THAN LOWER THAN APPLIED INPUT OUTPUT PINS OTHER THAN THOSE WHICH RESISTANT MIDDLE HIGH VOLTAGE VOLTAGE EXCEEDING RATED VALUE APPLIED BETWEEN 7HEN LATCH OCCURS SUPPLY CURRENT INCREASES RAPIDLY SOMETIMES RESULTING OVERHEATING DESTRUC TION 4HEREFORE VOLTAGE EXCEEDING MAXIMUM RATINGS SHOULD USED (ANDLING UNUSED INPUT PINS ,EAVING UNUSED INPUT PINS OPEN CAUSE MALFUNCTION 4HEREFORE THESE PINS SHOULD PULL PULL DOWN 6ARIATIONS SUPPLY VOLTAGE !LTHOUGH SPECIFIED SUPPLY VOLTAGE OPERATING RANGE ASSURED SUDDEN CHANGE SUPPLY VOLTAGE WITHIN SPECIFIED RANGE CAUSE MALFUNCTION 4HEREFORE VOLTAGE SUPPLY SHOULD KEPT CONSTANT POSSIBLE RECOMMENDABLE THAT RIPPLE VALUE SUPPLY FREQUENCY SHOULD LESS THAN TYPICAL VALUE THAT COEFFICIENT EXCESSIVE VARIATION SHOULD INSTANTANEOUS CHANGES SUCH SWITCHING TIME POWER SUPPLY 0RECAUTIONS EXTERNAL CLOCKS TAKES SOME TIME OSCILLATION STABILIZE AFTER CHANGING MODE FROM POWER RESET OPTIONAL STOP #ONSEQUENTLY EXTERNAL CLOCK MUST INPUT 2ECOMMENDED SCREENING CONDITIONS /402/- PRODUCT SHOULD SCREENED HIGH TEMPERATURE AGING BEFORE MOUNTING 6ERIFY PROGRAM
(IGH TEMPERATURE AGING
2EAD
-OUNT PROGRAMMING TEST CANNOT PERFORMED BITS PREPROGRAMMED /402/- PRODUCT CHARACTERISTICS #ONSEQUENTLY PROGRAMMING YIELDING CANNOT ENSURED
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
(!2$7!2% #/.&)'52!4)/.
4HIS CHAPTER DESCRIBES EACH BLOCK HARDWARE
4HIS SECTION DESCRIBES MEMORY SPACE REGISTER COMPOSING HARDWARE
-EMORY 3PACE
MEMORY SPACE +BYTES DATA PROGRAM AREAS LOCATED THIS SPACE AREA NEAR LOWEST ADDRESS DATA AREA IMMEDIATELY ABOVE DATA AREA DIVIDED INTO ISTER STACK DIRECT ADDRESS AREAS ACCORDING APPLICATIONS PROGRAM AREA LOCATED NEAR HIGHEST ADDRESS TABLES INTERRUPT RESET VECTORS VECTOR CALL INSTRUCTIONS HIGHEST ADDRESS THIS AREA &IGURE SHOWS STRUCTURE MEMORY SPACE SERIES MICROCONTROLLERS
2ESERVE 2!2EGISTER 2EGISTER 2EGISTER 2EGISTER -"06
6ACANT 6ACANT 6ACANT
6ACANT
2/&&&&( &&&&( 2/0ROGRAMMABLE 2/%XTERNAL
&&&&(
&&&&(
-EMORY 3PACE 3ERIES -ICROCONTROLLERS
(!2$7!2% #/.&)'52!4)/.
AREA 4HIS AREA WHERE VARIOUS RESOURCES SUCH CONTROL DATA REGISTERS LOCATED MEMORY AREA GIVEN !00%.$)8 AREA 4HIS AREA WHERE STATIC LOCATED !DDRESSES FROM -"06 ALSO USED GENERAL PURPOSE REGISTER AREA AREA 4HIS AREA WHERE INTERNAL LOCATED !DDRESSES FROM &&#( &&&&( ALSO USED TABLE INTERRUPT RESET VECTOR CALL INSTRUC TIONS 4ABLE SHOWS CORRESPONDENCE BETWEEN EACH INTERRUPT NUMBER RESET TABLE ADDRESSES REFERENCED SERIES MICROCONTROLLERS 4ABLE 4ABLE 2ESET )NTERRUPT 6ECTORS
4ABLE ADDRESS 5PPER DATA #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 &&#( &&#( &&#( &&#( &&#( &&#!( &&##( &&#%( ,OWER DATA &&#( &&#( &&#( &&#( &&#( &&#"( &&#$( &&#&( )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT )NTERRUPT 2ESET MODE 2ESET VECTOR &&&%( 4ABLE ADDRESS 5PPER DATA &&%( &&%( &&%( &&%!( &&%#( &&%%( &&&( &&&( &&&( &&&( &&&( &&&!( ,OWER DATA &&%( &&%( &&%( &&%"( &&%$( &&%&( &&&( &&&( &&&( &&&( &&&( &&&"( &&&$( &&&&(
.OTE &&&#( ALREADY RESERVED 7HEN USING &&&$( RESET MODE WRITE
(!2$7!2% #/.&)'52!4)/.
!RRANGEMENT $ATA -EMORY 3PACE
7HEN SERIES MICROCONTROLLERS HANDLE DATA DATA WRITTEN LOWER ADDRESS TREATED UPPER DATA THAT WRITTEN NEXT ADDRESS TREATED LOWER DATA SHOWN &IGURE -EMORY !"#&( !"#%( !"#$( !"##(
-/67 !"#$(
"EFORE EXECUTION
!FTER EXECUTION
-EMORY !"#&( !"#%( !"#$( !"##(
!RRANGEMENT $ATA -EMORY 3PACE 4HIS SAME WHEN BITS SPECIFIED OPERAND DURING EXECUTION INSTRUCTION "ITS CLOSER CODE TREATED UPPER BYTE THOSE NEXT TREATED LOWER BYTE 4HIS ALSO SAME WHEN MEMORY ADDRESS IMMEDIATE DATA SPECIFIED OPERAND ;%XAMPLE= %XTENDED ADDRESS IMMEDIATE DATA !SSEMBLE 8888( 8888( %XTENDED ADDRESS 8888( IMMEDIATE DATA 8888( !RRANGEMENT $ATA DURING %XECUTION )NSTRUCTION $ATA SAVED STACK INTERRUPT ALSO TREATED SAME MANNER
(!2$7!2% #/.&)'52!4)/.
)NTERNAL 2EGISTERS
SERIES MICROCONTROLLERS HAVE DEDICATED REGISTERS GENERAL PURPOSE REGISTERS MEMORY TYPES DEDICATED ISTERS FOLLOWS 0ROGRAM COUNTER !CCUMULATOR LENGTH REGISTER INDICATING LOCATION WHERE INSTRUCTIONS STORED LENGTH REGISTER STORING RESULTS ERATIONS TEMPORARILY LOWER BYTE USED EXECUTE DATA PROCESSING STRUCTIONS LENGTH REGISTER WHERE OPERATIONS PERFORMED BETWEEN THIS REGISTER ACCUMULATOR LOWER BYTE USED EXECUTE DATA PROCESSING INSTRUCTIONS LENGTH REGISTER INDEX MODIFICATION LENGTH REGISTER INDICATING MEMORY ADDRESS LENGTH REGISTER INDICATING STACK AREA LENGTH REGISTER WHERE REGISTER POINT CONDITION CODES STORED
4EMPORARY ACCUMULATOR
)NDEX REGISTER %XTRA POINTER 3TACK POINTER 0ROCESSOR STATUS BITS
0ROGRAM COUNTER !CCUMULATOR 4EMPORARY ACCUMULATOR )NDEX REGISTER %XTRA POINTER 3TACK POINTER 0ROCESSOR STATUS
(!2$7!2% #/.&)'52!4)/.
BITS PROCESSOR STATUS DIVIDED INTO UPPER BITS REGISTER BANK POINTER LOWER BITS CONDITION CODE REGISTER &IGURE
6ACANT 6ACANT 6ACANT
3TRUCTURE 0ROCESSOR 3TATUS INDICATES ADDRESS CURRENT REGISTER BANK RELATIONSHIP BETWEEN CONTENTS REAL ADDRESSES SHOWN &IGURE
3OURCE ADDRESS ,OWER BITS CODE
2ULE 4RANSLATING 2EAL !DDRESSES 'ENERAL PURPOSE 2EGISTER !REA BITS INDICATING RESULTS OPERATIONS TRANSFER DATA TENTS BITS CONTROLLING OPERATION WHEN INTERRUPT OCCURS FLAG FLAG WHEN CARRY BORROW INTO GENERATED RESULT OPERATIONS CLEARED OTHER CASES 4HIS FLAG USED DECIMAL CORRECTION INSTRUCTIONS INTERRUPT ENABLED WHEN THIS FLAG DISABLED WHEN FLAG RESET
FLAG
4HESE BITS INDICATE LEVEL CURRENTLY ENABLED INTER RUPT EXECUTES INTERRUPT PROCESSING ONLY WHEN INTERRUPT WITH VALUE SMALLER THAN VALUE INDICATED THIS REQUESTED FLAG )NTERRUPT LEVEL INTERRUPT (IGH (IGH
FLAG WHEN MOST SIGNIFICANT RESULT OPERATIONS CLEARED WHEN
(!2$7!2% #/.&)'52!4)/.
FLAG FLAG
FLAG WHEN RESULT OPERATIONS CLEARED OTHER CASES FLAG WHEN COMPLEMENT OVERFLOW OCCURS RESULT OPERATIONS RESET WHEN OVERFLOW DOES FLAG WHEN CARRY BORROW GENERATED RESULT OPERATIONS CLEARED OTHER CASES 7HEN SHIFT INSTRUCTION EXECUTED VALUE FLAG SHIFTED
FLAG
'ENERAL PURPOSE REGISTER LENGTH REGISTER WHERE DATE STORED GENERAL PURPOSE REGISTERS PROVIDED REGISTERBANKS MEMORY STORING DATA %IGHT REGISTERS PROVIDED BANK BANKS USED BANKS -"06 REGISTER BANK POINTER INDICATES CURRENTLY USED BANK .OTE REGISTER BANKS FOLLOWS DEPEND AREA BANKS BANKS BANKS -"06 BANKS !DDRESS
BANKS
-EMORY AREA 2EGISTER "ANK #ONFIGURATION
(!2$7!2% #/.&)'52!4)/.
#LOCK #ONTROL "LOCK
4HIS BLOCK CONTROLS STANDBY OPERATION SOFTWARE RESET -ACHINE CLOCK CONTROL BLOCK DIAGRAM -ACHINE CLOCK CONTROL SECTION
STATE 3TOP 3LEEP
#LOCK OSCILLATOR
#LOCK CONTROL
OPERATION CLOCK 2ESOURCE OPERATION CLOCK
&ROM TIME BASE TIMER
3ELECTOR
3TOP RELEASE SIGNAL
/PTION 2ESET CONTROL SECTION 0OWER RESET 7ATCHDOG TIMER RESET %XTERNAL RESET 3OFTWARE RESET )NTERNAL RESET SIGNAL 2ESET CONTROL
2EGISTER LIST
BITS !DDRESS 34"# 3TANBY CONTROL REGISTER
(!2$7!2% #/.&)'52!4)/.
$ESCRIPTION REGISTERS DETAIL EACH REGISTER DESCRIBED BELOW
!DDRESS 34"#
3TANDBY CONROL REGISTER 34"#
!DDRESS )NITIAL VALUE 8888"
;"IT 3TOP 4HIS USED SPECIFY SWITCHING STOP MODE OPERATION 3TOP MODE
4HIS CLEARED RESET STOP CANCELLATION ALWAYS READ WHEN THIS READ ;"IT 3LEEP 4HIS USED SPECIFY SWITCHING SLEEP MODE OPERATION 3LEEP MODE
4HIS CLEARED RESET SLEEP CANCELLATION STOP CANCELLATION ALWAYS READ WHEN THIS READ ;"IT STATE SPECIFYING 4HIS USED SPECIFY EXTERNAL STATE STOP MODE (OLDS STATE LEVEL IMMEDIATELY BEFORE STOP MODE (IGH IMPEDANCE
4HIS CLEARED RESET ;"IT 3OFTWARE RESET 4HIS USED SPECIFY SOFTWARE RESET 'ENERATES CYCLE RESET SIGNAL OPERATION
ALWAYS READ WHEN THIS READ
(!2$7!2% #/.&)'52!4)/.
$ESCRIPTION OPERATION POWER CONSUMPTION MODE 4HIS CHIP THREE OPERATION MODES SHOWN TABLE BELOW SLEEP MODE STOP MODE REDUCE POWER CONSUMPTION SYSTEM CLOCK SELECTED FOUR ACCORDING SYSTEM CONDITION MINIMIZE POWER CONSUMPTION 4ABLE /PERATING -ODE POWER #ONSUMPTION -ODES
%ACH OPERATING CLOCK PULSE CLOCK 3TOPS
4IME BASE TIMER
/PERATION MODE 3,%%0 34/0
#LOCK PULSE /SCILLATES 3TOPS
%ACH RESOURCE 3TOPS
7AKE SOURCE EACH MODE 6ARIOUS INTERRUPT REQUESTS %XTERNAL INTERRUPT
3TOPS
3,%%0 MODE STOPS ONLY OPERATING CLOCK PULSE OTHER OPERATIONS CONTINUED 34/0 MODE STOPS OSCILLATION $ATA HELD WITH LOWEST POWER CONSUMPTION THIS MODE 3,%%0 MODE 3WITCHING 3LEEP MODE 7RITING 34"# REGISTER SWITCHES MODE 3,%%0 MODE 3,%%0 MODE MODE STOP CLOCK PULSE OPERATING ONLY STOPS RESOURCES CONTINUE OPERATE INTERRUPT REQUESTED WHEN WRITTEN INSTRUC TION EXECUTION CONTINUES WITHOUT SWITCHING 3,%%0 MODE 3,%%0 MODE CONTENTS REGISTERS IMMEDIATELY BEFORE ENTERING 3,%%0 MODE HELD #ANCELING 3,%%0 MODE 3,%%0 MODE CANCELED INPUTTING RESET SIGNAL REQUEST INTERRUPT 7HEN RESET SIGNAL INPUT DURING 3,%%0 MODE SWITCHED RESET STATE 3,%%0 MODE CANCELED 7HEN INTERRUPT LEVEL HIGHER THAN REQUESTED FROM RESOURCE DURING 3,%%0 MODE 3,%%0 MODE CANCELED 7HEN FLAG ENABLE AFTER CANCELING EXECUTES INTERRUPT PROCESSING LIKE ORDINARY INTERRUPT 7HEN THEY ABLED STARTS PROCESSING NEXT INSTRUCTION GIVEN BEFORE TERING 3,%%0 MODE
(!2$7!2% #/.&)'52!4)/.
34/0 MODE 3WITCHING 34/0 MODE 7RITING 34"# REGISTER SWITCHES MODE 34/0 MODE 34/0 MODE STOPS CLOCK OSCILLATION RESOURCES STOP INPUTOUTPUT PINS OUTPUT PINS 34/0 MODE TROLLED 34"# REGISTER THAT THEY HELD STATE IMMEDIATELY BEFORE ENTERING 34/0 MODE THAT THEY ENTER HIGH IMPEDANCE STATE INTERRUPT REQUESTED WHEN WRITTEN INSTRUC TION EXECUTION CONTINUES WITHOUT SWITCHING 34/0 MODE 34/0 MODE CONTENTS REGISTERS IMMEDIATELY FORE ENTERING 34/0 MODE HELD #ANCELING 34/0 MODE 34/0 MODE CANCELED EITHER INPUTTING RESET SIGNAL REQUESTING INTERRUPT 7HEN RESET SIGNAL INPUT DURING 34/0 MODE SWITCHED RESET STATE 34/0 MODE CANCELED 7HEN INTERRUPT HIGHER THAN LEVEL REQUESTED FROM EXTERNAL INTERRUPT CIRCUIT DURING 34/0 MODE 34/0 MODE CANCELED 7HEN FLAG ENABLED AFTER CANCELING CUTES INTERRUPT PROCESSING LIKE ORDINARY INTERRUPT 7HEN THEY DISABLED STARTS PROCESSING NEXT INSTRUCTION GIVEN BEFORE ENTERING 34/0 MODE OSCILLATION STABILIZATION TIME SELECTED FROM TYPES 4ABLE OPTIONS 34/0 MODE CANCELED INPUTTING RESET SIGNAL SWITCHED OSCILLATION STABILIZATION STATE 4HEREFORE RESET QUENCE EXECUTED UNLESS OSCILLATION STABILIZATION TIME ELAPSED OSCILLATION STABILIZATION TIME CORRESPONDS OPTION ALLY SELECTED OSCILLATION STABILIZATION TIME MAIN CLOCK (OWEVER WHEN 0OWER RESET UNAVAILABLE SELECTED MASK OPTION SWITCHED OSCILLATION STABILIZATION STATE EVEN 34/0 MODE CANCELED INPUTTING RESET SIGNAL 4ABLE 3ELECTION /SCILLATION 3TABILIZATION 4IME /SCILLATION STABILIZATION TIME !BOUT !BOUT /SCILLATION STABILIZATION TIME !BOUT !BOUT 2EMARKS CRYSTAL OSCILLATOR CERAMIC OSCILLATOR
(!2$7!2% #/.&)'52!4)/.
3TATE TRANSITION DIAGRAM
3,%%0 #LOCK OSCILLATES /SCILLATION STABILIZATION WAITING
34/0 #LOCK STOPS
#LOCK OSCILLATES
0OWER
7HEN POWER RESET AVAILABLE SELECTED 7HEN POWER RESET UNAVAILABLE SELECTED !FTER OSCILLATION STABILIZING %XTERNAL RESET WHEN POWER RESET UNAVAILABLE SELECTED %XTERNAL RESET INTERRUPT WHEN POWER RESET AVAILABLE SELECTED %XTERNAL RESET INTERRUPT
(!2$7!2% #/.&)'52!4)/.
2ESET 4HERE FOUR TYPES RESET DEPENDING SOURCE SHOWN 4ABLE 4ABLE 3OURCES 2ESET 2ESET NAME %XTERNAL RESET 3OFTWARE RESET 7ATCHDOG RESET 0OWER RESET $ESCRIPTION 7HEN SETTING EXTERNAL RESET 7HEN WRITING 34"# 7HEN WATCHDOG TIMER OVERFLOWS 7HEN TURNING POWER
7HEN POWER RESET RESET DURING STOP STATE USED OSCILLA TION STABILIZATION TIME NEEDED AFTER OSCILLATOR STARTS OPERATING TIME BASE TIMER CONTROLS THIS STABILIZATION TIME #ONSEQUENTLY OPERATION DOES START IMMEDIATELY EVEN AFTER CANCELING RESET (OWEVER 0OWER RESET UNAVAILABLE SELECTED MASK OPTION OSCILLATION STABILIZATION TIME REQUIRED STATE AFTER EXTERNAL PINS HAVE BEEN RELEASED FROM RESET .OTE LONGER TIME THAN OPTIONALLY SPECIFIED OSCILLATION STABILIZATION TIME SHOULD ALLOWED RESET POWER 0OWER RESET UNAVAILABLE PRODUCTS OTHER CASES TIME BASED RESET TIMING GIVEN 3%2)%3 $!4! 3(%%4
(!2$7!2% #/.&)'52!4)/.
)NTERRUPT #ONTROLLER
INTERRUPT CONTROLLER FAMILY LOCATED BETWEEN EACH RESOURCE 4HIS CONTROLLER RECEIVES INTERRUPT REQUESTS FROM SOURCES ASSIGNS PRIORITY THEM 7HEN INTERRUPT CONTROLLER TRANSFERS PRIORITY ALSO DECIDES PRIORITY SAME LEVEL INTERRUPTS "LOCK DIAGRAM
4EST REGISTER !DDRESS DECORDER
2ESOURCE
,EVEL
2ESOURCE
,EVEL
,EVEL DECIDING BLOCK
3AME LEVEL PRIORITY DECID BLOCK
)NTERRUPT GENERATION BLOCK
2ESOURCE
,EVEL
2EGISTER LIST )NTERRUPT CONTROLLER CONSISTS INTERRUPT LEVEL REGISTERS INTERRUPT TEST REGISTER
BITS !DDRESS !DDRESS !DDRESS !DDRESS )NTERRUPT LEVEL REGISTER )NTERRUPT LEVEL REGISTER )NTERRUPT LEVEL REGISTER )NTERRUPT TEST REGISTER
(!2$7!2% #/.&)'52!4)/.
$ESCRIPTION REGISTERS DETAILS EACH REGISTER DESCRIBED BELOW
!DDRESS !DDRESS !DDRESS !DDRESS
)NTERRUPT LEVEL REGISTER ),2X )NTERRUPT ,EVEL 2EGISTER
!DDRESS !DDRESS !DDRESS
)NITIAL VALUE
),2X SETS INTERRUPT LEVEL EACH RESOURCE DIGITS CENTER EACH CORRESPOND INTERRUPT NUMBERS ;%XAMPLE=
)NTERRUPT NUMBER 4ABLE ADDRESS 5PPER &&&! ,OWER &&&" HARDWARE MANUAL
)NTERRUPT CONTROL MODULE
)NTERRUPT REQUESTS FROM RESOURCES
;"ITS =;"ITS =;"ITS =;"ITS )NTERRUPT LEVEL SETTING 2EQUIRED INTERRUPT LEVEL .ONE
7HEN INTERRUPT REQUESTED FROM RESOURCE INTERRUPT CONTROLLER TRANSFERS INTERRUPT LEVEL BASED VALUE BITS ),2X CORRESPONDING INTERRUPT !DDRESS !DDRESS !DDRESS !DDRESS )NTERRUPT TEST REGISTER
!DDRESS )NITIAL VALUE 888888"
USED TESTING ACCESS
(!2$7!2% #/.&)'52!4)/.
$ESCRIPTION OPERATION FUNCTIONS INTERRUPT CONTROLLERS DESCRIBED BELOW )NTERRUPT FUNCTIONS SERIES MICROCONTROLLERS HAVE INPUTS INTERRUPT REQUESTS FROM RESOURCES INTERRUPT LEVEL REGISTERS CORRESPOND EACH INPUT 7HEN INTERRUPT REQUESTED FROM RESOURCE INTER RUPT CONTROLLER RECEIVES TRANSFERS CONTENTS CORRESPONDING LEVEL REGISTER INTERRUPT DEVICE PROCESSED FOLLOWS INTERRUPT SOURCE GENERATED INSIDE RESOURCE INTERRUPT ENABLED AFTER REFERRING INTERRUPT ENABLE SIDE RESOURCE INTERRUPT REQUEST OUTPUT FROM RESOURCE INTERRUPT CONTROLLER !FTER RECEIVING THIS INTERRUPT REQUEST INTERRUPT CONTROLLER DETER MINES PRIORITY SIMULTANEOUSLY REQUESTED INTERRUPTS THEN TRANSFERS INTERRUPT LEVEL APPLICABLE INTERRUPT COMPARES INTERRUPT LEVEL REQUESTED FROM INTERRUPT CONTROLLER WITH PROCESSOR STATUS REGISTER RESULT COMPARISON INTERRUPT LEVEL PRIORITY OVER CURRENT INTERRUPT PROCESSING LEVEL CONTENTS FLAG SAME PROCESSOR STATUS REGISTER CHECKED RESULT CHECK STEP FLAG ENABLED INTER RUPT CONTENTS REQUIRED LEVEL SOON CURRENTLY EXECUTING INSTRUCTION TERMINATED PERFORMS INTERRUPT PROCESSING TRANSFERS CONTROL INTERRUPT PROC ESSING ROUTINE 7HEN INTERRUPT SOURCE CLEARED SOFTWARE INTERRUPT PROCESSING ROUTINE TERMINATES INTERRUPT PROCESSING &IGURE OUTLINES INTERRUPT OPERATION SERIES MICRO CONTROLLERS
)NTERNAL 2EGISTER FILE
)0,!
#HECK
#OMPARATOR
2ESOURCE
%NABLE 3OURCE 2ESOURCE
,EVEL COMPARATOR
)NTERRUPT CONTROLLER
)NTERRUPT PROCESSING &LOWCHART
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
2ESOURCES
0ORTS
SERIES MICROCONTROLLERS HAVE FIVE PARALLEL PORTS PORTS 0ORTS SERVE PORTS PORT SERVE PORTS PORT SERVES INPUT PORT 0ORTS ALSO USED RESOURCES ,IST PORT FUNCTIONS 4ABLE ,IST 0ORT &UNCTIONS
NAME
)NPUT TYPE #-/3
/UTPUT TYPE OPEN DRAIN OPEN DRAIN OPEN DRAIN
&UNCTION 0ARALLEL PORT 3EGMENT OUTPUT 0ARALLEL PORT 3EGMENT OUTPUT 0ARALLEL PORT
#-/3
#-/3 #-/3 (YSTERESIS #-/3
0ARALLEL PORT %XTERNAL INTERRUPT 0ARALLEL PORT 4IMER SERIAL EXTERNAL INTERRUPT
(YSTERESIS
#-/3 PUSH PULL
2EGISTER LIST PORT CONSISTS FOLLOWING REGISTERS
BITS !DDRESS !DDRESS !DDRESS !DDRESS !DDRESS !DDRESS 0ORT DATA REGISTER 0ORT DATA REGISTER 0ORT DATA REGISTER 0ORT DATA REGISTER )NITIAL VALUE )NITIAL VALUE )NITIAL VALUE )NITIAL VALUE 88888888" )NITIAL VALUE 88888888" )NITIAL VALUE
0ORT DATA REGISTER 0ORT DATA DIRECTION REGISTER
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION FUNCTIONS FUNCTION EACH PORT DESCRIBED BELOW OPEN DRAIN TYPE INPUTOUTPUT PORTS ALSO USED SEGMENT OUTPUT OPEN DRAIN TYPE INPUTOUTPUT PORTS ALSO USED SEGMENT OUTPUT /PERATION OUTPUT PORT VALUE WRITTEN OUTPUT 7HEN READ USUALLY VALUE READ INSTEAD CONTENTS OUTPUT LATCH (OWEVER WHEN 2EAD -ODIFY 7RITE INSTRUCTION EXECUTED CONTENTS OUTPUT LATCH READ 4HEREFORE PROCESSING STRUCTION USED EVEN INPUT OUTPUT MIXED WITH EACH OTHER /PERATION INPUT PORT 7HEN USING THESE PORTS INPUT PORTS TURN TRANSISTOR VALUE ALWAYS READ WHEN READ 7HEN SEGMENT OUTPUT SELECTED CONTROLLER PORT SEGMENT SELECT INPUT DATA ALWAYS READ /PERATION SEGMENT OUTPUT 7HEN USING THESE PORTS SEGMENT OUTPUTS SEGMENT OUTPUT MUST SELECTED MASK OPTION .OTE 7HEN SEGMENT OUTPUT SELECTED VOLTAGE HIGHER THAN CONTROLLER POWER SUPPLY APPLIED 7HEN SEGMENT OUTPUT SELECTED USING CONTROLLER PORT SEGMENT SELECT THESE PORTS USED SEGMENT OUTPUTS 3TATE RESET RESET THESE PORTS SERVE PORT OUTPUTS INITIALIZED OUTPUT TRANSISTOR TURNED BITS 3TATE STOP MODE SEGMENT OUTPUT OUTPUT STATE WHEN ENTERS STOP MODE HELD PORT OUTPUT WHEN STANDBY CONTROL REGISTER STOP MODE OUTPUT IMPEDANCE GOES (IGH IRRESPECTIVE VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
)NTERNAL DATA
3EGMENT OUTPUT
3EGMENT OUTPUT SELECT 3TOP
-ASK OPTION .OTE
READ
READ
WHEN 2EAD -ODIFY 7RITE INSTRUCTION EXECUTED
/UTPUT LATCH WRITE 3TOP
0ORTS .OTE 3ELECTION SEGMENT OUTPUT USING MASK OPTION AVAILABLE ONLY MASS PRODUCED PRODUCTS 3ELECTION USING MASK OPTION MUST SAME THAT USING CONTROLLER SEGMENT OUTPUT SELECT REGISTER CHANNEL OPEN DRAIN TYPE PORTS /PERATION OUTPUT PORT VALUE WRITTEN OUTPUT DIRECTLY 5SUALLY WHEN READ VALUE INSTEAD VALUE OUTPUT LATCH READ (OWEVER WHEN 2EAD -ODIFY 7RITE INSTRUCTION CUTED VALUE OUTPUT LATCH READ THAT PROCESSING STRUCTION USED EVEN WHEN INPUT OUTPUT MIXED TOGETHER /PERATION INPUT PORT 7HEN USING THESE PORTS INPUT PORTS TURN TRANSISTOR VALUE ALWAYS READ READING 3TATE WHEN RESET RESET INITIALIZED OUTPUT TRANSISTOR TURNED BITS 3TATE STOP MODE 7HEN STANDBY CONTROL REGISTER STOP MODE OUTPUT IMPEDANCE GOES (IGH IRRESPECTIVE VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
)NTERNAL DATA
0ULL RESISTOR OPTION
3TOP READ
READ
WHEN 2EAD -ODIFY 7RITE INSTRUCTION EXECUTED
/UTPUT LATCH WRITE 3TOP
0ORT
INPUT PORTS )NPUT PORT OPERATION READ ONLY REGISTER VALUE ALWAYS READ %ACH PORT CONTAINS PULL RESISTOR
)NTERNAL DATA 0ULL RESISTOR OPTION
3TOP READ
EXTERNAL INTERRUPT ONLY %XTERNAL INTERRUPT ENABLE 3TOP
0ORT
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
#-/3 TYPE PORTS ALSO USED RESOURCE INPUT OUTPUT 3WITCHING INPUT OUTPUT 4HIS PORT DATA DIRECTION REGISTER PORT DATA REGISTER EACH )NPUT OUTPUT INDEPENDENTLY EACH WITH OUTPUT WITH INPUT 7HEN RESOURCE OUTPUT ENABLED THESE PORTS OUTPUT IRRESPECTIVE SETTING CONDITIONS /PERATION OUTPUT PORT VALUE WRITTEN OUTPUT WHERE 7HEN READ USUALLY VALUE READ INSTEAD CONTENTS OUTPUT LATCH (OWEVER WHEN 2EAD -ODIFY 7RITE STRUCTION EXECUTED CONTENTS OUTPUT LATCH READ IRRESPEC TIVE SETTING CONDITIONS 4HEREFORE PROCESSING INSTRUC TION USED EVEN INPUT OUTPUT MIXED WITH EACH OTHER 7HEN DATA WRITTEN WRITTEN DATA HELD OUTPUT LATCH IRRE SPECTIVE SETTING CONDITIONS /PERATION INPUT PORT 7HEN USED INPUT PORT OUTPUT IMPEDANCE GOES (IGH 4HERE FORE WHEN READ VALUE READ 2ESOURCE OUTPUT OPERATION 7HEN USING RESOURCE OUTPUT SETTING PERFORMED RESOURCE OUTPUT ENABLE DESCRIPTION EACH RESOURCE 3INCE SOURCE OUTPUT ENABLE PRIORITY SWITCHING INPUT OUTPUT EVEN RESOURCE OUTPUT WHEN OUTPUT ENABLED EACH RESOURCE %VEN OUTPUT FROM EACH RESOURCE ABLED READ VALUE PORT EFFECTIVE RESOURCE OUTPUT VALUE CHECKED 2ESOURCE INPUT OPERATION VALUE PORT WITH RESOURCE INPUT FUNCTION ALWAYS INPUT RESOURCE INPUT IRRESPECTIVE SETTING RESOURCE INPUT WHEN USING EXTERNAL SIGNAL RESOURCE INPUT 3TATE WHEN RESET 7HEN RESET INITIALIZED OUTPUT IMPEDANCE GOES (IGH BITS 7HEN RESET INITIALIZED 4HEREFORE VALUE BEFORE SETTING OUTPUT 3TATE STOP MODE 7ITH STANDBY CONTROL REGISTER STOP MODE OUTPUT IMPEDANCE GOES (IGH IRRESPECTIVE VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
%XTERNAL INTERRUPT ENABLE 3TOP EXTERNAL INTERRUPT 3TOP 2ESOURCE INPUT )NTERNAL DATA
2ESOURCE OUTPUT
2ESOURCE OUTPUT ABLE
0ULL RESISTOR OPTION
READ
READ
/UTPUT LATCH
WHEN 2EAD -ODIFY 7RITE INSTRUCTION EXECUTED
WRITE
WRITE 3TOP
0ORT
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
4IMER 4IMER
4HIS TIMER USED TIMER CONTROL CIRCUIT WITH RESOLUTION &OUR CLOCK PULSES SELECTED "LOCK DIAGRAM
)NTERNAL DATA
#.42
#/-2 #OMPARE REGISTER
3TART #,%!2
COUNTER
/6%2 &,/7 4IMER #OMPARATOR
3ELECTOR CLOCK PULSE
4IMER OUTPUT TIMER
GENERATOR OUTPUT CONTROL /UTPUT ENABLE SIGNAL
/UTPUT
CLOCK PULSE OSCILLATION
2EGISTER LIST
BITS !DDRESS !DDRESS #.42 #/-2 #ONTROL REGISTER #OMPARE REGISTER
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION REGISTERS #ONTROL REGISTER #.42
!DDRESS #.42 !DDRESS #/-2
!DDRESS
)NITIAL VALUE
;"IT 4IMER07- OPERATION MODE SWITCHING OPERATION PERFORMED TIMER WHEN CONTROL CIRCUIT WHEN 4IMER CONTROL CIRCUIT
7HEN SWITCHING CHANNELS STOPPING COUNTING INTER RUPT DISABLED INTERRUPT REQUEST FLAG CLEARED ;"ITS #LOCK PULSE SELECT BITS #LOCK PULSES FROM PRESCALER OUTPUT TIMER PULSE WIDTH COUNT TIMER SELECTED USING #LOCK CYCLE )NTERNAL CLOCK PULSE INSTRUCTION CYCLE )NTERNAL CLOCK PULSE INSTRUCTION CYCLES )NTERNAL CLOCK PULSE INSTRUCTION CYCLES 4IMER CYCLE
.OTE THAT THESE BITS MUST REWRITTEN WHEN COUNTER OPERATING ;"IT #OUNTING ENABLE 7HEN THESE BITS TIMER CONTROL CIRCUIT STARTS OPERA TION 3TOPS COUNTING 3TARTS COUNTING
;"IT #HANNEL INTERRUPT REQUEST FLAG "ITS GOES WHEN INTERRUPT SOURCE OCCURS CLEAR GENERATED INTERRUPT SOURCE WRITE THIS MEANING READ LOWS
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
6ALUES COUNTER #/-2 MATCH 6ALUES COUNTER #/-2 MATCH
.OTE THAT ALWAYS READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION CUTED MEANING EACH WRITTEN FOLLOWS #LEARS THIS $OES CHANGE THIS AFFECT OTHER BITS
.OTE OPERATION MODE NEITHER READ WRITE VALUES THESE BITS HAVE MEANING ;"IT /UTPUT SIGNAL CONTROL 7HEN PORT SERVES TIMER OUTPUT TIMER OPERA TION MODE SIGNAL THAT REVERSED EACH TIME VALUES COUNTER COMPARE REGISTER MATCH OUTPUT OPERATION MODE 07SIGNAL OUTPUT 'ENERAL PURPOSE PORTS #OUNTER07- OUTPUT PINS
%VEN INPUT WHEN THIS SERVES COUNTER07- OUTPUT ;"IT )NTERRUPT ENABLE 4IMER MODE INTERRUPT OCCURS WHEN VALUES COUNTER COMPARE REGISTER MATCH $ISABLES COUNTER INTERRUPT OUTPUT %NABLES COUNTER INTERRUPT OUTPUT
(OWEVER OPERATION MODE INTERRUPT DOES OCCUR IRRESPEC TIVE VALUE THIS BITS !DDRESS #.42 !DDRESS #/-2 #OMPARE REGISTER #/-2 4HIS REGISTER SETS VALUE COMPARED WITH COUNTER VALUE TIMER OPERATION MODE ALSO CLEARS COUNTER WHEN VALUE AGREES WITH COUNTER VALUE OPERATION MODE (IGH PULSE WIDTH SPECIFIED THIS REGISTER VALUE
!DDRESS )NITIAL VALUE 88888888"
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION OPERATION 4IMER FUNCTION 3ETTING #.42 GIVES TIMER OPERATION MODE 7HEN #.42 COUNTER STARTS INCREMENTING FROM 7HEN VALUE COUNTER AGREES WITH THAT #/-2 COUNTER CLEARED NEXT COUNT CLOCK PULSE INCREMENTING RESTARTS 4HEREFORE BITS OUTPUT REVERSED WHEN OUTPUT FIXED LEVEL CYCLES COUNT CLOCK PULSES WHEN WRITTEN #/-2 CYCLES TIMES LONGER THAN THOSE COUNT CLOCK PULSES WHEN WRITTEN VALUE #/-2 REWRITTEN TIMER OPERATION MODE COMES EFFECTIVE FROM NEXT CYCLE WHEN VALUE COUNTER VALUE #/-2 TRANSFERRED COMPARATOR LATCH
#OUNT CLOCK PULSE /UTPUT SETTING 6ALUE #/-2
4IMER /PERATION #.42 INTERRUPT OCCURS WHEN VALUES COUNTER #/-2 MATCH $URING INTERRUPT PROCESSING USED INTERRUPT FLAG IRRESPECTIVE VALUE (OWEVER VALUES COUNTER #/-2 MATCH EVEN AFTER INTERRUPT DISABLED 7RITING PERMITS CLEARING INTERRUPT SOURCE 7HEN 2EAD -ODIFY 7RITE INSTRUCTION READ THAT ALWAYS READ PREVENT ERRONEOUS CLEARING COUNT CLOCK PULSE SELECTED FROM THREE CLOCK PULSES FROM PRESCALER CLOCK PULSE FROM INTERNAL TIMER CLOCK PULSE LECT BITS #.42
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
OPERATION 3ETTING #.42 GIVES OPERATION MODE #/-2 SPECIFIES DUTY OUTPUT PULSE 0ULSES OUTPUT WITH RESOLUTION DUTY 7HEN WRITTEN #/-2 DUTY OUTPUT PULSE WHEN WRITTEN DUTY WHEN WRIT VALUE #/-2 TRANSFERRED COMPARATOR LATCH WHEN VALUE COUNTER VALUE #/-2 REWRITTEN OPERA TION MODE BECOMES EFFECTIVE FROM NEXT CYCLE
7HEN #/-2 #OUNTER VALUE PULSE OUTPUT
7HEN #/-2 #OUNTER VALUE PULSE OUTPUT
7HEN #/-2 #OUNTER VALUE PULSE OUTPUT
0ULSE /UTPUT OPERATION MODE VALUES #.42 HAVE MEANING INTERRUPTION OCCURS EVEN CYCLE PULSE CHANGED SWITCHING COUNT CLOCK PULSE COUNT CLOCK PULSE SELECTED FROM THREE CLOCK PULSES PRES CALER CLOCK PULSE INTERNAL TIMER CLOCK PULSE SELECT BITS #.42
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
0ULSE WIDTH #OUNT 4IMER 4IMER
4HIS TIMER TIMER PULSE WIDTH MEASUREMENT FUNCTIONS TIMER FUNCTION MODES RELOAD TIMER SHOT RELOAD TIMER MODE VALUES COUNTED DOWN REPEATEDLY SHOT MODE COUNTING DOWN STARTED FROM VALUES STOPS FIRST UNDERFLOW PULSE WIDTH MEASUREMENT FUNCTION ENABLES MEASUREMENT (IGH CYCLE WIDTHS PULSES INPUT FROM PINS INPUTTING FROM PINS NOISE CLEARING CERCUIT SELECTABLE "LOCK DIAGRAM
)NTERNAL DATA
TIMER .##2
&ROM TIME BASE TIMER &UNCTION SWITCHING CIRCUIT 4IMING GENERATOR 3ELECTOR
DOWN COUNTER
)NPUT PULSE EDGE DETECTOR
.OISE CLEAR
007#
2,"2 3ELECTOR
CLOCK PULSE OSCILLATION DIVIDED PULSE CLOCK PULSE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
2EGISTER LIST
BITS !DDRESS !DDRESS !DDRESS !DDRESS 2,"2 .##2 0ULSE WIDTH CONTROL REGISTER 0ULSE WIDTH CONTROL REGISTER 2ELOAD BUFFER REGISTER .OISE CLEAR CONTROL REGISTER
$ESCRIPTION REGISTERS !DDRESS !DDRESS !DDRESS 2,"2 !DDRESS .##2 0ULSE WIDTH CONTROL REGISTER
!DDRESS )NITIAL VALUE
;"IT #OUNT ENABLE TIMER FUNCTION WHEN WRITTEN THIS VALUE DATA REGIS LOADED START COUNTING DOWN 7HEN WRITTEN COUNTING DOWN STOPS PULSE WIDTH MEASUREMENT FUNCTION WHEN WRITTEN THIS MEASUREMENT ENABLE STATE 5NDER THIS CONDITION COUNTING DOWN STARTED WHEN EDGE MEASURED PULSE DETECTED 7HEN WRITTEN THIS DURING MEASUREMENT COUNTING DOWN STOPS COUNT TRANS FERRED RELOAD BUFFER REGISTER 2,"2 4IMER FUNCTION #OUNT DISABLE #OUNT ENABLESTART 0ULSE WIDTH MEASUREMENT FUNCTION 0ULSE WIDTH MEASUREMENT STOPDISABLE 0ULSE WIDTH MEASUREMENT ENABLESTART
;"IT )NTERRUPT REQUEST ENABLE 7HEN INTERRUPT REQUEST OUTPUT WHEN INTERRUPT REQUEST FLAGS )NTERRUPT DISABLED )NTERRUPT ENABLED
;"IT 5NDERFLOW INTERRUPT REQUEST INDICATES WHETHER TIMER UNDERFLOWED MEANING EACH READ FOLLOWS UNDERFLOW 5NDERFLOW OCCURRED
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
ALWAYS READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION EXECUTED MEANING EACH WRITTEN FOLLOWS #LEARS THIS 5NCHANGES THIS OTHER BITS UNAFFECTED
;"IT -EASUREMENT INTERRUPT REQUEST 7HEN INTERRUPT OCCURS PULSE WIDTH MEASUREMENT MEANING EACH READ FOLLOWS 0ULSE WIDTH MEASUREMENT TERMINATED 0ULSE WIDTH MEASUREMENT TERMINATED
ALWAYS READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION EXECUTED MEANING EACH WRITTEN FOLLOWS #LEARS THIS 5NCHANGES THIS OTHER BITS UNAFFECTED
;"IT "UFFER FULL FLAG 7HEN INTERRUPT OCCURS WHEN SURED VALUE FOUND 2$"2 4HIS PULSE WIDTH MEASUREMENT CLEARED WHEN DATA BUFFER READ MEANING EACH READ FOLLOWS 0ULSE WIDTH MEASURED VALUE FOUND 0ULSE WIDTH MEASURED VALUE FOUND
!DDRESS !DDRESS !DDRESS 2,"2 !DDRESS .##2
0ULSE WIDTH CONTROL REGISTER
!DDRESS )NITIAL VALUE
;"IT &UNCTION SELECT USED SELECT TIMER PULSE WIDTH MEASUREMENT FUNCTIONS 4IMER FUNCTION 0ULSE WIDTH MEASUREMENT FUNCTION
FUNCTION SHOULD SELECTED WHEN OPERATION STOPPED WHEN
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"IT 4IMER MODE SELECT TIMER FUNCTION USED SELECT TIMER MODE 2ELOAD TIMER MODE SHOT TIMER MODE
MODE SHOULD SELECTED WHEN OPERATION STOPPED WHEN ;"IT 4IMER OUTPUT VALUE INVERTED EACH TIME COUNTER UNDERFLOWS WRITE MUST REWRITTEN WHEN ;"ITS #OUNT CLOCK PULSE SELECT BITS 3ETTING PERFORMED SHOWN BELOW USING COMBINATION BITS 4HESE BITS IRRELEVANT VALUE #OUNT CLOCK PULSE )NTERNAL CLOCK PULSE INSTRUCTION CYCLE )NTERNAL CLOCK PULSE INSTRUCTION CYCLES )NTERNAL CLOCK PULSE INSTRUCTION CYCLES
;"ITS -EASURED PULSE SELECT BITS 3ETTING PERFORMED SHOWN BELOW USING COMBINATION BITS 4HESE BITS IGNORED WHEN TIMER OPERATION (IGH LEVEL LEVEL 2ISING RISING &ALLING FALLING -EASURED PULSE WIDTH
!DDRESS !DDRESS !DDRESS 2,"2 !DDRESS .##2
2ELOAD BUFFER REGISTER 2,"2 TIMER FUNCTION 2,"2 READ WRITE RELOAD REGISTER PULSE WIDTH MEASUREMENT READ ONLY DATA BUFFER REGISTER HOLDING MEASURED VALUES THIS CASE WRITING IMPOSSIBLE CLEARED READING DATA
!DDRESS 4IMER FUNCTION
0ULSE WIDTH MEASUREMENT FUNCTION
)NITIAL VALUE 88888888"
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
.OISE CLEAR CONTROL REGISTER .##2
!DDRESS )NITIAL VALUE
!DDRESS !DDRESS !DDRESS 2,"2 !DDRESS .##2
;"ITS 3AMPLING CLOCK PULSE SELECT BITS SAMPLING CLOCK PULSE NOISE CLEARING CIRCUIT SELECTED SHOWN BELOW COMBINATION BITS #LOCK PULSE SELECTED NOISE CLEAR /SCILLATION CLOCK PULSE /SCILLATION CLOCK PULSE /SCILLATION CLOCK PULSE $ESCRIPTION OPERATION 4IMER FUNCTION TIMER FUNCTION FOLLOWING MODES 2ELOAD TIMER MODE %ACH TIME COUNTER UNDERFLOWS VALUE WRITTEN 2,"2 LOADED CONTINUE COUNTING DOWN THIS MODE WHEN COUNTER UNDER FLOWS INTERRUPT REQUEST FLAG INTERRUPT REQUEST OUTPUT WHEN %ACH TIME TIMER UNDERFLOWS VALUE INVERTED SHOT MODE #OUNTING STOPS UNDERFLOW THIS MODE WHEN COUNTER UNDER FLOWS UNDERFLOW INTERRUPT REQUEST FLAG AUTOMATICALLY STOP COUNTING BOTH MODES COUNTING STARTS WHEN WRITTEN STOPS WHEN WRITTEN #LOCK CYCLE ;mS= ;mS= ;mS= .OISE PULSE WIDTH ;mS= ;mS= ;mS=
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
0ULSE WIDTH MEASUREMENT FUNCTION -EASUREMENT START 7RITING CAUSES COUNTER ENTER OPERATION ENABLED STATE THIS CONDITION COUNTING STARTS WHEN EDGE MEASURED PULSE INPUT DETECTED PULSE WIDTH SUREMENT FUNCTION COUNTING DOWN STARTED FROM -EASUREMENT MEASURED VALUE 7HEN MEASUREMENT TERMINATED MEASURED VALUE TRANSFERRED BUFFER MEASUREMENT FLAG BUFFER FULL FLAG CAUSING COUNTER ENTER OPERATION ENABLED STATE THIS TIME INTERRUPT REQUEST OUTPUT WHEN 7HEN PREVIOUS MEASURED VALUE CANNOT READ AFTER CONTINU PULSE WIDTH MEASUREMENT HELD CONTINUING FLAG MEASURED VALUE DISCARDED ,ONG PULSE 7HEN COUNTER UNDERFLOWS DURING MEASUREMENT CONTINUE COUNTING THIS CASE INTERRUPT REQUEST ALSO OUTPUT WHEN -EASUREMENT STOP -EASUREMENT STOPS WHEN WRITTEN #ALCULATION PULSE WIDTH COUNT VALUE WHEN MEASUREMENT TERMINATED TRANSFERRED MEASURED VALUE BUFFER 4HEREFORE PULSE WIDTH SHOULD CALCU LATED USING FOLLOWING EQUATION 0ULSE WIDTH COUNT VALUE .UMBER COUNTS INVERTED CYCLE WIDTH COUNT CLOCK PULSE /THERS COUNTER REMAINS OPERATION ENABLED STATE EVEN AFTER MEASUREMENT CONTINUOUS PULSE WIDTH MEASUREMENT POSSIBLE -EASUREMENT (IGH PULSE WIDTH STARTED FROM CHANGING EDGE INPUT PULSE 7HEN INPUT PULSE ALREADY (IGH WHEN ENABLED COUNTING PERFORMED AFTER NEXT RISING EDGE
)NPUT PULSE SIGNAL #OUNT STOP #OUNT
-EASUREMENT (IGH 0ULSE 7IDTH
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
.OISE CLEARING CIRCUIT OPERATION &IGURE SHOWS OPERATION NOISE CLEARING CIRCUIT SAMPLED CLOCK PULSE SELECTED CLOCK PULSE SELECT BITS NOISE CLEAR CONTROL REGISTER )NTEGRATING SAMPLED SIGNAL CLEARS NOISE MAXIMUM WIDTH CLEARED NOISE FOLLOWS 3AMPLING CLOCK CYCLE 7HEN NOISE CLEARING PROHIBITED INPUT INPUT DIRECTLY PULSE WIDTH COUNT TIMER
INPUT 3AMPLING CLOCK PULSE
)NTEGRATED VALUE
)NTERNAL SIGNAL
/PERATION .OISE #LEARING #IRCUIT
5SAGE PRECAUTIONS REWRITE VALUE WHEN DURING TIMER ERATION PULSE WIDTH MEASUREMENT MODE SWITCHING REWRITING STATE EACH FLAG DOES CHANGE #LEAR EACH FLAG IMMEDIATELY AFTER MODE SWITCHED 2EAD MEASURED VALUE BEFORE NEXT UNDERFLOW 7HEN VALUE READ AFTER UNDERFLOW INVERTED SOMETIMES DISABLING CULATION CORRECT MEASURED VALUE 7HEN PREVIOUS MEASURED VALUE CANNOT READ AFTER CONTINUOUS PULSE WIDTH MEASUREMENT HELD WITHOUT TRANSFERRING VALUE BUFFER
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
5!24
&ULL DUPLEX DOUBLE BUFFERS SYNCHRONOUS ASYNCHRONOUS DATA TRANSFER BAUD RATES INTERNAL CLOCK BAUD RATE ALSO FREELY SELECTED EXTERNAL CLOCK INPUT INPUT FROM INTERNAL TIMER 6ARIABLE DATA LENGTH TRANSFER FORMAT DATA CLOCK PINS SWITCHED DATA CLOCK INPUTOUTPUT POLARITIES INVERTED "LOCK DIAGRAM "AUD RATE GENERATOR SERIAL CLOCK GENERATOR
CLOCK TIMER OUTPUT 3ERIAL CLOCK
5!24 SERIAL CLOCK 03#+ 3ERIAL CLOCK 03#+
23%,
SWITCHING BETWEEN PORT OUTPUT SERIAL CLOCK OUTPUT 3#+% 5!24 VALID WHEN 23%, 3#+% SERIAL VALID WHEN 23%,
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ATA TRANSMITTERRECEIVER
$ATA
0ARITY GENERATOR 3TART DETECTION 3TART 2ESET 2ECEIVER BYTE COUNT 3HIFT CLOCK 4RANSFER CLOCK 3)$2 2$2& /2&% 4$40 3HIFTER
2$20
0ARITY GENERATOR 4IMING 2ESET 3HIFT CLOCK 3HIFTER 03#+
4RANSMITTER BYTE COUNT
4RANSMITTER CONTROL
4RANSFER CLOCK 4$2% 3/$2 23%,
3ERIAL DATA 2$2& /2&% 4$2%
SWITCHING BETWEEN PORT OUTPUT SERIAL DATA OUTPUT 5!24 VALID WHEN 23%, SERIAL VALID WHEN 23%,
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
2EGISTER LIST
BITS !DDRESS !DDRESS !DDRESS !DDRESS !DDRESS !DDRESS 3)$2 3/$2 3ERIAL MODE CONTROL REGISTER 3ERIAL RATE CONTROL REGISTER 3ERIAL STATUS DATA REGISTER 3ERIAL INPUT DATA REGISTER 3ERIAL OUTPUT DATA REGISTER
3ERIAL MODE CONTROL REGISTER
$ESCRIPTION REGISTERS 3ERIAL MODE CONTROL REGISTER !DDRESS !DDRESS !DDRESS !DDRESS 3)$2 !DDRESS 3/$2 !DDRESS 4HIS REGISTER USED SELECT 5!24 OPERATION MODE
!DDRESS 3-$% 3#+%
)NITIAL VALUE
;"IT 0ARITY ENABLE USED DETERMINE WHETHER APPEND PARITY WHEN TRANSMITTING DETECT WHEN RECEIVING SERIAL DATA INPUTOUTPUT PARITY )NITIAL VALUE
0ARITY EVEN PARITY 4$40 REGISTER
;"IT 3TOP LENGTH USED DETERMINE STOP LENGTH TRANSMIT DATA RECEIVING ONLY FIRST STOP RECOGNIZED SECOND LATER BITS IGNORED LENGTH LENGTH )NITIAL VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"ITS -ODE CONTROL "ITS USED SELECT TRANSFER MODE DATA LENGTH -ODE $ATA LENGTH )NITIAL VALUE 6ALUES PARENTHESES INDICATE DATA LENGTH WITH PARITY
.OTE OCCURRENCE RECEIVE INTERRUPT MODE DIFFERENT FROM THAT OTHER MODES THIS MODE 5!24 RECEIVE INTERRUPT REQUESTED WHEN 2$2& /2&% $ESCRIPTION /PERATION 4HIS MODE USED WHEN SEVERAL SLAVE CONNECTED HOST ;"IT 3-$% 3YNCHRONOUS TRANSFER !SYNCHRONOUS TRANSFER )NITIAL VALUE
;"IT 3#+% 3#,+ ENABLE 7HEN WRITTEN 5!24 SERIAL CLOCK OUTPUT SWITCHED PORT OUTPUT EXTERNAL SYNCHRONOUS CLOCK PULSE MODE WHICH SYNCHRONOUS CLOCK PULSE INPUT FROM OUTSIDE BITS REGISTER VALUE ALSO READ FROM PORT INPUT &UNCTIONS GENERAL PURPOSE INPUTOUTPUT PORT THAT DOES OUTPUT SERIAL CLOCK PULSE 7HEN PORT INPUT ALSO FUNCTIONS SERIAL CLOCK INPUT )NITIAL VALUE &UNCTIONS 5!24 SERIAL CLOCK INPUTOUTPUT PORT
EXTERNAL CLOCK INPUT MODE THIS 4HIS VALID WHEN 23%, ;"IT 3ERIAL OUTPUT ENABLE 7HEN WRITTEN PORT SWITCHED 5!24 SERIAL DATA OUTPUT ENABLE SERIAL DATA OUTPUT &UNCTIONS PORT THAT DOES OUTPUT SERIAL DATA &UNCTIONS 5!24 SERIAL DATA OUTPUT PORT 3/54 4HIS VALID WHEN 23%, )NITIAL VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
3ERIAL RATE CONTROL REGISTER 4HIS REGISTER USED CONTROL DATA TRANSFER SPEED BAUD RATE 5!24
!DDRESS !DDRESS !DDRESS !DDRESS 3)$2 !DDRESS 3/$2 !DDRESS
!DDRESS
)NITIAL VALUE
;"IT #LOCK RATE USED SELECT ASYNCHRONOUS TRANSFER CLOCK RATE (OWEVER WHEN BITS CLOCK RATE SELECTED IRRESPECTIVE VALUE CLOCK INPUT CLOCK INPUT )NITIAL VALUE
.OTE SYNCHRONOUS TRANSFER CLOCK RATE FOLLOWS IRRESPECTIVE VALUE #LOCK SOURCE TIMER DEDICATED BAUD RATE GENERATOR %XTERNAL CLOCK DEDICATED BAUD RATE GENERATOR .OTE THAT DEDICATED BAUD RATE GENERATOR SELECT CLOCK RATE ACCORDING VALUE ;"ITS #LOCK SELECT "ITS USED SELECT CLOCK INPUT 5!24 PORT EXTER INTERNAL CLOCK SELECTED CLOCK INPUT BAUD RATE CLOCK FREQUENCY ACCORDING VALUE INITIAL VALUE DETAILS $ESCRIPTION OPERATION ;"ITS "ITS NEEDED ONLY WHEN GENERATING SERIAL CLOCK PULSE WITH DEDICATED BAUD RATE GENERATOR BAUD RATE SELECTED FROM EIGHT KINDS THESE BITS INITIAL VALUE BAUD RATE SETTING $ESCRIPTION /PERATION
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
3ERIAL STATUS DATA REGISTER 4HIS REGISTER USED INDICATE CURRENT STATUS 5!24 PORT 7HEN DATA COMMUNICATION LENGTH BITS MOST SIGNIFICANT DATA INCLUDED
!DDRESS !DDRESS !DDRESS !DDRESS 3)$2 !DDRESS 3/$2 !DDRESS
!DDRESS 2$2&
/2&%
4$2%
)NITIAL VALUE
;"IT 2$2& 2$2& FLAG USED INDICATE DATA STATUS SERIAL INPUT DATA REGISTER 3)$2 %MPTY #ONTAINS DATA )NITIAL VALUE
7HEN 3)$2 REGISTER READ AFTER READING REGISTER WITH 2$2& FLAG 2$2& FLAG CLEARED 7HEN THIS FLAG RECEIVER INTERRUPT REQUEST OUTPUT ;"IT /2&% /2&% FLAG USED INDICATE THAT OVERRUN FRAMING ERROR CURRED 4HIS FLAG INITIALIZED RESET .ORMAL %RROR
THIS FLAG DATA TRANSFERRED FROM RECEIVE SHIFT REGISTER 3)$2 REGISTER 7HEN 3)$2 REGISTER READ AFTER READING REGISTER WITH /2&% FLAG /2&% FLAG CLEARED 7HEN THIS FLAG RECEIVER INTERRUPT REQUEST OUTPUT STATUS INPUT DATA SPECIFIED 2$2& /2&% FLAGS FOLLOWS 2$2& /2&% %MPTY &RAMING ERROR DATA INPUT UNDER THIS CONDITION 2$2& .ORMAL DATA /VERRUN PREVIOUS DATA REMAINS 3)$2 DATA STATUS
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"IT 4$2% 4$2% FLAG USED INDICATE STATUS SERIAL OUTPUT DATA REGISTER 3/$2 #ONTAINS DATA %MPTY )NITIAL VALUE
7HEN DATA WRITTEN 3/$2 REGISTER AFTER READING REGISTER WITH 4$2% FLAG SERIAL DATA OUTPUT FROM 3/54 7HEN 4$2% FLAG TRANSMITTER INTERRUPT REQUEST OUTPUT ;"IT 4RANSMITTER INTERRUPT REQUEST ENABLE USED ENABLE TRANSMITTER INTERRUPT REQUEST $ISABLES INTERRUPT %NABLES INTERRUPT )NITIAL VALUE
;"IT 2ECEIVER INTERRUPT REQUEST ENABLE USED ENABLE RECEIVER INTERRUPT REQUEST $ISABLES INTERRUPT %NABLES INTERRUPT )NITIAL VALUE
;"IT 4$40 7HEN PARITY PROVIDED TREATED 3/$2 REGISTER 7HEN PARITY PROVIDED THIS USED DETERMINE WHETHER PARITY SERIAL OUTPUT DATA EVEN PARITY %VEN PARITY )NITIAL VALUE
;"IT 2$20 7HEN PARITY PROVIDED TREATED 3)$2 REGISTER 7HEN PARITY PROVIDED THIS USED DETERMINE WHETHER PARITY SERIAL INPUT DATA EVEN )NITIAL VALUE UNDEFINED PARITY %VEN PARITY
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
3ERIAL INPUT DATA REGISTER 3)$2 3ERIAL OUTPUT DATA REGISTER 3/$2 3)$2
!DDRESS
!DDRESS !DDRESS !DDRESS !DDRESS 3)$2 !DDRESS 3/$2 !DDRESS !DDRESS !DDRESS !DDRESS !DDRESS 3)$2 !DDRESS 3/$2 !DDRESS
3)$2 REGISTER USED INPUT SERIAL DATA )NITIAL VALUE UNDEFINED 3/$2
!DDRESS
3/$2 REGISTER USED OUTPUT SERIAL DATA )NITIAL VALUE UNDE FINED 3ERIAL MODE CONTROL REGISTER
!DDRESS 03%. 23%,
)NITIAL VALUE
;"IT 03%. USED DETERMINE WHETHER START STOP OPERATION BAUD RATE GENERATOR 3TOPS OPERATION 3TARTS OPERATION )NITIAL VALUE
;"IT 23%, USED SELECT WHETHER EITHER 5!24 SERIAL OUTPUT DATA CLOCK 5!24 3ERIAL )NITIAL VALUE
;"ITS "ITS USED SELECT DIVISION DIVIDER FRONT BAUD RATE GENERATOR
(!2$7!2% #/.&)'52!4)/.
3ELECTS DIVIDING 3ELECTS DIVIDING 3ELECTS DIVIDING 3ELECTS DIVIDING )NITIAL VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION OPERATION /PERATION MODES 5!24 OPERATION MODES LISTED 4ABLE THEY SWITCHED SETTING VALUE SERIAL MODE CONTROL REGISTER 4ABLE /PERATION -ODES 5!24 -ODE 0ARITY 0ROVIDED PROVIDED 0ROVIDED PROVIDED PROVIDED 0ROVIDED PROVIDED $ATA LENGTH #LOCK MODE !SYNCHRONOUSSYNCHRONOUS !SYNCHRONOUSSYNCHRONOUS !SYNCHRONOUSSYNCHRONOUS !SYNCHRONOUSSYNCHRONOUS !SYNCHRONOUSSYNCHRONOUS !SYNCHRONOUSSYNCHRONOUS !SYNCHRONOUSSYNCHRONOUS 3TOP LENGTH BITS BITS BITS BITS BITS BITS BITS
(OWEVER STOP LENGTH SPECIFIED ONLY TRANSMITTER CHAN LENGTH ALWAYS SPECIFIED RECEIVER CHANNEL )NTERRUPT OCCURRENCE FLAG SETTING CONDITIONS 5!24 THREE FLAGS INTERRUPT SOURCES THREE FLAGS /2&% 2$2& 4$2% /2&% FLAG OVERRUN FRAMING ERROR FLAG WHICH WHEN ERROR OCCURS RECEIVING 2$2& FLAG INDICATES THAT RECEIVE DATA READY 3)$2 REGISTER 4$2% FLAG INDICATES THAT WRITING TRANSMIT DATA REGISTER 3/$2 ENABLED INTERRUPT SOURCES RECEIVING TRANSMITTING RECEIVING INTERRUPT REQUESTED 2$2& /2&% FLAG TRANSMIT TING INTERRUPT REQUESTED 4$2% FLAG CONDITIONS TIMING SETTING EACH FLAG VARY ACCORDING OPERA TION MODES CONDITIONS TIMING INTERRUPT REQUESTS ALSO VARY FLAG TIMING EACH MODE SHOWN BELOW A2ECEIVING MODES "OTH 2$2& RECEIVE DATA REGISTER FULL /2&% OVERRUNFRAMING FLAGS WHEN RECEIVING TRANSFER COMPLETED LAST STOP DETECTED INTERRUPT REQUEST THEN OUTPUT 7HEN 2$2& FLAG ACTIVE RECEIVED DATA TRANSFERRED SERIAL DATA INPUT REGISTER 3)$2
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ATA 2$2& INTERRUPT
3TOP
3TOP
2$2& &LAG 4IMING
$ATA 2$2& /2&% INTERRUPT
3TOP
$ATA 2$2& /2&% INTERRUPT
3TOP
/VERRUN ERROR
&RAMING ERROR
/2&% &LAG 4IMING
2ECEIVING MODE "OTH 2$2& /2&% FLAGS WHEN RECEIVING TRANSFER COMPLETED WITH LAST DATA LAST STOP TECTED (OWEVER WHEN FRAMING ERROR OCCURS FLAGS IRRESPEC TIVE VALUE LAST DATA INTERRUPT REQUEST OUTPUT WHEN FLAGS INPUT DATA GOES 5SING MODE
$ATA 2$2& INTERRUPT 3TOP 3TOP
2$2& &LAG 4IMING
$ATA 2$2& /2&% INTERRUPT
3TOP
$ATA 2$2& /2&% INTERRUPT
3TOP
/VERRUN ERROR
&RAMING ERROR
/2&% &LAG 4IMING
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
4RANSMISSION 7HEN NEXT DATA READY WRITE AFTER DATA WRITTEN 3/$2 SERIAL OUTPUT DATA REGISTER TRANSFERRED INTERRUPT SHIFT REGISTER 4$2% TRANSMIT DATA REGISTER EMPTY FLAG INTERRUPT REQUEST OUTPUT
3/$2 WRITE 4$2% )NTERRUPT REQUEST OUTPUT 3/54 INTERRUPT 3/54 OUTPUT 3TART
$ATA BITS
3TOP
4$2% &LAG 4IMING -ODE
4RANSFER DATA FORMAT 5!24 HANDLE ONLY RETURN ZERO TYPE DATA RELA TIONSHIP BETWEEN TRANSMITTERRECEIVER CLOCKS DATA SHOWN FIGURE BELOW
3TART 3TOP 3TOP 3TOP 6ARIES WITH MODE
4RANSMITTED DATA MODE MODE
4RANSFER $ATA &ORMAT SHOWN FIGURE DATA TRANSFER STARTS FROM START LEVEL DATA DATA LENGTH SPECIFIED FIRST TRANSFERRED TRANSFER ENDS STOP (IGH LEVEL DATA ASYNCHRONOUS TRANSFER RELATIONSHIP BETWEEN SHOWN ABOVE FIGURE ADDITION ASYNCHRONOUS TRANSFER RELA TIONSHIP SHOWN ABOVE DIAGRAM EVEN WHEN INPUT
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
4RANSFER CLOCK SELECTION TRANSFER CLOCK SELECTED FROM EXTERNAL CLOCK 07TIMER DEDICATED BAUD RATE GENERATOR 4HIS SELECTION DONE BITS SERIAL RATE CONTROL REGISTER DIVISION RATIOS LISTED 4ABLE 4ABLE #LOCK $IVISION 2ATIO
#LOCK INPUT %XTERNAL CLOCK TIMER
!SYNCHRONOUS
3YNCHRONOUS
$EDICATED BAUD RATE GENERATOR
7HEN USING DEDICATED BAUD RATE GENERATOR SELECT INPUT CLOCK BAUD RATE GENERATOR 4ABLE INDICATES INPUT CLOCKS USED DIVISION 4ABLE INDICATES ERENCE BAUD RATES 4ABLE )NPUT #LOCK "AUD 2ATE 'ENERATOR $IVISION #LOCK OPERATION OPERATION OPERATION OPERATION
4ABLE 3ELECTION "AUD 2ATE 7HEN $EDICATED "AUD 2ATE 'ENERATOR 5SED $IVISION RATIO "AUD RATE 2EMARKS #LOCK DIVISION DIVISION
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
3ELECTION INPUTOUTPUT SIGNAL 5!24 SHARES DATA CLOCK INPUTOUTPUT WITH SERIAL 4HERE FORE OUTPUT SIGNAL SELECTED 23%, OUTPUT SWITCHING TWEEN PORT OUTPUT RESOURCE OUTPUT RESOURCE ENABLE SELECTED 23%, BECOMES VALID 7HEN 23%, 5!24 SELECTED 7HEN 23%, SERIAL SELECTED 5SING MODE %XAMPLE
OCCURRENCE RECEIVE INTERRUPT MODE DIFFERENT FROM THAT OTHER MODES 5!24 RECEIVER INTERRUPT REQUEST THIS MODE OUTPUT WHEN 2$2& /2&% 4HIS MODE USED WHEN SEVERAL SLAVE #05S CONNECTED HOST &IGURE
-ASTER
3LAVE
3LAVE
3YSTEM #ONFIGURATION 7HEN -ODE 5SED #OMMUNICATION STARTED WHEN TRANSFERS ADDRESS DATA ADDRESS DATA DATA WITH WHICH SELECTS SLAVE COMMUNICATION SOURCE 7HEN SLAVE SELECTED COMMUNICA TION WITH MASTER PERFORMED ACCORDING USER DEFINED RULES $ATA WITH USUALLY USED UNSELECTED SLAVE WAITS UNTIL NEXT COMMUNICATION STARTED &IGURE SHOWS FLOWCHART PARITY CHECK FUNCTION CANNOT USED THIS MODE SHOULD
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
-ASTER 3TART TRANSFER MODE DATA SELECTION SLAVE PERFORM BYTE TRANSFER COMMUNICATE
3LAVE 3TART TRANSFER MODE BYTE RECEIVING 3ELECTED TRANSFER MODE #OMMUNICATE WITH MASTER
#OMMUNICATION &LOWCHART 7HEN -ODE 5SED !FTER SLAVE COMPLETES COMMUNICATION WITH MASTER TIMING DISABLING OUTPUT DETERMINED FOLLOWING THREE METHODS 7RITE LAST DATA 3/$2 REGISTER WAIT SHIFT CLOCKS AFTER 4$2% FLAG THEN DISABLE OUTPUT !FTER RECEIVING LAST DATA FROM MASTER DISABLE OUTPUT #ONFIGURE SIGNAL LINE CONNECTED OUTPUT SLAVE WIRED THIS CASE THERE NEED DISABLE OUTPUT 0RECAUTIONS 5!24 !FTER CANCELING REGISTER INITIALIZATION RESET SHIFT CLOCKS REQUIRED INITIALIZE INTERNAL CONTROL SECTION 7HEN USING EXTERNAL CLOCK MINIMUM PULSE WIDTH FOLLOWS OPERATING CLOCK CYCLE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
3ERIAL
SERIAL DATA TRANSFER POSSIBLE CLOCK SYNCHRONOUS METHOD FIRST FIRST SELECTED DATA TRANSFER SHIFT CLOCK MODE SELECTED FROM FOUR THREE INTERNAL EXTERNAL "LOCK DIAGRAM
)NTERNAL DATA
FIRST
FIRST 4RANSFER DIRECTION SELECT 3)/& 3)/% 3#+%
3HIFT DIRECTION 3ERIAL DATA REGISTER
INPUT 3YNCHRONIZER
OUTPUT 3YNCHRONIZER
3ERIAL MODE REGISTER /VERFLOW
.OTE /UTPUT ENABLE /UTPUT ENABLE 03#+ .OTE )NTERNAL CLOCK PULSE #ONTROLLER 3HIFT CLOCK PULSE SELECT
#LEAR 3HIFT CLOCK COUNTER
.OTE OUTPUTS SERVE 5!24 OUTPUTS 4HEY USED OUTPUTS SERIAL WHEN 23%, 5!24 2EGISTER LIST
(!2$7!2% #/.&)'52!4)/.
BITS !DDRESS !DDRESS 3ERIAL MODE REGISTER 3ERIAL DATA REGISTER
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION REGISTERS DETAIL EACH REGISTER DESCRIBED BELOW
!DDRESS !DDRESS
3ERIAL MODE REGISTER USED CONTROL SERIAL
!DDRESS 3)/& 3)/% 3#+%
)NITIAL VALUE
;"IT 3)/& 3ERIAL INTERRUPT REQUEST FLAG 4HIS USED INDICATE SERIAL TRANSFER STATE MEANING EACH WHEN READING FOLLOWS 3ERIAL DATA TRANSFER TERMINATED 3ERIAL DATA TRANSFER TERMINATED
.OTE THAT ALWAYS READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION READ THIS WHEN INTERRUPT ENABLED 3)/% INTERRUPT REQUEST OUTPUT MEANING EACH WHEN WRITING FOLLOWS #LEARS THIS 5NCHANGES THIS OTHER BITS UNAFFECTED
TRANSFER DECISION MADE EITHER THIS ;"IT 3)/% 3ERIAL INTERRUPT ENABLE 4HIS USED ENABLE SERIAL INTERRUPT REQUEST 3ERIAL INTERRUPT OUTPUT DISABLED 3ERIAL INTERRUPT OUTPUT ENABLED
;"IT 3#+% 3HIFT CLOCK OUTPUT ENABLE 4HIS USED CONTROL SHIFT CLOCK PINS 'ENERAL PURPOSE PORT INPUT SHIFT CLOCK OUTPUT
7HEN USING EXTERNAL CLOCK ALWAYS INPUT 4HIS VALID WHEN 23%, 5!24
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"IT 3ERIAL DATA OUTPUT ENABLE 4HIS USED CONTROL OUTPUT SERIAL 'ENERAL PURPOSE PORT SERIAL DATA OUTPUT
7HEN USING ALWAYS INPUT 4HIS VALID WHEN 23%, 5!24 ;"ITS 3HIFT CLOCK SELECT BITS 4HESE BITS USED SELECT SERIAL SHIFT CLOCK MODES -ODE )NTERNAL SHIFT CLOCK MODE )NTERNAL SHIFT CLOCK MODE )NTERNAL SHIFT CLOCK MODE %XTERNAL SHIFT CLOCK MODE #LOCK RATE INSTRUCTION CYCLE INSTRUCTION CYCLE INSTRUCTION CYCLE /UTPUT /UTPUT /UTPUT )NPUT
;"IT 4RANSFER DIRECTION SELECT SERIAL DATA TRANSFER THIS USED DECIDE TRANSFER DIRECTION FROM LEAST SIGNIFICANT FIRST FIRST FROM MOST SIGNIFICANT FIRST FIRST FIRST FIRST
.OTE THAT WHEN THIS REWRITTEN AFTER WRITING DATA DATA COME INVALID ;"IT 3ERIAL TRANSFER START 4HIS USED START SERIAL TRANSFER AUTOMATICALLY CLEARED WHEN TRANSFER TERMINATED 3TOPS SERIAL TRANSFER 3TARTS SERIAL TRANSFER
"EFORE STARTING TRANSFER ENSURE THAT TRANSFER STOPPED !DDRESS !DDRESS 3ERIAL DATA REGISTER 4HIS REGISTER USED HOLD SERIAL TRANSFER DATA WRITE DATA THIS REGISTER DURING SERIAL OPERATION
!DDRESS )NITIAL VALUE 88888888"
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION OPERATION OPERATION SERIAL DESCRIBED BELOW /UTLINE 4HIS MODULE CONSISTS SERIAL MODE REGISTER SERIAL DATA ISTER SERIAL OUTPUT DATA OUTPUT SERIAL RIAL OUTPUT SYNCHRONIZATION WITH FALLING EDGE SERIAL SHIFT CLOCK PULSE GENERATED FROM INTERNAL EXTERNAL CLOCK SERIAL INPUT DATA INPUT SERIAL FROM SERIAL INPUT RISING EDGE SERIAL SHIFT CLOCK PULSE
3HIFT CLOCK PULSE
3HIFT CLOCK PULSE
CONVERSION
3ERIAL OUTPUT
3HIFT CLOCK PULSE
3HIFT CLOCK PULSE
CONVERSION
3ERIAL INPUT
/PERATION MODES SERIAL THREE INTERNAL SHIFT CLOCK MODES EXTERNAL SHIFT CLOCK MODE ACCORDING TYPE SHIFT CLOCK WHICH SPECIFIED -ODE SWITCHING CLOCK SELECTION SHOULD MADE WITH SERIAL STOPPED )NTERNAL SHIFT CLOCK MODE /PERATION PERFORMED INTERNAL CLOCK SHIFT CLOCK PULSE WITH DUTY OUTPUT FROM SYNCHRONOUS TIMING OUTPUT $ATA TRANSFERRED EVERY CLOCK PULSE %XTERNAL SHIFT CLOCK MODE $ATA TRANSFERRED EVERY CLOCK PULSE SYNCHRONIZATION WITH EXTERNAL SHIFT CLOCK PULSE INPUT FROM TRANSFER SPEED FROM INSTRUCTION CYCLES 7HEN INSTRUCTION CYCLE OSCILLATION TRANSFER SPEED WRITE DATA DURING SERIAL OPERATION THER MODE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
)NTERRUPT FUNCTIONS 4HIS MODULE OUTPUT INTERRUPT REQUEST OUTPUT INTER RUPT REQUEST 3)/% ENABLE INTERRUPT THEN INTERRUPT FLAG 3)/& AFTER DATA TRANSFER TERMINATED
3HIFT STARTSTOP TIMING $ATA TRANSFER STARTS WHEN WRITTEN STOPS WHEN WRITTEN 7HEN DATA TRANSFER TERMINATED TOMATICALLY CLEARED WHICH STOPS OPERATION )NTERNAL SHIFT CLOCK MODE FIRST ;7HEN TRANSFER TERMINATED=
3)/&
;7HEN TRANSFER SUSPENDED=
3)/&
%XTERNAL SHIFT CLOCK MODE FIRST ;7HEN TRANSFER TERMINATED=
3)/&
(!2$7!2% #/.&)'52!4)/.
2ESOURCES ;7HEN TRANSFER SUSPENDED=
3)/&
.OTE 7HEN DATA WRITTEN OUTPUT DATA CHANGES FALLING EDGE EXTERNAL CLOCK PULSE 3HIFT 3TART3TOP 4IMING
)NPUTOUTPUT SHIFT TIMING $ATA OUTPUT FROM SERIAL OUTPUT FALLING EDGE SHIFT CLOCK PULSE INPUT FROM SERIAL INPUT RISING EDGE SHIFT CLOCK PULSE FIRST
OUTPUT INPUT
FIRST
OUTPUT INPUT
INDICATE INPUT DATA INDICATE OUTPUT DATA
)NPUT/UTPUT 3HIFT 4IMING
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
%XTERNAL )NTERRUPT
EDGES EXTERNAL INTERRUPT SOURCES DETECTED CORRE SPONDING FLAG INTERRUPT GENERATED SAME TIME FLAG INTERRUPTS RELEASE 34/0 3,%%0 MODE "LOCK DIAGRAM
0).4 007#).4
2EGISTERS
BITS !DDRESS %XTERNAL INTERRUPT CONTROL REGISTER
$ESCRIPTION REGISTERS %XTERNAL INTERRUPT CONTROL REGISTER CONTROLS INTERRUPTS PINS !DDRESS
!DDRESS
)NITIAL VALUE
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"IT %XTERNAL INTERRUPT REQUEST FLAG 7HEN EDGE SPECIFIED BITS INPUT 7HEN INTERRUPT REQUEST OUTPUT THIS MEANING EACH READ FOLLOWS 3PECIFIED EDGE INPUT 3PECIFIED EDGE INPUT OUTPUT
ALWAYS READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION READ MEANING EACH WRITTEN FOLLOWS #LEARS THIS 5NCHANGES THIS OTHER BITS UNAFFECTED
;"ITS %DGE POLARITY MODE SELECT BITS 4HESE BITS USED CONTROL INPUT EDGE POLARITY MODE EDGE DETECTED 2ISING EDGE &ALLING EDGE "OTH EDGE MODE
;"IT )NTERRUPT ENABLE 4HIS USED ENABLE EXTERNAL INTERRUPT REQUEST $ISABLES INTERRUPT REQUEST %NABLES INTERRUPT REQUEST SETTING
;"IT %XTERNAL INTERRUPT REQUEST FLAG 7HEN EDGE SPECIFIED BITS INPUT 7HEN INTERRUPT REQUEST OUTPUT THIS MEANING EACH READ FOLLOWS 3PECIFIED EDGE INPUT 3PECIFIED EDGE INPUT OUTPUT
ALWAYS READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION READ MEANING EACH WRITTEN FOLLOWS #LEARS THIS 5NCHANGES THIS OTHER BITS UNAFFECTED
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"ITS %DGE POLARITY MODE SELECT BITS USED CONTROL INPUT EDGE POLARITY MODE EDGE DETECTED 2ISING EDGE &ALLING EDGE "OTH EDGE MODE
;"IT )NTERRUPT ENABLE USED ENABLE EXTERNAL INTERRUPT REQUEST $ISABLES INTERRUPT REQUEST %NABLES INTERRUPT REQUEST SETTING
0RECAUTIONS EXTERNAL INTERRUPT CIRCUIT 7HEN ENABLING INTERRUPT AFTER CLEARING RESET ALWAYS CLEAR INTERRUPT FLAG SIMULTANEOUSLY INTERRUPT REQUEST OUTPUT IMMEDIATELY WHEN TERRUPT FLAGS
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
#ONTROLLERDRIVER
CONTROLLERDRIVER CONSISTS DISPLAY CONTROLLER THAT GENERATES SEGMENT COMMON SIGNALS ACCORDING DISPLAY DATA MEMORY DATA SEGMENT COMMON DRIVERS THAT DRIVE PANEL DIRECTLY $IRECT DRIVING &OUR COMMON OUTPUTS SEGMENT OUTPUTS BYTE DISPLAY DATA MEMORY SELECTED DUTY USED GENERAL PURPOSE PORTS OPTION "LOCK DIAGRAM
-AIN CLOCK CONTROL REGISTER ,#$2
0OWER SUPPLY
0RESCALER 4IMING CONTROLLER #OMMON DRIVER
)NTERNAL DISPLAY BYTES
#IRCUIT COMMUTAT
3EGMENT DRIVER
#ONTROLLER
$RIVER
#ONTROLLER$RIVER "LOCK $IAGRAM
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
2EGISTERS
BITS !DDRESS !DDRESS ,#$2 3%'2 CONTROL REGISTER 3EGMENT OUTPUT SELECT REGISTER
$ESCRIPTION REGISTERS DETAIL CONTROL REGISTER DESCRIBED BELOW !DDRESS ,#$2 !DDRESS 3%'2 CONTROL REGISTER ,#$2
!DDRESS 63%,
)NITIAL VALUE
;"ITS !LWAYS WRITE ;"IT 63%, $RIVE POWER CONTROL 4HIS USED CONTROL DRIVE POWER #ONNECTION INTERNAL RESISTOR DIVIDED VOLTAGE ENTERS STATE #ONNECTION INTERNAL RESISTOR DIVIDED VOLTAGE ENTERS STATE ;"IT $ISPLAY DISPLAY BLANKING SELECT 4HIS USED SELECT DISPLAY DISPLAY BLANKING SEGMENT OUTPUT DISPLAY BLANKING CONFORMING WAVEFORM $ISPLAY $ISPLAY BLANKING
;"ITS $ISPLAY MODE SELECT 4HESE BITS USED SELECT DISPLAY MODE MODE ACCORDING FOLLOWING TABLE $ISPLAY MODE STOP DUTY OUTPUT MODE DUTY OUTPUT MODE DUTY OUTPUT MODE .UMBER TIME DIVISIONS
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
;"ITS &LAME 0ERIOD #LOCK CYCLE SELECT 4HESE BITS USED SELECT CLOCK CYCLE FRAME FREQUENCY SHOWN BELOW #ALCULATE OPTIMUM FRAME FREQUENCY REGISTER ACCORDING MODULE &RAME FREQUENCY .UMBER TIME DIVISIONS #LOCK FREQUENCY
!DDRESS ,#$2 !DDRESS 3%'2
3EGMENT OUTPUT SELECT REGISTER 3%'2
!DDRESS
)NITIAL VALUE
;"ITS 0ORTSEGMENT OUTPUT SELECT 3ELECTS PORT FUNCTION 3ELECTS SEGMENT OUTPUT 3ELECTION 03%' 03%' 3ELECTION 03%' 03%' 3ELECTION 03%' 03%' 3ELECTION 03%' 3ELECTION 03%'
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
DISPLAY CONTROLLERDRIVER CONTAINS GENERATING MENT OUTPUT SIGNAL DATA THIS AUTOMATICALLY READ SYNCHRO NIZATION WITH COMMON SIGNAL SELECT TIMING WAVEFORM CORRE SPONDING THIS DATA OUTPUT FROM SEGMENT OUTPUT SEGMENT SIGNALS CORRESPOND LOCATIONS DISPLAY %ACH LOCATION SYNCHRONIZATION WITH COMMON SIGNAL SELECT TIMING BITS WITH BITS WITH BITS WITH BITS WITH VALUE EACH SIGNAL CONVERTED VOLTAGE SIGNAL CONVERTED OUTPUT EVER RESET HIGH IMPEDANCE BECAUSE THEY ALSO SERVE PORTS WAVEFORM OUTPUT FROM SEGMENT PINS IRRESPECTIVE ERATION 4HEREFORE READING WRITING FROM DISPLAY POSSIBLE TIMING 7HEN USING GENERAL PURPOSE OUTPUT PORTS UPPER BYTES USUALLY USED
!DDRESS
-ULTIPLEXED WITH PORT
-ULTIPLEXED WITH PORT
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
/PERATION &IRST WRITE DATA DISPLAYED DISPLAY 4HEN VALUE CORRESPONDING PANEL USED CONTROL REGISTER DRIVE WAVEFORM OUTPUT ACCORDING DATA DISPLAY WHEN CLOCK PULSE SUPPLIED HIGH SPEED CLOCK SPEED CLOCK SELECTED CLOCK SOURCE CLOCK SOURCE SWITCHED DURING DISPLAY (OWEVER DISPLAY TENDS FLICKER SWITCHING 4HEREFORE BEST STOP DISPLAY BLANKING BEFORE SWITCHING CLOCK DISPLAY DRIVE OUTPUT FRAME WAVEFORM COMBINATION BIAS DUTY SHOWN BELOW POSSIBLE .OTE THAT COMBINATION BIAS DUTY SHOULD USED %XAMPLES WAVEFORMS SHOWN FOLLOWING PAGES DUTY BIAS BIAS 2ECOMMENDED MODE !PPLICATION DISABLED DUTY DUTY
DUTY MODE OUTPUT WAVEFORMS LECTIVE LEVEL OUTPUT WAVEFORM ALSO CONFORMING WAVE FORM DUTY 7HEN OPERATION TERMINATED BOTH COMMON SEGMENT OUTPUT VEFORMS LEVEL (OWEVER WHEN SPECIFIED ERAL PURPOSE PORT MASK OPTION SEGMENT DATA OUTPUT
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
DRIVE OUTPUT WAVEFORM 7AVEFORM BIAS DUTY
FRAME $ISPLAY %XAMPLE 7AVEFORM #ORRESPONDING $ATA
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
7AVEFORM BIAS DUTY
FRAME
%XAMPLE 7AVEFORM #ORRESPONDING $ATA $ISPLAY
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
7AVEFORM BIAS DUTY
FRAME
%XAMPLE 7AVEFORM #ORRESPONDING $ATA $ISPLAY
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
6OLTAGE SETTING POWER PINS DRIVING VOLTAGES POWER PINS SHOWN BELOW BIAS BIAS 6,#$ 6,#$ 6,#$ 6,#$ 6,#$ 6,#$
6,#$ OPERATING VOLTAGE CONNECTION EXAMPLE SUPPLY POWER DRIVE SHOWN &IGURE
6,#$
6,#$
BIAS
BIAS
#ONNECTION %XAMPLES 3UPPLY 0OWER $RIVING .OTE DUTY WHEN USING EXTERNAL DIVIDING RESISTOR LADDER CIRCUIT SHORT CIRCUIT PINS "UILT VOLTAGE DIVIDING RESISTOR BUILT VOLTAGE DIVIDING RESISTORS CONNECTED SHOWN &IGURE 7RITING 63%, CONNECTS BUILT VOLTAGE DIVIDING RESISTORS 4HEREFORE WRITE 63%, CONNECT RESISTORS CONNECT RESISTORS BUILT VOLTAGE DIVIDING CIRCUIT CONNECTED THROUGH TRAN SISTOR WITHIN CHIP 4HEREFORE CURRENT FLOWING INTO RESISTOR WHEN ,#$# STOPS
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
63%, ,#$# ENABLED )NTERNAL EQUIVALENT CUIT "UILT 6OLTAGE $IVIDING RESISTORS
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
4IME BASE 4IMER
4HIS TIMER BINARY COUNTER USES CLOCK PULSE WITH CILLATION MAIN CLOCK SELECTED FROM FOUR INTERVAL TIMES 4HIS FUNCTION CANNOT USED WHEN MAIN CLOCK STOPPED "LOCK DIAGRAM
4"4#
COUNTER
4")% 4")&
)NTERRUPT QUEST
4"4# CLOCK PULSE WITH OSCILLATION MAIN CLOCK OSCILLATION 2EGISTER LIST TIME BASE TIMER TIME BASE TIMER CONTROL REGISTER 4"#2
BITS !DDRESS 4"#2 4IME BASE TIMER CONTROL REGISTER
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION REGISTERS DETAIL TIME BASE TIMER CONTROL REGISTER 4"#2 DESCRIBED BELOW
!DDRESS 4"#2
4IME BASE TIMER CONTROL REGISTER 4"#2
!DDRESS 4")% 4")&
)NITIAL VALUE 888"
;"IT 4")% )NTERVAL TIMER INTERRUPT ENABLE 4HIS USED ENABLE INTERRUPT INTERVAL TIMER $ISABLES INTERVAL INTERRUPT %NABLES INTERVAL INTERRUPT
;"IT 4")& )NTERVAL TIMER OVERFLOW 7HEN WRITING THIS USED CLEAR INTERVAL TIMER OVERFLOW FLAG #LEARS INTERVAL TIMER OVERFLOW FLAG OPERATION
7HEN READING THIS INDICATES THAT INTERVAL TIMER OVERFLOW OCCURRED INTERVAL TIMER OVERFLOW )NTERVAL TIMER OVERFLOW
READ WHEN 2EAD -ODIFY 7RITE INSTRUCTION READ 4")& WHEN 4")% INTERRUPT REQUEST OUTPUT 4HIS CLEARED UPON RESET ;"IT 4IME BASE TIMER CLEAR 4HIS USED CLEAR TIME BASE TIMER #LEARS TIME BASE TIMER OPERATION
4HIS ALWAYS READ ;"ITS )NTERVAL TIME SPECIFICATION BITS 4HESE BITS USED SPECIFY INTERVAL TIMER CYCLE )NTERVAL TIME
6ALUE ;MS= ;MS= ;MS= CLOCK FREQUENCY
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
7ATCHDOG 4IMER 2ESET
WATCHDOG RESET GENERATED USING OUTPUT TIME BASED TIMER CLOCK PULSE "LOCK DIAGRAM
COUNTER
3TART 2ESET CONTROL
4IME BASE TIMER
2EGISTERS WATCHDOG TIMER RESET WATCHDOG TIMER CONTROL REGISTER 7$4%
BITS !DDRESS 7$4% 7ATCHDOG TIMER CONTROL REGISTER
$ESCRIPTION REGISTER DETAIL WATCHDOG TIMER CONTROL REGISTER 7$4% DESCRIBED BELOW !DDRESS 7$4% 7ATCHDOG TIMER CONTROL REGISTER 7$4"IT !DDRESS )NITIAL VALUE 88888888"
;"ITS 7ATCHDOG TIMER CONTROL BITS 4HESE BITS USED CONTROL WATCHDOG TIMER &IRST WRITE ONLY AFTER RESET /THER THAN ABOVE 3ECOND LATER WRITE /THER THAN ABOVE #LEARS WATCHDOG TIMER COUNTER OPERATION 3TARTS WATCHDOG TIMER OPERATION
WATCHDOG TIMER STOPPED ONLY RESET 4HESE BITS READ
(!2$7!2% #/.&)'52!4)/.
2ESOURCES
$ESCRIPTION OPERATION WATCHDOG TIMER ENABLES DETECTION PROGRAM MALFUNCTION 3TARTING WATCHDOG TIMER WATCHDOG TIMER STARTS WHEN WRITTEN WATCHDOG TIMER TROL BITS #LEARING WATCHDOG TIMER 7HEN WRITTEN WATCHDOG TIMER CONTROL BITS AFTER START WATCH TIMER CLEARED COUNTER WATCHDOG TIMER CLEARED WHEN CHANGING STANDBY MODE 34/0 3,%%0 7!4#( 7ATCHDOG TIMER RESET WATCHDOG TIMER CLEARED WITHIN TIME GIVEN TABLE BELOW WATCHDOG TIMER RESET OCCURS RESET CHIP INTERNALLY 4IME BASE TIMER CYCLE -INIMUM TIME -AXIMUM TIME !PPROX !PPROX 3TOPPING WATCHDOG TIMER /NCE STARTED WATCHDOG TIMER WILL STOP UNTIL RESET OCCURS
/0%2!4)/.
#LOCK 0ULSE 'ENERATOR 2ESET )NTERRUPT POWER #ONSUMPTION -ODES 3TATES 3LEEP 3TOP 2ESET
/0%2!4)/.
OPERATION DESCRIBED BELOW
#LOCK 0ULSE 'ENERATOR
SERIES MICROCONTROLLERS CONTAIN SYSTEM CLOCK PULSE GENERATOR CRYSTAL OSCILLATOR CONNECTED PINS GENERATE CLOCK PULSES #LOCK PULSES ALSO SUPPLIED INTERNALLY INPUTTING EXTERNALLY GENERATED CLOCK PULSES SHOULD KEPT OPEN
8TAL /0%.
#LOCK 0ULSE 'ENERATOR
/0%2!4)/.
2ESET
DETAIL RESET OPERATION RESET SOURCES DESCRIBED BELOW
2ESET /PERATION
7HEN RESET CONDITIONS OCCUR SERIES MICROCONTROLLERS SUSPEND CURRENTLY EXECUTING STRUCTION ENTER RESET STATE CONTENTS WRITTEN CHANGE BEFORE AFTER RESET EVER RESET OCCURS DURING WRITING LONG DATA DATA WRITTEN UPPER BYTES WRITTEN LOWER BYTES RESET OCCURS AROUND WRITE TIMING CONTENTS ADDRESSES BEING WRITTEN SURED 7HEN RESET CONDITIONS CLEARED SERIES MICROCONTROLLERS RELEASED FROM RESET STATE START OPERATION AFTER FETCHING MODE DATA FROM ADDRESS &&&$( UPPER BYTES RESET TORS FROM ADDRESS &&&%( LOWER BYTES FROM ADDRESS &&&&( THAT ORDER &IGURE SHOWS FLOW CHART RESET OPERATION
2ESET CLEAR
&ETCHES MODE DATA FROM ADDRESS &&&$( &ETCHES RESET VECTORS FROM ADDRESSES &&&%( &&&&( &ETCHES INSTRUCTION CODES FROM RESET VECTORS EXECUTES INSTRUCTION
%XECUTES NEXT INSTRUCTION
/UTLINE 2ESET /PERATION &IGURE INDICATES STRUCTURE DATA STORED ADDRESSES &&&$( &&&%( &&&&(
&&&&( &&&%( &&&$( ,OWER BITS RESET VECTOR 5PPER BITS RESET VECTOR -ODE DATA
%NTER ADDRESS WHERE INSTRUCTION WHICH WILL EXECUTED FIRST AFTER RESET CLEARED STORED
2ESERVED ALWAYS
2ESET 6ECTOR 3TRUCTURE
/0%2!4)/.
2ESET 3OURCES
SERIES MICROCONTROLLERS HAVE FOLLOWING RESET SOURCES %XTERNAL 3PECIFICATION SOFTWARE 0OWER 7ATCHDOG FUNCTION 7HEN LEVEL INPUT 7HEN WRITTEN STANDBY CONTROL REGISTER 0OWER WHEN POWER RESET OPTION SELECTED 7HEN WATCHDOG FUNCTION ENABLED WATCHDOG CONTROL REGISTER REACCESS THIS REGISTER OBTAINED WITHIN SPECIFIED TIME
7HEN STOP MODE CLEARED RESET POWER RESET OPTIONAALLY SELECTED OPERATION STARTED AFTER ELAPSE OSCILLATION STABILIZATION TIME DETAILS PAGE
/0%2!4)/.
)NTERRUPT
INTERRUPT CONTROLLER READY ACCEPT INTERRUPTS WHEN INTERRUPT REQUEST OUTPUT FROM INTERNAL RESOURCES EXTERNAL INTERRUPT INPUT TEMPORARILY SUSPENDS CURRENTLY EXECUTING INSTRUCTION EXECUTES INTERRUPT PROCESSING PROGRAM &IGURE SHOWS INTERRUPT PROCESSING FLOW CHART
)NTERNAL -AIN PROGRAM 2EGISTER FILE 2ESET CLEAR )0,! #HECK 2!,EVEL COMPARATOR 3OURCE 2ESOURCE )NTERRUPT CONTROLLER RESTORED #OMPARATOR )NITIALIZE INTERRUPT -AIN PROGRAM EXECUTION SAVED ,EVEL DECIDED )NTERRUPT GENERATION )NTERRUPT PROCESSING UPDATED
#LEAR REQUEST )NTERRUPT PROCESSING 2ESTORE 2%4)
%NABLE
)NTERRUPT PROCESSING &LOWCHART INTERRUPTS DISABLED AFTER RESET CLEARED 4HEREFORE INITIALIZE INTERRUPTS MAIN PROGRAM %ACH RESOURCE GENERATING INTERRUPTS INTERRUPT LEVEL SETTING REGISTERS INTERRUPT CONTROLLER CORRESPONDING THESE INTERRUPTS INITIALIZED LEVELS INTERRUPTS INTERRUPT LEVEL SETTING REGISTERS INTERRUPT CONTROLLER INTERRUPT LEVEL FROM WHERE INDICATES HIGHEST LEVEL SECOND HIGHEST LEVEL ,EVEL INDICATES THAT INTERRUPT OCCURS INTERRUPT REQUEST THIS LEVEL CANNOT ACCEPTED !FTER SETTING RESOURCES MAIN PROGRAM EXECUTES VARIOUS CONTROLS )NTERRUPTS GENERATED FROM RESOURCES HIGHEST PRIORITY INTERRUPT REQUESTS IDENTIFIED FROM THOSE OCCURRING SAME TIME INTERRUPT CONTROLLER TRANSFERRED THEN CHECKS CURRENT INTERRUPT LEVEL STATUS FLAG STARTS INTERRUPT PROC ESSING PERFORMS INTERRUPT PROCESSING SAVE CONTENTS CURRENT STACK FETCHES ENTRY ADDRESSES INTERRUPT PROGRAM FROM INTERRUPT VECTORS !FTER UPDATING VALUE REQUIRED STARTS EXECUTING INTERRUPT PROCESSING ROUTINE #LEAR INTERRUPT SOURCES PROCESS INTERRUPTS INTERRUPT PROCESSING ROUTINE &INALLY RESTORE VALUES SAVED 2%4) INSTRUCTION STACK RETURN INTERRUPTED INSTRUC TION .OTE 5NLIKE FAMILY SAVED STACK INTERRUPT TIME
/0%2!4)/.
4ABLE LISTS RELATIONSHIPS BETWEEN EACH INTERRUPT SOURCE INTERRUPT VECTOR 4ABLE )NTERRUPT 3OURCES )NTERRUPT 6ECTORS )NTERRUPT SOURCE %XTERNAL INTERRUPT %XTERNAL INTERRUPT TIMER 0ULSE WIDTH COUNT TIMER 5!24 SERIAL )NTERVAL TIMER 5NUSED 5NUSED 5NUSED )21! 5NUSED )21" 5NUSED 5PPER VECTOR ADDRESS &&&!( &&&( &&&( &&&( &&&( &&&( &&%%( &&%#( &&%!( &&%( &&%( &&%( ,OWER VECTOR ADDRESS &&&"( &&&( &&&( &&&( &&&( &&&( &&%&( &&%$( &&%"( &&%( &&%( &&%(
/0%2!4)/.
POWER #ONSUMPTION -ODES
SERIES MICROCONTROLLERS HAVE STANDBY MODES SLEEP STOP REDUCE POWER SUMPTION 7RITING STANDBY CONTROL REGISTER 34"# GIVES TRANSITION THESE STANDBY MODES SECTION SETTING RELEASING EACH MODE 7HETHER OSCILLATION STABILIZATION PERIOD REQUIRED RELEASE FROM EACH POWER CONSUMPTION MODE DEPENDS MASK OPTION POWER RESET PAGE 4ABLE POWER #ONSUMPTION -ODE %ACH #LOCK -ODE
&UNCTION -AIN CLOCK 3UBCLOCK )NSTRUCTION 2/2!)/ 4IME BASE TIMER 070ULSE WIDTH COUNTER
/PERATION MODE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE 3,%%0 /PERATE /PERATE 3TOP (OLD (OLD /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE /PERATE 3TOP 34/0 3TOP /PERATE 3TOP (OLD (OLD 3TOP 3TOP 3TOP 3TOP 3TOP 3TOP /PERATE 3TOP
2ESOURCE
5!24 ,#$# %XTERNAL INTERRUPT 7ATCHDOG TIMER
/0%2!4)/.
3TATES 3LEEP 3TOP 2ESET
3LEEP 3TOP STATE IMMEDIATELY BEFORE SLEEP STATE HELD STATE IMMEDIATELY BEFORE STOP STATE HELD WHEN STOP MODE STARTED STANDBY CONTROL REGISTER 34"# IMPEDANCE OUTPUT INPUT OUTPUT PINS GOES (IGH WHEN IMPEDANCE RESOURCE PINS EXCLUDING PINS PULL OPTION GOES (IGH 4ABLE 3TATE
NAME .ORMAL 0ORT 2ESOURCE OUTPUT )NPUT OSCILLATION 3LEEP 0ORT 2ESOURCE OUTPUT )NPUT OSCILLATION 3TOP 0ORT 2ESOURCE OUTPUT (IGH INPEDANCE
OUTPUT -ODE INPUT 2ESET INPUT 0ORT 0ORT )NPUT 0ORTRESOURCE 3TOP (IGH IMPEDANCE
2ESOURCE OUTPUT (IGH IMPEDANCE
OUTPUT -ODE INPUT 2ESET INPUT (IGH IMPEDANCE
(IGH IMPEDANCE
(IGH IMPEDANCE
2ESET (IGH IMPEDANCE
STATE EACH SERIES MICROCONTROLLERS SLEEP STOP RESET FOLLOWS
2ESET
03%' 03%' 03%' 03%' 0).4 03#+
)NPUT OSCILLATION /UTPUT OSCILLATION -ODE INPUT 2ESET INPUT
(IGH IMPEDANCE
0ORT )NPUT (IGH IMPEDANCE
/UTPUT OSCILLATION /UTPUT OSCILLATION -ODE INPUT 2ESET INPUT 0ORT 0ORT )NPUT 0ORTRESOURCE -ODE INPUT 2ESET INPUT 0ORT 0ORT )NPUT 0ORTRESOURCE
INTERNAL INPUT LEVEL FIXED PREVENT LEAKAGE OPEN INPUT 0INS WHICH PULL OPTION SELECTED ENTER PULL STATE
RESET SERVE OUTPUT DEPENDING OPTION SETTING
WHEN EDGE DETECTION EXTERNAL INTERRUPT SELECTED ONLY EXTERNAL INTERRUPT INPUT EVEN STOP MODE
).3425#4)/.3
,EGEND 4RANSFER )NSTRUCTIONS /PERATION )NSTRUCTIONS "RANCH )NSTRUCTIONS /THER )NSTRUCTIONS &AMILY )NSTRUCTION
).3425#4)/.3
,EGEND
3YMBOL DIRN -EANING %XTENDED ADDRESSING ADDRESSES &&&& $IRECT ADDRESSING ADDRESSES $IRECT ADDRESSING POSITION 2ELATIVE ADDRESSING BITS )MMEDIATE ADDRESSING VECTOR ADDRESSING 5PPER BYTE ,OWER BYTE ,OWER BYTE 2EGISTER INDIRECT ADDRESSING )NDEX WITH OFFSET %XTRA POINTER ACCUMULATOR -EMORY REGISTERS )MMEDIATE DATA BITS )MMEDIATE DATA BITS 6ECTOR NUMBER /FFSET 2EMAINDER
&LAG .:6# #HANGED EXECUTION INSTRUCTION CHANGED 2ESET EXECUTION INSTRUCTION EXECUTION INSTRUCTION
).3425#4)/.3
4RANSFER )NSTRUCTIONS
-NEMONIC
DIR! )8OFF! EXT! !DIR )8OFF !EXT
/PERATION
.:6#
#ODE
)8OFF -/67 DIR! -/67 )8OFF! -/67 EXT! -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 -/67 37!0 !DIR )8OFF !EXT
3%4" DIRN #,2" DIRN 8#(7 8#(7 8#(7 8#(7 -/67
.OTES BYTE TRANSFER ONLY BYTES /PERANDS MORE OPERAND INSTRUCTIONS SHOULD STORED ORDER DESIGNATED -NEMONIC /PPOSITE ORDER FAMILY
).3425#4)/.3
/PERATION )NSTRUCTIONS
-NEMONIC
!$$# !$$# !$$# !$$# !$$# !DIR )8OFF
DECIMAL DECIMAL
/PERATION
.:6#
#ODE
!$$#7 !$$# 35"# 35"# 35"# !DIR 35"# )8OFF 35"# 35"#7 35"# ).#7 ).#7 ).#7 $%#7 $%#7 $%#7 -5,5 $)65 !.$7
8/27 #-07 2/2# 2/,# !DIR )8OFF
!DIR )8OFF !DIR )8OFF
ADJUST ADDITION ADJUST SUBTRACTION
!DIR )8OFF
)8OFF ).#7 $%#7
).3425#4)/.3
"RANCH )NSTRUCTIONS
-NEMONIC
":"%1 ".:".% "#",/ ".#"(3 DIRBREL DIRBREL #!,,6 #!,, 8#(7 2%4)
THEN THEN THEN THEN THEN
/PERATION
0#REL 0#REL 0#REL 0#REL 0#REL
.:6#
#ODE
THEN 0#REL THEN 0#0#REL THEN 0#0#REL DIRB THEN 0#0#REL DIRB THEN 0#0#REL VECTOR CALL SUBROUTINE CALL RETURN FROM SUBROUTINE RETURN FROM INTERRUPT
RESTORE
).3425#4)/.3
/THER )NSTRUCTIONS
-NEMONIC
053(7 0/07 053(7 0/07 #,2# 3%4# #,2) 3%4)
/0%2!4)/.
/PERATION
.:6#
#ODE
).3425#4)/.3
&AMILY )NSTRUCTION
-!3+ /04)/.3
-!3+ /04)/.3
4ABLE -ASK /PTIONS
-ODEL 3PECIFICATION METHOD 3ELECT WHEN ORDERING MASK %02/- WRITER &IXED -"06
0ORT PULL RESISTOR SELECTED EACH EACH &IXED UNAVAILABLE PINS
0ORT3EGMENT OUTPUT
SELECTED EVERY PINS
3EGMENT OUTPUT
3EGMENT OUTPUT
0OWER RESET 0OWER RESET AVAILABLE 0OWER RESET UNAVAILABLE SELECTED !VAILABLE
3ELECTION MAIN CLOCK OSCILLATION STABILIZATION TIME
!BOUT ABOUT !BOUT ABOUT SELECTED FIXED
2ESET OUTPUT 2ESET OUTPUT AVAILABLE 2ESET OUTPUT UNAVAILABLE SELECTED /UTPUT AVAILABLE
MAIN CLOCK OSCILLATION STABILIZATION TIME GENERATED DIVIDING MAIN CLOCK OSCILLATION 3INCE OSCILLATION CYCLE UNSTABLE IMMEDIATELY AFTER OSCILLATION STARTS TIME THIS TABLE ONLY GUIDE
7HEN USING PORT VOLTAGE LARGER THAN SHOULD APPLIED
0ORTSEGMENT OUTPUT SWITCHING SHOULD SPECIFIED SAME MANNER PORT ALLOCATION SEGMENT OUTPUT SELECT REGISTER CONTROLLER DESCRIBED PAGE
!00%.$)8
!00%.$)8
!PPENDIX
!DDRESSES !DDRESS 2EAD7RITE 2EGISTER $ESCRIPTION REGISTER 0ORT DATA REGISTER 0ORT DATA REGISTER 0ORT DATA REGISTER
34"# 7$4# 4"#2
3TANDBY CONTROL REGISTER 7ATCHDOG TIMER CONTROL REGISTER 4IME BASE TIMER CONTROL REGISTER 0ORT DATA REGISTER 0ORT DATA REGISTER 0ORT DATA DIRECTION REGISTER
#.42 #/-2 2,"2 .##2
TIMER CONTROL REGISTER TIMER COMPARE REGISTER PULSE WIDTH CONTROL REGISTER PULSE WIDTH CONTROL REGISTER RELOAD BUFFER REGISTER NOISE REDUCTION CONTROL REGISTER
3ERIAL MODE REGISTER 3ERIAL DATA REGISTER
!00%.$)8
!DDRESS !DDRESS 2EAD7RITE 2EGISTER 3)$23/$2 $ESCRIPTION REGISTER 5!24 SERIAL MODE CONTROL REGISTER 5!24 SERIAL RATE CONTROL REGISTER 5!24 SERIAL STATUSDATA REGISTER 5!24 SERIAL DATA REGISTER 5!24 SERIAL MODE CONTROL REGISTER
62!,#$2 3%'2
%XTERNAL INTERRUPT CONTROL REGISTER $ISPLAY DATA 2!,#$ CONTROL REGISTER 3EGMENT OUTPUT SELECT REGISTER )NTERRUPT LEVEL SETTING REGISTER )NTERRUPT LEVEL SETTING REGISTER )NTERRUPT LEVEL SETTING REGISTER
.OTE INDECATES VACANT AREA USED
!00%.$)8
!PPENDIX 7RITING %02/&UNCTIONS EQUIVALENT -"-#! USED %02/- MODE !CCORDINGLY USER WRITE DATA WITH GENERAL PURPOSE %02/- WRITER USING DEDICATED ADAPTER .OTE THAT ELECTRI SIGNATURE MODE SUPPORTED 7RITING PROCEDURE %02/- WRITER -"-#! ,OAD PROGRAM DATA FROM &&&( %02/- WRITER .OTE THAT &&&&( OPERATION MODE EQUIVALENT &&&( %02/- MODE ,OAD OPTION DATA FROM %02/- WRITER NEXT PAGE CORRESPONDENCE EACH OPTION 7RITE DATA WITH %02/- WRITER MEMORY SPACE %02/- MODE SHOWN BELOW
ADDRESS NORMAL OPERATION ADDRESS %02/- MODE
0ROHIBITION
0ROHIBITION "&&( /PTION SETTING AREA "&&( 0ROHIBITION
6ACANT AREA 2EAD VALUE /PTION SETTING AREA 6ACANT AREA 2EAD VALUE
02/-
0ROGRAM AREA 02/&&&(
&&&&(
WRITER ADAPTER (!9!4/ 0ACKAGE NUMBER -"0&!DAPTER MODEL NUMBER
!00%.$)8
02/- /PTION
6ACANT 6ACANT 6ACANT 6ACANT 6ACANT 2ESET /UTPUT 2EADABLE 7RITABLE 2EADABLE 7RITABLE 2EADABLE 7RITABLE 2EADABLE 7RITABLE 2EADABLE 7RITABLE /SCILLATION STABILIZATION TIME !VAILABLE 5NAVAILABLE !VAILABLE 5NAVAILABLE 0OWER 2ESET
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
0ULL
0ULL
0ULL
0ULL
0ULL
0ULL
5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
0ULL
0ULL
0ULL
0ULL
0ULL
0ULL
5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE
6ACANT 2EADABLE 7RITABLE
VACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE 7RITABLE
6ACANT 2EADABLE WRITABLE
0ULL
0ULL
0ULL
0ULL
5NAVAILABLE 5NAVAILABLE 5NAVAILABLE 5NAVAILABLE !VAILABLE !VAILABLE !VAILABLE !VAILABLE
.OTE )NITIAL VALUE EACH
-!.5!, 2%,%!3$%6)#% $%3#2)04)/. )335% $!4% %$)4)/.
%$)4)/. )335% &EBRUARY
#(!.'% ./4)#2%,%!3%
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GENERAL CUSTOMERS
!002/6!,
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'REGG #ATHERINE PLEASE DISTRIBUTE HARD COPY FROM THIS FLOPPY DISK PERSON MARKED WITH ALSO OTHER CONCERNED PEOPLE NEEDED 2EGARDING .EW2EVISED DOCUMENTS PLEASE REPLACE WITH HAPPENS THAT THIS LASER OUTPUT VERSION REPLACES STAPLED PRINTED VERSION
&UJITSU -AR#OM
FURTHER INFORMATION PLEASE CONTACT *APAN &5*)435 ,)-)4%$ %LECTRONIC $EVICES )NTERNATIONAL /PERATIONS $EPARTMENT +!7!3!+) 0,!.4 +AMIKODANAKA .AKAHARA +AWASAKI +ANAGAWA *APAN .ORTH 3OUTH !MERICA &5*)435 -)#2/%,%#42/.)#3 3EMICONDUCTOR $IVISION .ORTH &IRST 3TREET *OSE %UROPE &5*)435 -)+2/%,%+42/.)+ 'MB( 3IEBENSTEIN $REIEICH "UCHSCHLAG 'ERMANY 4ELEX !SIA 0ACIFIC &5*)435 -)#2/%,%#42/.)#3 !3)! ,)-)4%$ "RAS "ASAH 2OAD 0LAZA 0ARK 3INGAPORE
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6ERSION 0AGE< .UMBERING 6ERSION !UTO< .UMBERING 0AGE< .UMBERING 0REFIX 3TARTING 0AGES !UTO< .UMBERING 3TREAM /UTLINE ,EVELS ,EVEL ,EVEL 0REFIX ,EVEL 0REFIX ,EVEL 0REFIX $ELTAS 2ESTART &IRST,EVEL
0/07 #,2) 3%4) -/67 -/67 -/67 -/67 8#(7 8#(7 8#(7 -/67 3%4" 3%4" 3%4" 3%4" #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 #!,,6 8#(7 -/67 -/67 -/67 -/67 -/67 -/67 -/67 EXT! -/67 DIR! -/67 )8D! -/67 $%#7 -/67 !EXT -/67 !DIR -/67 -/67 $%#7 ).#7 $%#7 ).#7 ).#7 #,2# 3%4# -/67 3%4" 3%4" 3%4" 3%4" #,2" #,2" #,2" #,2" #,2" -/67 !DIR !DIR #,2" #,2" $%#7 ).#7 0/07 8/27 !DIR !.$7 EXT! -/67 !EXT -/67 #,2"
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ADDR
2/,#
!$$#
35"#
2/2#
#-07
!$$#7
35"#7
8#(7
!$$#
35"#
!$$#
35"#
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!DIR
!DIR
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!$$#
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35"#
!$$#
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FUJITSU LIMITED
further information please contact: Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044)754-3753 Fax: (044)754-3329 North South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street Jose, 95134-1804, U.S.A. Tel: (408)922-9000 Fax: (408)432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103)690-0 Fax: (06103)690-122 Asia Pacific FUJITSU MICROELECTONICS ASIA PTE. LIMITED #05-08, Lorong Chuan Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
F9610 FUJITSU LIMITED Printed Japan

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