Type IXBD 4410-4411 IXBD 4412-4413 IXDP IXDP IXC. 10M35 IXC. 20M35 IXC
|
|
|
Top Searches for this datasheet
Smart Power Chip-sets manufactured IXYS designed interface with company's family Power MOSFET IGBT products order provide improved performance broad range power conversion motor control applications. IXYS focussed main areas: High/Low Side Driver Integrated Circuits which complement IXYS Power MOSFET IGBT that offer with either open closed loop protection power devices, such IXBD4410 Series. Regulator Controller circuits optimized specialized power supplies motor control applications. device satisfying this need would IXDP610 IXMS150. Other devices included IXYS product range series High Voltage Current Regulators Digital Deadtime Generator. IXYS experienced staff analog, digital power designers teamed together ensure accurate definition future generations integrated solutions satisfy needs power control, power conversion motion control markets. Using advantages compatibility CMOS IXYS HDMOSprocess, IXYS will continue integrate functions power control which still composed discretely.
Type IXBD 4410-4411 IXBD 4412-4413 IXDP IXDP IXC. 10M35 IXC. 20M35 IXC. 35M35 IXC. 10M35S IXC. 10M45S IXDP IXMS Description ISOSMARTHalf Bridge Driver Chipsets Inverter Interface Digital Deadtime Generator 3-Phase Controls switchable Current Regulator, mA/350 switchable Current Regulator, mA/350 switchable Current Regulator, mA/350 Switchable Current Regulator, mA/350 Switchable Current Regulator, mA/450 Compatible Digital Controller High Performance Dual Microstepping Controller Page
1998 IXYS rights reserved
Quality Reliability Program
IXYS committed philosophy that quality must built into product achieved only through inspection. IXYS designed implemented complete Quality Reliability Program insure that IXYS' products meet and/or exceed expectation customers. IXYS' Quality Reliability Program contains numerous audit points insure quality each process. Stringent electrical tests numerous environmental tests short long term with samples from product lots. Only after successful completion each step program will IXYS mark component. result: superior product your application requirements.
Production Flow Motion Control Products
100% VISUAL CHARACTERIZATION
HOLD PENDING SAMPLE TEST RESULTS
100% ELECTRICAL
STATIC BURN-IN
ELECTRICAL TEST
COMPONENT MARK
PACKING SHIPPING
OUTGOING QUALITY ASSURANCE
CUSTOMER BONDED STORES
SAMPLE LONG TERM EVALUATION
Typical Power Electronic Control System
1998 IXYS rights reserved
ISOSMARTHalf Bridge Driver Chipsets
Type Description Package Temperature Range
Features
IXBD4410PI IXBD4411PI IXBD4410SI IXBD4411SI IXBD4412PI IXBD4413PI
Full-Feature Low-Side Driver 16-Pin P-DIP Full-Feature High-Side Driver 16-Pin P-DIP Full-Feature Low-Side Driver 16-Pin Full-Feature High-Side Driver 16-Pin Basic Low-Side Driver Basic High-Side Driver 8-Pin P-DIP 8-Pin P-DIP
+85°C +85°C +85°C +85°C +85°C +85°C +70°C +70°C
IXBD4410KIT Full-Feature Chipset Eval. IXBD4412KIT Basic Chipset Evaluation
IXBD4410/IXBD4411 IXBD4412/IXBD4413 ISOSMARTchipsets designed control gates Power MOSFETs, Power IGBTs, that connected half-bridge (phaseleg) configuration driving multiple-phase motors, used applications that require half-bridge power circuits. IXBD4410/ IXBD4411 full-feature chipset consisting 16-Pin-DIP devices interfaced isolated small-signal ferrite pulse transformers. IXBD4412/IXBD4413 basic, low-cost chipset consisting 8-PinDIP devices interfaced isolated single pulse transformer. smallsignal transformers both chipsets provide greater than 1200 isolation. Even with commutating noise ambients greater than V/ns 1200 potentials, these chipsets establish error-free two-way communications between system ground-reference
IXBD4410 resp. IXBD4412 inverter output-reference IXBD4411 resp. IXBD4413. They incorporate undervoltage lockout, overcurrent desaturation shutdown protect IGBT Power MOSFET devices from damage. Both chipsets provide necessary gate drive signals fully control grounded-source low-side power device, well floating-source high-side power device. Additionally, IXBD4410/4411 chipset provides negative-going, off-state gate drive signal improved turn-off IGBTs, Power MOSFETs, system logiccompatible status fault output, FLT, indicate overcurrent desaturation, undervoltage VEE. During status fault, both chipsets keep their respective gate drive outputs off; IXBD4410/4411 IXBD4412/4413.
1200 greater low- high-side isolation. Drives Power Systems Operating mains dv/dt immunity greater than ±50V/ns Proprietary low- high-side leveltranslation communication On-chip negative gate-drive supply ensure Power MOSFET IGBT turn-off logic compatible HCMOS inputs with hysteresis Available either 16-Pin 16-Pin wide-body, small-outline plastic package (IXBD4410/4411) switching time with 1000 load; switching time with 10000 load propagation delay time peak output drive capability Self shut-down output response over-current short-circuit Under-voltage over-voltage lockout protection Protection from cross conduction half bridge Logic compatible fault indication from both high-side driver (XBD4410/4411).
Applications
3-Phase Motor Controls Switch Mode Power Supplies (SMPS) Uninterruptible Power Supplies (UPS) Induction Heating Welding Systems Switching Amplifiers General Power Conversion Circuits
IXYS reserves right change limits, test conditions dimensions.
1998 IXYS rights reserved
IXBD4410 IXBD4411
Symbol VDD/VEE VDD/GND (rev) Tstg Definition Supply Voltage 4410/4411 4412/4413 Input Voltage (INH, INL) Input Current (INL, INH, Peak Reverse Output Current (OUT) Maximum Power Dissipation Operating Ambient Temperature Maximum Junction Temperature Storage Temperature Range Lead Soldering Temperature Recommended Operating Conditions VDD/VEE VDD/GND VDD/LG LGh/LGl Supply Voltage 4410/4411 4412/4413 16.5 V/ns Maximum Ratings -0.5 -0.5 -0.5.VDD +0.5
IXBD4412 IXBD4413
Dimensions inch 25.4 16-Pin
Maximum Common Mode dv/dt
Symbol
Definition/Condition Characteristic Values 25°C, unless otherwise specified) min. typ. max.
16-Pin Plastic
INL, Inputs (referred VtVih Positive-Going Threshold Negative-Going Threshold Input Hysteresis Input Leakage Current/Vin=VDD Input Capacitance 3.65
Open Drain Fault Output (referred 4410/4411) Output/Rpu Output/Io VDD-0.05
Cross view both packages
Output (referred Output/Io Output/Io Output Res./Io -0.1 Output Res./Io Peak Output Current/CL VDD-0.05 VEE+0.05 8-Pin Plastic 0.45
Input (referred 4410/4411 4412/4413) Positive-Going Threshold Input Capacitance Shorting Device Output Resistance 0.24
Supply (referred 4410/4411) Iout finv VEEF Output Voltage/Io Output Current/Vout 0.70 Inverting Frequency Undervoltage Fault Indication -6.5 -7.5
-4.8
1998 IXYS rights reserved
IXBD4410 IXBD4411
Symbol Definition/Condition Characteristic Values 25°C, unless otherwise specified) min. typ. max.
IXBD4412 IXBD4413
Undervoltage Lockout Drop Hysteresis 10.5 0.15 11.5
Quiescent Power Supply Current Current/Vin=VDD
Inputs (Fig. td(on) td(off) tdlh(off) Turn-on delay time; 4410/4412 Rise time; Turn-off delay time 4410/4412 Fall time 4410/4412 Turn-on delay time 4411/4413 Turn-off delay time tdlh(on) 4410/4412 Turn-on delay time 4411/4413 Turn-off delay time =1nF Fig. Output signal waveform Fault Output Delay Fault Conditions (4410/4411) tFLT Delay/Rpu =1nF =1nF =1nF =10nF =1nF
Overcurrent Protection Delay Driver-Off delay time
Fig. IXBD4410/4411 Switching time test circuit 1998 IXYS rights reserved
Figure IXBD4412/4413 Switching time test circuit
IXBD4410 IXBD4411
IXBD4412 IXBD4413
Chipset Overview
ISOSMARTchipsets pairs integrated circuits providing isolated high- low-side drivers phaseleg motor control, other application which utilizes half bridge, 3phase drive configuration. They consist drive control inputs (INL INH) Power-MOSFET/IGBT gate-drive outputs. Both inputs operate from common ground, activated HCMOS compatible logic levels. low-side output operates near input ground, while high-side output operates from floating ground that nominally source connection high-side phaseleg power device. Both outputs typically provide transient current drive fast switching phaseleg power device. IXBD4410/IXBD4411 full featured ISOSMARTdriver chipset incorporates IXBD4410 low-side driver (Fig. IXBD4411 high-side driver (Fig. When input "INL" positive logic level, low-side gate output goes high (turns on); when "INH" positive logic level, high-side gate drive output goes high. high-side isolated from low-side magnetic barrier, across which turn on/off signal transmitted highside gate drive. case IXBD4410/4411 chipset, IXBD4411 fault signal also transmitted back IXBD4410 driver. This isolation only depends cost communications transformer, which designed withstand 1200 more. There magnetic transmission channels between low- highside IC's bi-directional communication (IXBD4410/4411). sends signal from low-side IXBD4410 high-side IXBD4411 other sends signal back from high-side low-side signal that sent controls IXBD4411 gate-drive output. signal sent from IXBD4411 back IXBD4410 indicates high-side fault occurred (overcurrent, under-voltage high-side +power supplies). This detected IXBD4410 driver sets "FLT" low, indicate highside fault. fault signal that returned from IXBD4411 strictly status; gate-drive shutdown because high-side fault done
UVDD UVEE
Fig. IXBD4411, high-side driver block diagram
UVDD UVEE
Fig. IXBD4410, low-side driver block diagram
Fig. Logic representation IXBD4410 signal 1998 IXYS rights reserved
IXBD4410 IXBD4411
locally within high-side IXBD4411. IXBD4411 gate-drive will turn-off power device whenever overcurrent under voltage condition arises. overcurrent sensing active only while gate driver output "high" (on). overcurrent fault condition latched reset next gate input positive transition. (pin IXBD4411 used should grounded. low-side IXBD4410 driver provides output (FLT) indicate highside (IXBD4411) low-side (IXBD4410) fault. This output "open-drain" output. IXBD4410 low-side driver fault indications similar IXBD4411 high-side driver indications outlined above. "graphic" logic diagram chipset's function presented Fig.4. Note that this diagram presents logic this function "low-side" IXBD4410 driver actual circuit. describes combined logic "fault logic" "hi-side fault sense" blocks both IXBD4410 IXBD4411 shown Fig. IXBD4412/IXBD4413 basic, lower cost ISOSMARTchipset consists pair P-DIP ICs: IXBD4412 (low-side driver) IXBD4413 (high-side driver). operates similarly IXBD4410/4411 pair, does include negative drive fault indications option. This pair requires only single magentic isolated transmission channel. most efficient method providing power high-side driver bootstrapping. This method illustrated functional drawing page application example (Fig. diode capacitor Using this method, power drawn through high-voltage diode onto reservoir capacitor whenever floating high-side ground returns near real ground low-side driver; when high-side gate turned floating ground moves towards higher potential, bootstrapping diode back-biases, high-side driver draws power solely from reservoir capacitor. Power also provided isolated power supply (usually extra secondary system housekeeping supply switching transformer). Both IXBD4410 IXBD4411 contain on-board negative charge pumps provide negative gate drive, which ensures turn-off high- low-side power device presence currents induced power device Miller capacitance from inductive ground transients. These charge pumps provide relative local driver ground when rated average currents charge pump requires external capacitors Fig. charge pump frequency nominally kHz. charge pump clock turned whenever difference between supplies exceed prevent exceeding breakdown rating Both IXBD4410 IXBD4411 drivers possess local grounds each, common logic ground, "Kelvin" ground. Kelvin ground logic grounds first connected directly each other, then Kelvin-source power device accurate overcurrent measurement presence inductive transients power device source terminal. Power MOSFET IGBT overcurrent sensing utilizes -chip comparator with typical threshold. typical application, current mirror Power MOSFET IGBT connected grounded, low-value resistor, overcurrent comparator input high- low-side driver. comparator will respond typically within overcurrent condition shutdown driver output. power switches could protected also desaturation detection (see Fig. assure maximum protection phaseleg power devices, chipset incorporates following Power MOSFET IGBT protection circuits:
IXBD4412 IXBD4413
Description IXBD4410 (Low-Side Driver)
Sym. Description IXBD 4410/4411 Positive power supply. Logic input signal referenced (logic ground). IXBD4410. "high" this turns gate drive output resets fault logic. "low" this turns gate drive output. IXBD4411 this used should connected ground (LG). Connection (IXBD 4411) Logic input signal referenced (logic ground). IXBD4410, this signal transmitted IXBD4411 "high-side" driver through pins T+). "high" this turns IXBD4411 gate drive output resets fault logic. "low" this turns IXBD4411 gate drive output. IXBD4411 this used should connected ground (LG). Connection (IXBD 4411) Transmitter output complementary drive signals. Direct drive signal transformer, which connected receiver chipset's companion device. IXBD4410, this signal transmits on/off command companion IXBD4411. IXBD4411, this signal transmits fault indication companion IXBD4410 driver. Receiver input complementary signal. Directly connected signal transformer, which driven chipset's companion device. IXBD4410, this input receives fault indication from companion IXBD4411 driver. IXBD4411, this input receives on/off command from companion IXBD4410 driver.
Power device overcurrent desaturation protection. IXBD4410/ 4411 4412/4413 will turn driven device within sensing output overcurrent, desaturation condition. Gate-drive lockout circuitry prevent cross conduction (simultaneous conduction low- high-side phaseleg power devices), either under normal operating conditions when fault occurs. During power-up, chipset's gatedrive outputs will (off), until voltage reaches under-voltage trip point. Under-voltage gate-drive lockout low- and/or high- side driver whenever respective positive power supply falls below typically. Under-voltage gate-drive lockout low- high- side driver whenever respective negative power supply rises above typically (IXBD4410/4411).
1998 IXYS rights reserved
IXBD4410 IXBD4411
Description IXBD4411 (High-Side Driver)
IXBD4412 IXBD4413
Description IXBD4412 (Low-Side Driver)
Description IXBD4413 (High-Side Driver)
Sym. Description IXBD 4410/4411 Low/high side fault output. IXBD4410, this output indicates fault condition either device chipset. "high" indicates fault, "low" indicates that either overcurrent,VDD under-voltage occurred. case overcurrent, this output will remain active "low" until next input cycle respective driver. case under-voltage, this output will remain "low" until proper voltage restored. IXBD4411 does have output,and should tied Connection (IXBD 4411) Current sense desaturation detection input. This input active only while "high" (on). When "low" (off) this input pulled ground through resistor. voltage this above threshold typical, will turn output (pin off. This used power device overcurrent protection.
Sym. Description IXBD 4412 Logic input signal referenced GND. "high" this turns gate drive output resets fault logic. "low" this turns gate drive output. Logic input signal referenced GND. "high" this transmitted "high-side" driver (IXBD4413), turns "high-side" gate drive output resets fault logic. "low" this transmitted "high-side" driver (IXBD4413) turns gate drive output. Transmitter output complementary signal. Direct drive signal transformer, which connected receiver companion IXBD4413 "highside" driver. This signal transmits on/off command companion driver. Current sense desaturation detection input. This input active only while "high" (on). When "low" (off) this input pulled ground through resistor. voltage this pin, above threshold typical, will turn output (pin off. This used power device overcurrent protection. Logic power ground. Gate drive output. This output responds signal. "high" will turn ("high"), "low" will turn ("low"). fault condition will also turn this output ("low"). Positive power supply.
Sym. Description IXBD 4413 used. Connect (pin used. Connect (pin Receiver input complementary signal. Directly connected signal transformer, which driven companion IXBD4412 "low-side" driver. This input receives on/off command from companion "low-side" IXBD4412 driver. Current sense desaturation detection input. This input active only while "high" (on). When "low" (off) this input pulled ground through resistor. voltage this pin, above threshold typical, will turn output (pin off. This used power device overcurrent protection. Logic power ground. Gate drive output. This output responds transmitted signal from companion IXBD4412 "low-side" driver. "high" "low-side" driver (IXBD4412) will turn this output ("high"), "low" will turn ("low"). fault condition will also turn this output ("low"). Positive power supply.
Kelvin ground. This ground used Kelvin connection overcurrent desaturation sensing. Logic power ground. Capacitor terminals negative charge pump (VEE); terminal (pin 12).
Negative supply terminal. Gate drive output. IXBD4410 this output responds signal. "high" will turn ("high"), "low" will turn ("low"). IXBD4411, this output responds transmitted signal from companion IXBD4410. "high" IXBD4410 drives will turn ("high"). "low" will turn ("low"). This output will turn ("low") also response fault condition.
1998 IXYS rights reserved
IXBD4410 IXBD4411
IXBD4412 IXBD4413
Application
IXBD4410/4411 IXBD 4412/ 4413 chipset devices specifically designed MOS-gated transistor drivers half-bridge power converters, 3-phase motor controls, applications. phaseleg command normally generated previous (user provided) circuitry. must decomposed into separate logic signals, high-side low-side power transistors, with appropriate deadtime each state transition. deadtime insures non-overlapping conduction even turn-on turn-off delay times power devices unequal. minimum deadtime should greater than tdlh. separate circuit, device like IXYS deadtime generator IXDP630, used perform this function. ISOSMARTchipset family devices generate deadtime, although there internal lockout that prohibits device form being commanded "on" before other commanded "off". This simplifies start-up shutdown protection circuitry, preventing logic error during power-up from turning both high-and low-side transistors simultaneously. Negative Charge Pump Circuit Design on-chip generator provided IXBD4410/4411 generates negative power supply, regulated below positive rail. (Note: this circuit present lower-cost IXBD4412/4413 chipset).If will will This negative drive potential off-state either desirable required many instances. When switching clamped inductive load (Fig. turn-on will commutate freewheeling diode around Whether this diode intrinsic MOSFET) extrinsic (IGBT bipolar), reverse recovery critical proper circuit operation. high turn-on di/dt near rated voltage, recovery quite "snappy" (the di/dt second half recovery process, after diode begun recover blocking capability, very large), creating very high dv/dt across This dv/dt impressed across Miller capacitance forcing large 1998 IXYS rights reserved
reduces voltage required create failure, this problem even more likely occur. industrial module package (e.g.: A/1200 IGBT phaseleg module), series inductance contributed long gate leads connectors further complicate design. heavily snubbered converter, power supply design with transformer leakage inductance, design problem relatively simple negative drive seldom required. these applications, IXBD4412/4413 adequate. However, modern snubberless lightly snubbered converter design, important keep gate drive impedance high enough during transistor turnoff limit reapplied dv/dt (the transistor 'active' snubber). This always important control, case IGBT required achieve necessary RBSOA. same time, mandatory keep off-state gate drive impedance very assure transistor remain during induced dv/dt (including diode recovery dv/dt). some instances, simply possible satisfy both criteria with applied off-state. these cases IXBD4410/4411 with negative bias generator must used. internal generator charge pump circuit. Referring Fig. external charge pump capacitor required between
Fig. Switching clamped inductive load current flow gate terminal device. this current pulse causes high enough voltage drop across output impedance gate drive circuit, Rout, will turned conduction every instance turned (and Vice Versa), aside from degrading efficiency, lead catastrophic failure both power transistors. high temperature, where mV/°C temperature coefficient IGBT/MOSFET threshold
Fig. IXBD4410/4411 Detailed phase circuit with dead time generator IXDP
IXBD4410 IXBD4411
terminals (C7, C11), output reservoir capacitor between (C10, C14). charge pump capacitor (C7, C11) recommended. voltage regulation method used IXBD4410/4411 allows ripple frequency depends size output reservoir capacitor (C10, C14) average load current. minimum recommended output reservoir (C10, C14) tantalum, aluminium electrolytic construction chosen. Note that this reservoir capacitor addition good quality high frequency bypass capacitor (0.1 that should placed from (C9, C13). small resistor series with charge pump capacitor, (R7, reduces peak charging currents charge pump. value greater recommended, illustrated applications example Fig. Current Sense Desaturation Detection Circuit members ISOSMARTdriver family provide very flexible overcurrent/short circuit protection capability that works with both standard three-terminal power transistors, with 5-terminal current sensing power devices. Overcurrent detection accomplished illustrated Fig. (for current mirror power device) Fig. (for standard three terminal power transistor). Desaturation detection accomplished with same internal circuits measuring voltage across power transistor on-state with external resistor divider (Fig. 7c). input trip point VTIM, typically referenced Kelvin ground Current Mirror MOSFET IGBT allow good control peak let-thru currents excellent short circuit protection when combined with ISOSMARTdriver family devices. sense resistor chosen develop desired peak transistor current, assuming mirror ration 1400:1, trip point desired: 1400/30 (use CC). important realize that Coss unit area mirror cells much
IXBD4412 IXBD4413
With Current Mirror
With Standard MOSFET/IGBT
Desaturation Detection with Standard MOSFET/IGBT
Fig. Alternative overcurrent protection circuits larger that Coss unit area bulk chip (due periphery effects). This causes large transient current pulse mirror output whenever transistor switches dv/dt currents), which cause false overcurrent trigger. filter indicated Fig. will eliminate this problem. Standard three-terminal MOSFET IGBT devices discrete well modern industrial single transistor phaseleg modules) also protected from short circuit with ISOSMARTdriver family devices. discrete device designs, where source/emitter terminal available, overcurrent protection with external power resistor implemented. resistor placed series with device emitter, with full device current flowing through (Fig. 7b). sense resistor again selected develop desired peak transistor current, assuming trip point desired: (use non-inductive current sense resistor). important recognize that "noninductive" relative term, especially when applied current sense resistor construction characterization. There always significant series inductance inserted with sense resistor, di/dt voltage transients cause false overcurrent trigger. filter indicated Figure will eliminate this problem. Choosing pole current sense resistor zero should exactly compensate series inductance. Because exact value normally known (and vary depending layout component lead dress) this normally good idea. Usually, time constant should times longer than suspected time constant. Desaturation detection Figure probably most common method short circuit protection today. While strictly "overcurrent" detector, power transistor gain, consequently short circuit let-thru current, well controlled with modern MOSFET IGBT) this methodology offers very effective protection. Both IXBD4410/4411 one-phase (half-bridge) circuits Fig. IXBD4412/4413 circuit Fig. uses desaturation detection. Fig. voltage across Power MOSFET devices IGBTs) monitored sets voltage-divider networks, high-side gate driver, lowside gate driver. dividers trip input comparators when either Power MOSFET device exceeds reasonable value, perhaps (usually value nominal voltage works well). chosen tolerate applied steady state voltage acceptable power dissipation. Dielectric withstand capability, power handling, temperature rise, board creep strike spacings, must carefully considered design voltage-divider networks. off-state, voltage across Power MOSFET device high potential. keep this normal condition from setting internal fault flip-flop IXBD4410 IXBD4411, internal CMOS switch turned placed across pins shorting them together. This effectively discharges Fig. maintains zero potential with respect 1998 IXYS rights reserved
IXBD4410 IXBD4411
When command arrives switch Power MOSFET device, CMOS switch shorting turned off. driven Power MOSFET device switched approximately later, with typical load conditions, drain-to-source potential, VDS, take additional delay collapse normal on-state voltage level. prevent false triggering this, parallel combination with R11, R14, delays input signal. During this turn-on interval, voltageacross will rise until Power MOSFET device finally comes pulls voltage across back down. MOSFET device load circuit shorted, voltage cannot callapse turn-on. this case, voltage across rises rapidly until reaches tripping fault flip-flop shutting down driver output. same time, must kept small enough that added delay does slow down detection short circuit event much that Power MOSFET device fails before driver realizes that trouble. desaturation detection circuit Fig. functions identically Fig. just described. Current limit desaturation detection latched, reset cycle-by-cycle basis with rising edge respective input command. Three Phase Motor Controls Fig. block diagram typical 3phase voltage-source inverter motor control. power circuit consists power switching transistors with freewheeling diodes around each them. control function performed digitally microprocessor, microcontroller, chip, user custom
1200
IXBD4412 IXBD4413
performed board full random logic analog circuits. these cases, command power transistors generated circuit, this circuit usually referred system ground potential bottom terminal power bridge. ISOSMARTfamily drivers interface between world control logic world power, input logic commands precisely control actions high voltage current (1200 typical application). Fig. detailed schematic phase three 3-phase motor control, showing interconnection IXBD4410/4411 associated circuitry. This application utilizes full feature IXBD4410/4411 family devices line operated inverter. situations that would benefit from negative gate drive, require fault status output, IXBD4412/4413 chipset prove adequate. Fig. complete schematic phase 3-phase inverter using lower cost IXBD4412/4413 chipset. Notice reduction total parts count. With smaller 8-pin packages devices themselves, IXBD4412/4413 chipset offers reduction board real estate modest
reduction feature compared IXBD4410/4411 devices. Layout Considerations IXBD4410/4411 IXBD4412/4413 intended used high voltage, high speed, high dv/dt applications. ensure proper operation, great care must taken laying printed circuit board. layout critical areas include communication links, current sense, gate drive, supply bypassing. communication path should short possible. Added inductance disturbs frequency response signal path, these distortions cause false triggering receiver. transformer should placed between with orientation reversed (Fig. 10). Capacitance between high- low-side should minimized. signal trace should underneath communication path, high- low-side traces should separated PCB. dv/dt high-side during power stage switching cause false logic transitions low-side circuits capacitive coupling. signal pulse transformer provides isolation between high-and
Fig. Typical 3-phase motor control system block diagram 1998 IXYS rights reserved
Fig. Lower cost IXBD4412/4413 single phase circuit with deadtime generator IXDP630
IXBD4410 IXBD4411
low-side circuits. line operation, spacing recommended between low- highside circuits, transformer HIPOT specification least 1500 required. This creep spacing usually adequate control leakage currents with 1200 applied after years accumulated dust particulates standard industrial environment. other environments, other line voltages, this spacing should appropriately modified. Power Circuit Noise Considerations typical transistor inverter, output MOSFET switch with di/dt >500 A/µs. Referring Fig.11 assuming that MOSFET source terminal inch path system ground, voltage high A/µs 13.5 developed. MOSFET switched transient will last long (25/500) which more than typical propagations 74HC series gate.
IXBD4412 IXBD4413
three traces while positioning transistors next their heat sink meeting UL/VDE voltage spacings just difficult. Grounding gate driver option Fig. solves MOSFET turn problem eliminating from source feedback loop. Now, unfortunately, gate driver will oscillate every time turned off. IXDP630 output goes "high", gate drive output follows (after propagation delay) MOSFET starts
Fig. Suggested Orientation
current sense/desaturation detect input noise sensitive. trip point referred (Kelvin ground) pin, applied signal must kept clean possible, filter recommended, preferably monolithic ceramic capacitor placed close possible directly between preserve maximum noise immunity, should first connected directly pin, pair then sent directly power transistor source/emitter terminal, desaturation detection circuit used) bottom divider resistor chain. supply pins must bypassed with impedance capacitor (preferably monolithic ceramic construction) with minimum lead length. output driver stage draws (typical) currents during transitions di/dt values excess A/µs. Supply line inductance will cause supply ground bounce chip that cause problems (logic oscillations and, severe cases, possible latchup failure) without proper bypassing. These bypass elements addition reservoir capacitors required negative supply high-side bootstrapped supply these features used.
Fig. Potential layout problems that create functional problems Fig. illustrates example layout problem. power circuit consists three power transistors (MOSFETs this example). With ISOSMARTgate driver chipset grounded option Fig. communication path from IXDP630 will operate without errors. trace induced voltages common with digital path, input gate driver will respond them. Unfortunately, MOSFET will operate properly. voltage induced across when turned acts source degeneration, modifying turn-on behavior MOSFET. LS1= (assuming gate plateau MOSFET di/dt turn-on will regulated driver/MOSFET/LS1 loop about A/µs; quite surprise when your circuit requires A/µs operate correctly. possible make this behavior create turn-on turn-off di/dt limiter (perhaps snub upper free wheeling diode reverse recovery). While possible, this normally desirable practical where more transistors controlled. Equalizing parasitic impedances conduct. voltage transient induced across di/dt) raises local ground (point until exceeds (630) (4410/4412) driver (after propagation delay) turns MOSFET off. MOSFET current falls, V(LS1) drops, point drops system ground slightly below), driver detects input. After propagation delay, again turns MOSFET continuing oscillation more cycle. eliminate this problem, ground level transformation circuit must added, that rejects this common mode transient. simplest de-coupling circuit, also illustrated Fig. capacitor voltage remains constant while transient voltage dropped across driver detects input transition, eliminating oscillation. This circuit does significantly turn-on turn-off delay time, cannot used transient lasts longer than allowable delays. Delay times must considered selection system dead time. most complex (and most effective) method eliminating effects transients between grounds isolation. 1998 IXYS rights reserved
IXBD4410 IXBD4411
Optocouplers pulse transformers most commonly used isolation techniques, work very well this case. IXDP630/631 been specifically designed directly drive high speed optocoupler like Hewlett Packard HCPL22XX family General Instrument 740L60XX optologic family. These optos especially well suited motor control power conversion equipment their very high common mode dv/dt rejection capabilities. Transformer Considerations transformer communication link isolation barrier between high- low-side ICs. high-side gate fault signals transmitted through transformer while maintaining proper isolation. transmitter signal form square wave, receiver responds only logic edges. This allows much smaller transformer designs, since switching frequency does require pulse transformer. nominal electrical specifications transformer follows:
IXBD4412 IXBD4413
Open circuit inductance (100 kHz; mV): Interwinding capacitance: Primary leakage inductance: Turns ratio: Primary-to-secondary isolation (1min): 1500 Core permeability (µi):
recommended ferrite bead Fair Rite Products' part number 2661000101. manufactured
seen application drawings (Fig. coupling capacitor damping resistor added series with primary side transformer. capacitor will control small amount energy needed transfer signal companion driver. resistor will control damping signal limit peak transmitter output current. receiver designed operate over wide common mode input range. reduce noise pickup, receiver ±250 input hysteresis. signal being distorted transmitter, transmitter probably running into current limit. decrease coupling capacitance increase damping resistance should solve this problem. receiver operates over wide input range. minimum amplitude side receiver about maximum about critical that there overshoot transformer secondary waveform. Each signal should slightly overdamped. significant overshoot exists, received signal logically inverted. increase damping resistor will solve this problem.
Fair-Rite Products Corp. Wallkill, Phone: (914) 895-2055
Several transformer manufacturers have produced custom transformers IXBD4410/4411 IXBD 4412/4413 chip set, above specifications: outlinePart Number 1914 Electronics Buinsville, Phone: (612) 894-9690 outlinePart Number 23Z129 Fil-Mag Diego, Phone: (619) 569-6577 Transformer, type 23Z119 IXBD 4412/4413 23Z129 IXBD 4410/4411 FEE, Rodgau/Germany Phone: +49-6106-2011 Fax: +49-6106-24286
Fig. Ferrite bead dimensions recommended transformer this ISOSMARTdriver chipset fabricated using very small ferrite shield bead (see Fig. 12), onto which six-turn primary two-turn secondary winding magnet wire made. windings segment wound achieve primary-tosecondary isolation 2500 six-turn primaries connected respective IXBD4410/4411 transmitter outputs two-turn secondaries connected their respective receiver inputs.
Fig. Transmitter/Receiver Waveforms
1998 IXYS rights reserved
Inverter Interface Digital Deadtime Generator 3-Phase Controls
Type IXDP630 IXDP631 Package 18-Pin Plastic 18-Pin Plastic Configuration Oscillator Crystal Oscillator Temp. Range -40°C +85°C -40°C +85°C
Features
HCMOS logic implementation maintains power high speed Schmitt trigger inputs CMOS logic levels improve noise immunity Simultaneously injects equal deadtime three output phases Replaces 10-12 standard SSI/MSI logic devices Allows wide range modulation strategies Directly drives high speed optocouplers
This HCMOS integrated circuit intended primarily application three-phase, sinusoidally commutated brushless motor, induction motor, servomotor modulator control systems. injects required deadtime convert single phase command into separate logic signals required drive upper lower semiconductor switches inverter. also provides facilities output disable fast overcurrent fault condition shutdown.
IXDP630, deadtime programming achieved internal oscillator. IXDP631, programming achieved crystal oscillator. alternative both IXDP630/ with external clock signal. Because flexibility, IXDP630/ easily utilized variety brushed trapezoidally commutated brushless hybrid variable reluctance step other more exotic motor drive power control circuit designs.
Applications
Phase Motion Controls Phase Systems General Power Conversion Circuits Pulse Timing Waveform Generation General Purpose Delay Filter General Purpose Three Channel "One Shot"
Block Diagram IXDP 630/IXDP
IXYS reserves right change limits, test conditions dimensions.
1998 IXYS rights reserved
IXDP630 IXDP631
Symbol Definition min. Tstg Supply Voltage Input Voltage Input Current Output Voltage Output Current Storage Temperature Lead Soldering (max. -0.5 -0.5 Maximum Ratings max. Dimensions inch 25.4 16-Pin Plastic
Recommended Operating Conditions fOSC Supply Voltage Operating Temperature Output Current Oscillator Frequency 0.001 16/24
Symbol
Definition/Condition min.
Characteristic Values typ. max.
VtVHYS ICCQ ICCQ
Input Threshold Input Threshold Hysteresis Input Leakage Current Input Capacitance Output High Voltage Output Voltage Supply Current Outputs Unloaded Quiescent Current Outputs Unloaded IXDP630 Quiescent Current Outputs Unloaded IXDP631
DP630 Oscillator Section COSC ROSC fOSC Capacitor (RCIN GND) Resistor (OSCOUT RCIN) Frequency Range Initial Tolerance (fOSC 1MHz) Temperature Coefficient DP631 Oscillator Section fOSC VINH VINL Frequency Range Oscillator Thresholds (IXTLIN) 0.1-24 tpdro 0.047 1000 0.001 -400 ppm/°C
thold
External Oscillator thold tpdro tpdeo
Frequency Range (ODCOUT open) Time DATA-to-XTLIN Time DATA-to-OSCIN Hold Time CLOCK-Data Propagation Delay RESET-to-OUTPUT Propagation Delay ENABLE-to-OUTPUT
0-24
tpdeo
1998 IXYS rights reserved
IXDP630 IXDP631
Description IXDP630
Sym. Description three single3 phase inputs. Each input expanded into outputs generate non-overlapping drive signals, RU/RL, SU/SL, delay from falling edge line rising edge other function clock. Sym. Description CIRCUIT GROUND Volts
RCIN first node clock network. IXDP630, XTLIN input applied RCIN. IXDP 631, crystal oscillator applied XTLIN. external clock supplied chip should connected this pin. This output node oscillator. connected indirectly RCIN XTLIN pins when using internal oscillator described applications information. recommended external use. After appropriate delay, external drive outputs (R,S, phase with their corresponding inputs; (R,S, complementary outputs.
Description IXDP631
ENAR High logic input will enable ENAS outputs, proper ENAT input phase. (R,S,T) signals control drive output lines. logic input will force both controlled outputs logic level High logic level will enable outputs their related phase. OUTENA simultaneously controls outputs. input logic level will inhibit outputs (low).
RESET RESET signal active low. When logic RESET applied, outputs will low. After releasing RESET command within generated delay, outputs will align with phase input level after programmed delay internal.
Voltage Supply
Waveforms This diagram shows normal operation IXDP630/631 after RESET input released. DEADTIME Clock periods between when both "0". length DEADTIME fixed times period CLK.
deadtime deadtime deadtime
noise deadtime Note: input, deadtime deadtime
diagram shows OUTENA ENAX asynchronously forcing Output Output state. OUTENA will force three channels state. ENAX (where three channels) will only force Outputs that channel state. Note that because ENAX asynchronous with respect internal clock deadtime counters, when ENAX goes whatever state deadtime counter immediately propagates output. This figure also shows that noise input will filtered before Output Output will become active, which extend deadtime. 1998 IXYS rights reserved
IXDP630 IXDP631
Application Information
Basic Operation IXDP630/631 Deadtime Generators intended simplify implementation single- threephase digitally controlled power conversion circuit. replaces three digital event counters (timer/ counters) microcontroller implementation motor control, other power system. most cases these timers premium. They must used calculate pulse width three independent modulators, interrupt service times, generate real-time clock, handle communications timing functions, etc. input command inputs first synchronized with internal oscillator. When input changes state, output switched off, after deadtime exactly clock periods, complimentary output switched example, input output first rising edge after input brought low, output goes low. After exactly more clock periods output goes high. This injected delay deadtime. This method synchronizing utilized guarantee that deadtime always exactly same accuracy frequency). This very important certain applications. Unbalanced deadtime creates offset output stage transfer function, cause saturation induction machine control driven transformer corrected within cycles.
Deadtime power circuits
deadtime required? Fig. typical switching power conversion equipment output stage. typically more) switches. simple logic error turning transistor wrong instant cause catastrophic failure right wrong) circumstances. normal operation, when state output totem pole must change, conducting transistor turned off. Then, after delay (usually called deadtime), other transistor turned delay added ensure that there possibility both transistors conducting same time (this would cause short circuit link "shoot through" would likely fail both transistors microseconds). When control logic commands switch change state, several parasitics delay/modify this command. propagation delay control logic gate drive buffer, (off) power transistor, storage time (for bipolars) tail time (for IGBTs), voltage rise current fall times, etc., significant. Problems Caused Excessive Deadtime little good, should better except with deadtime. Unfortunately, deadband switching output stage causes nonlinearity power circuit transfer function that difficult control loop remove. Fig. illustrates problem. switching period time commanded time commanded deadtime. Assuming continuous condition, with current direction IL1: With current direction IL2:
zero, instantly changes This significant nonlinearity that causes zero crossing distortions load current voltage that must removed feedback loop around stage. these nonlinearities large enough, loop have gain speed remove them. This cause problems behavior product that unacceptable. Zero crossing distortion current microstepped step motor, example, causes very serious position errors, velocity ripple, audible noise operation undesirable.
Fig. Problems caused excessive deadtime. Calculating Appropriate Deadtime Values designer must determine, under worst case conditions, absolute maximum delay between logic command actual cessation transistor conduction. This includes appropriate stages logic, transistor storage delay times, etc. very important include special effects switch technology chosen. Storage time bipolar transistor with constant base drive vary 10:1 collector current varies (storage time increases dramatically collector current, such light load). These effects must considered when determining "worst case" delay time requirements. power circuit must only work full rated load, must fail under light load conditions. delay least this time (plus guardband) must injected command series transistor absolutely prohibit turn-on during this interval.
Fig. Totem Pole configuration transistor switches; reason deadtime requirements 1998 IXYS rights reserved
change "apparent duty cycle" then twice deadtime (2DT). deadtime cycle period, duty cycle, load current crosses
IXDP630 IXDP631
Selecting Components Specific Requirement Deadtime IXDP630/631 exactly clock periods: 8/fclk. Once worst case (minimum) deadtime been determined (from Power switching component manufacturer data sheets, drive circuit analysis, breadboard measurements, etc.) clock frequency calculated: fclk(max) DT(min). This highest allowable clock frequency, including effects initial accuracy, tolerance, temperature coefficient, etc. When choosing oscillator components, special attention resistor capacitor construction mandatory. Oscillator Design There versions deadtime generator. They have distinctly different internal oscillator designs serve different application. either case, however, internal oscillator disabled simply leaving external components off. HCMOS compatible clock directly into RCIN XTLIN pin. IXDP630 Oscillator Design IXDP630 uses Schmitt trigger inverter oscillator (Fig. external components, ROSC COSC, determine clock frequency consequently deadtime. This design allows significant cost reduction over standard crystal oscillator, entails trade-off frequency accuracy. initial accuracy drift function external component tolerance temperature coefficients, supply voltage, IXDP630 internal parameters. frequencies under MHz, assuming external components were perfect, IXDP630 would introduce initial accuracy error temperature dependence -400 ppm. shift frequency over range typically less than higher frequencies with resistor values below IXDP630 internal parameters become more influential factors. This results greater frequency variation from device another, well with temperature supply voltage variations. high accuracy requirement, IXDP631 with crystal oscillator would better choice. Oscillator frequency Rosc Cosc shown Fig. analytical method setting oscillator, design equation operation below approximately: fOSC 0.95 Cosc Rosc operation above MHz, fOSC 0.95 Cosc (Rosc+30) 10-8 IXDP631 Precision Crystal Oscillator Design IXDP631 uses more common standard internal crystal oscillator design. proper operation crystal must parallel resonant type, resonating crystal's fundamental frequency. Fig. illustrates recommended oscillator configuration. Note external components required. capacitors needed achieve calibrated crystal frequency (their value determined crystal manufacturer), resistor necessary assure that circuit starts every case. While circuit will usually operate without these extra parts, this recommended. crystal oscillator IXDP631 significantly more accurate than oscillator IXDP630. total tolerance (including effects initial accuracy, temperature, supply voltage, drift, etc.) better than ±100 ppm. This improves accuracy repeatability desired deadtime, added expense crystal. Which version appropriate your application? That depends willing trade component cost deadtime accuracy.
COSC COSC COSC COSC
COSC COSC COSC COSC
Oscillator 1000
Fig. IXDP630 internal Schmitt Trigger inverter oscillator (ROSC, COSC external)
Fig. Oscillator frequency component selection IXDP630. 1998 IXYS rights reserved
IXDP630 IXDP631
IXDP630 Oscillator Component Details IXDP630 oscillator only external components. Rosc should precision, high frequency resistor. material used carbon composition resistors hydroscopic absorbs water), causing resistors above change value with relative humidity. This initial tolerance temperature coefficient deviations, recommended. Instead, precision metal film carbon film resistor construction preferred, with initial tolerances better with temperature coefficients ±100 ppm. construction Cosc also critical circuit operation. Cosc should good quality monolithic ceramic (single multilayer) metallized polypropylene timing capacitor. ceramic technology chosen, sure consider temperature coefficient tolerance. minimum capacitor value that critical, part number rated capacitance. ceramic initial tolerance +80/-20 temperature variation +30/-80 over temperature. initial tolerance, over temperature. initial tolerance, over temperature (although tighter selections readily available NPO). film technology chosen, polypropylene best choices. Tolerances down standard temperature coefficient ±100 ppm. layout external components also critical. components should close device possible, minimizing stray capacitance inductance. IXDP631 Crystal Oscillator Component Details IXDP631 oscillator requires three external passive components, addition crystal. crystal chosen with frequency below fclk (min). capacitors resistor (illustrated earlier Fig. follow rules similar oscillator option. resistor should metal carbon film, although accuracy stability significantly affect oscillator frequency accuracy. capacitors should monolithic ceramic construction (CK05, similar) with better characteristics. Grounding, Interfacing Noise Immunity very high level currents that switched high speed typical motor control power circuit, voltage transients di/dt) cause serious problems. Fast digital circuits respond transients instead legitimate inputs, disturbing inverter operation causing outright failure. Bypassing Decoupling with high speed logic component, IXDP630/631 should bypassed with good quality (monolithic ceramic film) capacitor designed specifically bypass application. Decoupling normally required. IXDP630 does generate sufficient supply line current ripple significant noise source when properly bypassed, capable rejecting normal supply line noise. Logic Levels inputs IXDP630 IXDP631 (except XTLIN IXDP631) HCMOS Schmitt Trigger compatible. IXDP631, XTLIN different because crystal oscillator circuit cannot tolerate Schmitt input. hysteresis inherent Schmitt Trigger inputs greatly improves reliability digital communications. reject ground bounce induced voltages digital signal traces Power Circuit Noise Generation Fig. Recommended Crystal Oscillator Components 1998 IXYS rights reserved typical transistor inverter, output MOSFET switch with di/dt 500A/µs. Referring Fig. assuming that MOSFET Source Terminal inch path system ground, voltage high 13.5 developed: 500A/µs 13.5 MOSFET switches transient will last long (25/500) which much more than typical propagation delay series gate.
Caution: digital circuits tied system ground, local ground, clear that such transient would cause spurious outputs. inverter, consequences such error could catastrophic. Turning transistor wrong time could easily cause explode, with potential equipment damage operator injury clearly undesirable.
Fig. Power circuit noise generation Methods Correcting these Problems first step logic family with inherent noise immunity. Standard derivatives, including 74HCT CMOS) poor choice because logic levels these families employ. particular, VOL, close ground reject levels ground noise common power circuits. 74HC logic significantly superior, older 4000 series CMOS even better. Unfortunately, modern motor controls, especially those that employ microprocessors, speeds 4000 series CMOS longer adequate. most cases 74HC logic only viable alternative. Layout second, most important step printed circuit board (PCB) layout. very important component power circuit, there
IXDP630 IXDP631
tendency leave schematic. During layout process, engineer must consider each every connection from standpoint contribution system operation. sensitive What noise producing lines routed near What transients occur between circuits tied each this trace.? With exceptions, modern autorouters cannot deal with these requirements. autorouters used, they produce layouts that will function. Remember that IXDP630/631 interface between control circuits power circuits. Nowhere else these problems more likely occur. Nowhere else will need more attention. Fig. illustrates example layout problem. power circuit consists three MOSFET di/dt turn-on will regulated driver/MOSFET/ loop about A/µs quite surprise when your circuit requires A/µs operate correctly. possible make this behavior create turn-on turn-off di/dt limiter (perhaps snub upper freewheeling diode reverse recovery). While possible, this normally desirable practical where more transistors controlled. Equalizing parasitic impedances three traces while positioning transistors next their heat sink meeting UL/VDE voltage spacings just difficult. Grounding gate drive buffer option solves MOSFET turn problem eliminating from eliminate this problem, ground level transformation circuit must added that rejects this common mode transient. simplest decoupling circuit, also illustrated Fig. capacitor voltage remains constant while transient voltage dropped across buffer detects input transition, eliminating oscillation. This circuit does significantly turn-on turn-off delay time, cannot used transient lasts long these delays allowed extend. Delay times must considered selection system deadtime. also important consider layout bypass capacitor well oscillator components order keep these close device possible. Isolation most complex (and most effective) method eliminating effects transients between grounds isolation. Optocouplers pulse transformers most commonly used isolation techniques, work very well this case. IXDP630/631 been specifically designed directly drive high speed optocoupler like Hewlett Packard HCPL22XX family General Instrument 740L60XX optologic family. These optos especially well suited motor control power conversion equipment their very high common-mode dv/dt rejection capabilities. Fig. Potential layout problems that create functional problems. power transistors (MOSFETs this example) controlled common digital (the IXDP630). With gate drive amplifier discrete circuit possibly driver like IXBD4410) grounded option (b), communication path from IXDP630 will operate without errors. trace induced voltages common with digital path input gate drive buffer will respond them. Unfortunately, MOSFET will operate properly. voltage induced across when turned acts source degeneration, modifying turn-on behavior MOSFET. (assuming gate plateau Source feedback loop. Now, unfortunately, gate driver will oscillate every time turn off. IXDP630 output goes high, gate driver output follows (after propagation delay) MOSFET starts conduct. voltage transient induced across Ls1/di/dt) raises local ground (point until exceeds (630)-Vil (gate buffer) buffer (after prop. delay) turns MOSFET off. MOSFET current falls, V(Ls1) drops, point drops slightly below) system ground, buffer detects input. After propagation delay, again turns MOSFET continuing oscillation more cycle. major problem associated with using optocoupler power circuit common-mode dv/dt capability. When lower transistor turned Collector Drain) pulled ground very quickly. optocoupler that drives upper transistor local output stage referenced Emitter (Source) this upper device, which tied Collector lower device. this node moves, dv/dt between here input circuit common impressed across upper optocoupler. This causes displacement currents flow sensitive nodes optical receiver circuitry, cause false triggering output. Always strict attention manufacturer's recommended dv/dt ratings exceeding them could disastrous.
1998 IXYS rights reserved
High Voltage Current Regulators
Current Regulator BVDS min. switchable regulators Switchable regulators ID(P) typ.
TO-220
TO-251
TO-252
connections
Connection (Control switchable regulator) Pos. Term., Neg. Term.
IXCP 10M35 IXCP 20M35 IXCP 35M35 IXCP 10M35S IXCP 10M45S
IXCU 10M35 IXCU 20M35 IXCU 35M35 IXCU 10M35S IXCU 10M45S
IXCY 10M35 IXCY 20M35 IXCY 35M35 IXCY 10M35S IXCY 10M45S
Features Extremely stable current characteristics ppm/K Minimum 350/450 breakdown Easily configured bi-directional current sourcing continuous dissipation International standard packages JEDEC TO-220, TO-251 TO-252 On/Off switchable current source
switchable regulators This family extremely stable, high voltage current regulators. temperature stability based threshold compensation technique uses IXYS' most recently developed high voltage process. complete family will capable providing other intermediate current levels which programmed on-chip during manufacturing phase. Specific applications current sourcing PABX applications, telephone line terminations, surge protection voltage supply protection. devices back-toback configuration will give bidirectional operation. Specific bidirectional applications would series surge protection soft start-up applications from mains.
Switchable regulators IXYS Switchable Current Regulator with 350/450 minimum breakdown capability, intended current source off-line applications, such switched mode power supply start-up circuits, where shutting regulator down demand required reduce standby power consumption. additional design flexibility, regulated current level reduced values below nominal adding single resistor series with negative terminal.
Fig. Current regulator characteristics Applications Start-up circuits SMPS PABX current sources Telephone line terminations PABXs modems Highly stable voltage sources Surge limiters protection Instantaneously reacting indestructible fuses Waveform synthesizes Soft start-up circuits
Nomenclature Current Regulators IXCU 10M45S (Example) IXYS Current Regulator Package style TO-220 TO-251 TO-252 (D-PAK) Current Rating, Current Level Amps, Voltage rating, Switchable regulator
Fig. Block diagram switchable regulator
Fig. Block diagram switchable regulator
IXYS reserves right change limits, test conditions dimensions.
1998 IXYS rights reserved
IXCP10M35 IXCU10M35
IXCP20M35 IXCU20M35
TO-220
IXCP35M35 IXCU35M35
Switchable Current Regulators
Symbol Tstg Definition Drain Source Voltage Power Dissipation 25°C) Maximum Reverse Current Junction Operating Temperature Storage Temperature Temperature soldering (max. Mounting torque with screw (TO-220) with screw M3.5 (TO-220) Maximum Ratings +350 +150 +150
0.45/4 Nm/lb.in. 0.55/5 Nm/lb.in.
Symbol
Definition/Condition
Characteristic Values 25°C, unless otherwise specified) min. typ. max.
BVDS
Breakdown voltage operating current level Plateau Current
10M35 20mA* 20M35 35mA* 35M35 50mA* 10M35 20M35 35M35 VDS=
ID(P)
ppm/K
TO-252 (D-PAK)
DID(P)/DT DVDS/D ID(p)
Plateau Current Shift with Temperature Dynamic Resistance
10M35 20M35 35M35
RthJC RthJA
Thermal Resistance junction-to-case Thermal Resistance junction-to-ambient,TO-220 TO-252
Pulse test limit power dissipation within device capability. TO-251
Dim. Millimeter Min. Max. 2.19 2.38 0.89 1.14 0.13 0.64 0.89 0.76 1.14 5.21 5.46 0.46 0.58 0.46 0.58 5.97 6.22 4.32 5.21 6.35 6.73 4.32 5.21 2.28 4.57 9.40 10.42 0.51 1.02 0.64 1.02 0.89 1.27 2.54 2.92 Inches Min. Max. 0.086 0.035 0.025 0.030 0.205 0.018 0.018 0.235 0.170 0.250 0.170 0.090 0.180 0.370 0.020 0.025 0.035 0.100 0.094 0.045 0.005 0.035 0.045 0.215 0.023 0.023 0.245 0.205 0.265 0.205 0.410 0.040 0.040 0.050 0.115
1998 IXYS rights reserved
IXCP10M35S IXCU10M35S IXCP10M45S IXCU10M45S
Switchable Current Regulators
Symbol VAKR VAGR VAGR Tstg
Test Condition 25°C 150°C 25°C 150°C 10M35S 10M45S 10M35S 10M45S
Maximum Ratings Nm/lb.in. Nm/lb.in.
ID(p)
25°C 25°C
-0.3 +150 +150 0.45/4 0.55/5
Fig. Resistor "RK" series with negative achieve different current levels
Temperature Soldering (max. Mounting torque with screw (TO-220) with screw M3.5 (TO-220)
ID(P)
Symbol
Test Condition
Characteristic Values 25°C unless otherwise specified) min. typ. max. 10M35S 10M45S
VAKR ID(P) VG(off)
(Fig.
Fig. Plateau current versus external resistance
(Fig. 10M35S 10M45S Fig. 10M35S 10M45S Fig. Dynamic resistance; (Fig.
ID(p)
dv/di RthJC RthJA
Fig. Current regulator controlled
Thermal Resistance junction-to-case Thermal Resistance junction-to-ambient, TO-220 TO-252
1000
connections Control terminal (+), Positive terminal (-), Negative terminal
ID(P)
-3.5 -2.5 -1.5
Fig. Plateau current versus applied input voltage
1998 IXYS rights reserved
IXC.10M35 IXC.20M35
IXC.35M35
IXC.10M35S IXC.10M45S
Application examples with switchable regulator
Start-up Circuit often overlooked area switch mode power supply (SMPS) designs start-up circuit housekeeping supply). good start-up circuit should inexpensive, require little space, non-complex should lower overall efficiency power supply. maximize efficiency, should switch when supply operation. Fig. shows simple start-up circuit universal SMPS. Here W/11 dropping resistor, provides initial greater supply current required SMPS control This circuit will consume 12.4 additional power, which must dissipated which reduces overall SMPS design efficiency. Depending application, additional space should provided adequately cool avoid damaging heat sensitive components. Fig. shows SMPS start-up circuit using IXCP 10M45S switchable current regulator 2N7000P MOSFET, switch off. Only during first SMPS start-up does need supply which commanded during other times. additional average power dissipation this start-up circuit during normal operation, after turned off, proportional square voltage across Fig. Standard start-up circuit SMPS into improved SMPS efficiency. Even though there more components required Fig. versus Fig. absence heat generating component will serve increase overall packing density improve layout flexibility. Simple Line Power Supply with IXCP 10M45S Fig. IXCP 10M45S, IC1, extends input voltage range linear voltage regulator IC2, 78L05 example, allow work mains. fact, three terminal linear regulator rated less than (100 mains) from will work this application. Assume that rectified voltage across sufficiently positive allow output 78L05 supply load with regulated Under steady state conditions current output just matches current input (IN) with current flow into Assume current demanded load such that goes down. This will cause (IN) current also down resulting excess current output from (-). This excess current will charge resulting terminal voltage becoming more positive, which then reduces output current until matches (IN) input current. current demanded load goes increasing (IN) input current will also will initially source additional current discharging itself. reduction voltage causes terminal become more negative with respect results output current increase. steady state, will provide exactly current required more less. Note that must heat sink since average power dissipation approximately peak input mains voltage multiplied output regulator current.
Fig. SMPS start-up circuit using IXCP 10M45S
This approximately assuming such, minimal heat build-up will occur IXCP 10M45S, eliminating potential problems heat sensitive components. reduction power dissipation start-up circuit translates directly
Fig. IXCP 10M45A extend input voltage range voltage current regulators
1998 IXYS rights reserved
IXC.10M35 IXC.20M35
IXC.35M35
IXC.10M35S IXC.10M45S
Other Application
Current Regulator Current Source PABXs Telephone instruments need take power from telephone line when they taken "off" hook; i.e., when telephone physically lifted user. power sourced PABX end, most cases, this achieved applying differential voltage telephone lines substantially sized inductors. These inductors provide very resistance applied voltage while simultaneously presenting high impedance audio signals appearing line ensuring that signal routed voltage source under operating line conditions.
current sources needed, line line. Their characteristics must have high degree matching. This provides longitudinal balance that needed. Longitudinal imbalance between lines will mean that there likely unwanted pickup across phone terminals. circuit Fig. shows current sources PABX line. Applied voltage around well longitudinal balance, each source must present certain impedance value speech signals each line. current sources would provide attractive cost-effective solution PABX current
Fig. current Regulators placed back-to-back
Telephone Line Termination Fig. shows simple schematic modem interface telephone line subscriber end. Block consists circuit which provides line termination characteristics that required. Different countries require different characteristics. termination must provide specific characteristics well provide dynamic impedance necessary between lines.
Fig. Modem link-telephone line line termination
Fig. Using matched IXCP35M35 current regulators current sources.
sourcing applications (Fig. 11). devices have breakdown capability utilized with voltage supplies substantially greater than required. capability also allows extension this current source approach embrace other specific functions PABX system. important aspect current sources lines that degree matching should high. design current regulator embraces these features.
Fig. Bi-directional Regulator (one package)
addition inductor, some other components generally necessary. example IXCP35M35 current regulator could provide cost-effective equivalent function single package. IXCP35M35 nominal value capable acting constant current source line. high dynamic impedance signals under normal conditions when operating voltage across greater than several volts. Although this device operates nominal current, other current levels could supplied user.
input information into line, switch will have close. This initially means that ringing voltage will imposed across termination "X". Therefore, only provide terminating characteristics under normal data transmission capable withstanding initially applied differential ringing voltage line when switch closed.
Fig. Example line terminating circuit
Fig. PABX current sourcing with current sources longitudinal balance
Devices matched operating voltage level combination on-chip trimming preassembly stage binning procedure during electrical test.
Fig. Normal fusing links series with each board
1998 IXYS rights reserved
IXC.10M35 IXC.20M35
IXC.35M35
IXC.10M35S IXC.10M45S
Prevents "dip" power supply during fault condition Regulator remains intact easily tied with logic indicate "down state" board Highly Stable Voltage Sources obvious application would current regulator source highly stable current produce stable voltage reference (Fig. 18). This would effectively independent temperature cost approach. high voltage reference also possible, thanks their high breakdown voltages.
Fig. Soft start mains using regulator series with load. Fig. IXCP current regulators generate linear waveforms.
Fig.17 cost current regulators instead fuses
differential line voltage either polarity, therefore also needs cater this potential bi-directionally. existing solution illustrated Fig. end-of-line termination some countries. Fig. show alternate solutions using IXCP regulators. Instantaneous "Fuse" Another application would protection against sudden voltage "droops" voltage supply lines logic cards computing systems, resulting from component suddenly shorting ground. Normal fusing networks will draw considerable current during time takes fuse clear. This could cause sufficient power rail voltage cause malfunctions other logic cards, even with fast-blow fuses (Fig. 16). current regulator series with logic card restricts current operating level (Fig. 17). Therefore voltage supply does become overloaded regulator remains intact.
Vout nominal Vout 1.75 nominal Vout 0.875 nominal
Fig. surge suppression
Overvoltage Suppression regulator used voltage surge suppressor. device again connected series with lead (Fig. would normally operate current level lower than plateau (Fig. 20A). incoming voltage surge (Fig. 20b) less than breakdown voltage regulator will clamped IXCP regulator voltage less than plateau current times effective resistance load. Waveform Pattern Generation Using pair matched current regulators, very linear symmetrical waveforms generated. temperature-stable characteristics
current regulator provide high degree linearity repeatability. Basically circuit consists simply current regulator, switches, capacitor (Fig. 21). Switch would ground side would operate from voltage logic. Switch would driven from isolated driver. With matched regulators, upward downward slopes match requirement dictated control logic timing. Soft Start-Up Circuits Here regulator characteristic will clamp initial current surges which occur when power initially applied load. device, with capability could, example, used with power supply with mains limit initial high in-rush current into lamp filaments, thereby increasing filament life several times. could, therefore, used effectively lighting display transportation lighting industries. Testing Handling Recommendations initial assessment parts where customer test device characteristics free without heat sinking, continuous power dissipation should kept within ambient 25°C. (RthJA TO-220, RthJA TO-252)) Normal electrostatic handling precautions devices should adhered 1998 IXYS rights reserved
Fig. Simple voltage source with high stability
Fig. surge suppression
current regulator thus provides "instantaneous fusing" function. When logic component replaced, regulator normal functioning mode. obvious advantages having this regulator fuse substitute are:
Fig. Incoming surge/output surge across load
Compatible Digital Controller, IXDP
Description IXDP610 Digital Pulse Width Modulator (DPWM) programmable CMOS device which accepts digital pulse width data from microprocessor generates complementary, non-overlapping, pulse width modulated signals direct digital control switching power bridge. DPWM designed operated under direct control microprocessor interfaces easily with most standard microprocessor microcomputer buses. IXDP610 packaged 18-Pin slim waveform generated IXDP610 results from comparing output Pulse Width counter number stored Pulse Width Latch (see below). programmable "deadtime" incorporated into waveform. Dead-Time Logic disables both outputs each transition Comparator output required dead-time interval. output stage provides complementary output signals capable sinking sourcing voltage levels. Output Disable logic activated either software hardware. This facilitates cycle-by-cycle current-limit, short-circuit, over-temperature, desaturation protection schemes. IXDP610 capable operating frequencies from zero 300kHz; dead-time programmable from zero clock cycles cycle), which allows operation with fast power MOSFETs, IGBTs, bipolar power transistors. trade-off between frequency resolution provided selecting counter resolution 7-bit 8-bit. output drive makes IXDP610 capable directly driving opto isolators Smart Power devices. fast response pulse width commands achieved instantaneous change outputs correspond command. This eliminates one-cycle delay usually associated with other digital implementations. Features
Microcomputer compatible complementary outputs direct control switching power bridge Dynamically programmable pulse width ranges from modes operation: 7-bit 8bit resolution Switching frequency range Programmable Dead-time Counter prevents switching overlap Cycle-by-Cycle disable input protect against over-current, overtemperature, etc. Outputs disabled under software control Special locking prevents damage stage event software failure 18-pin slim package
Dimensions inch 18-Pin Slim
Symbol Vout Tstg
Definition Supply voltage Input voltage Output voltage Maximum power dissipation Storage temperature range Industrial Military
Maximum Ratings -0.3 -0.3 -0.3
1998 IXYS rights reserved
IXDP
Symbol Definition Operating Range Maximum Ratings Military min. max. +150
Industrial min. max.
Numbers Fig. corresponding time values bottom left this page.
Symbol
Supply voltage Operating free temperature
Definition/Condition Characteristic Values (Over operating range, unless otherwise specified) min. typ. max. Input High Voltage Input Voltage Input Hysteresis ODIS ODIS ODIS -0.3 -0.3 -0.1 +0.3 Fig. Write operation timing diagram
VIH(CMOS) VIL(CMOS) VIH(TTL) VIL(TTL)
Output High Voltage OUT1 OUT2 Output Voltage Input High Voltage Input Voltage Input Leakage Current Power Supply Current Definition/Condition OUT1 OUT2 Inputs Except ODIS Inputs Except ODIS Inputs fCLK
+0.3 Fig. Output disable outputs timing
Symbol
Fig.
Characteristic Values 25°C, Industrial Military -40.85°C -55.125°C
typ. min. max. min. max.
OUT2
tAVWL tWHAX tSLWL tWHSH tWLWH tDVWH tWHDX fCLK tCLCH tCHCL
Stable Stable after High High after High Pulse Width Data Valid High Data Held after High Clock Frequency Clock Pulse Duration High Output when Writing latch ODIS Output High Output When Writing Stop Control latch Time
38.5
Fig. Stop outputs timing
tCHOV tODLOL tWHOL
Fig. CLOCK output when writing latch
tRLRH
Extended frequency range parts also available. Output will change rising CLOCK edges after (see Fig.
1998 IXYS rights reserved
IXDP
Description IXDP
ODIS OUT1 OUT2
Nomenclature Digital Controller
Sym. Description
DATA data IXDP610 configured input only. Data written IXDP610 placed data lines through during microprocessor write cycle. Data accepted IXDP610 when CHIP SELECT WRITE input goes from high state. SELECT input determines whether data written IXDP610 will Control latch Pulse Width latch. least significant most significant bit. CIRCUIT GROUND
SELECT-this input determines whether data written into IXDP610 goes internal Pulse Width (PW) latch Control latch. zero this input (low voltage) directs data latch; this input (high voltage) directs data Control latch. RESET-this asynchronous, active input disables outputs, chooses 8-bit count mode counter, sets clock "divided clears Lock bit, sets dead-time counter Asserting RESET writes 01000111 binary Control latch. Asserting RESET only which Lock control latch cleared. Writes control latch that occur after lock been one, only modify Stop bit. writes control latch, while RESET input asserted, ignored. RESET also clears latch. WRITE-a low-to-high transition this input, when CHIP SELECT low, causes data written selected IXDP610 latch. SELECT low, data written pulse width latch. SELECT high, data written control latch. CHIP SELECT this active input enables WRITE input that data written into IXDP610 latch selected SELECT input.
IXDP
(Example) IXYS Digital Controller Package Type 18-Pin Plastic Temperature Range Industrial (-40 85°C) Military (-55 125°C) Optional Processing Blank Standard Burn-in
OUT2 COMPLEMENTARY OUTPUTS OUT1 these outputs provide complementary signals. base period cycle time these outputs determined CLOCK control latch. POWER SUPPLY
CLOCK frequency this input determines base frequency. also drives internal state machines. effect data transactions. ODIS OUTPUT DISABLE asserting this Schmitt trigger input forces complementary outputs immediately disabled (OUT1 OUT2 forced low). complementary outputs will remain long long this input asserted, duration cycle which OUTPUT DISABLE goes from high; i.e., complementary outputs re-enabled until beginning next cycle, then only OUTPUT DISABLE Stop Control latch asserted.
1998 IXYS rights reserved
IXDP
Description
Introduction IXDP610 digital controller. simplifies interface between microprocessor switching power bridge providing microprocessor means directly control average voltage across load motor, etc.). Since IXDP610 generates complementary control signals, there need Digital Analog Converters (DACs), Sawtooth Generators, Analog Comparators. OUT1 OUT2 directly drive buffers power transistors. IXDP610 servo system depicted system block diagram shown Fig. IXDP610 receives digital data from microprocessor converts data pair complementary signals that used control average voltage across servo motor. Shaft Encoder Peripheral Interface (SEPI) converts incremental encoder signals binary number microprocessor monitor complete control servo motor. possible generate control signals software with dedicated microprocessor microcontroller. This limitation, however, very switching frequencies kHz) significant software overhead. using IXDP610 handle generation control signals, microprocessor handle several channels control signals switch relatively high rates kHz). Servicing IXDP610 simple writing 8-bit number Pulse Width latch whenever change duty cycle desired. This analogous writing data DAC. Programmable dead-time Because IXDP610 digital programmable, possible tailor dead-time period (defined Fig. IXDP610's programmable dead-time feature difficult duplicate equivalent analog system. control switching bridge usually involves process alternating "on-time" power switches connected series between high-voltage low-voltage. example, H-bridge Fig. operated turning upper left lower right transistors leaving remaining transistors off, during first half cycle. second half cycle, upper right lower left transistors remaining off. During minimum time during transition (the dead-time period). Since dead-time programmable, tailored specific application. short highspeed MOSFETs longer IGBTs. Protection circuitry IXDP610 several features that facilitate protection power devices being controlled. ODIS input that driven external hardware under emergency shutdown conditions, such over-current over-temperature. Stop bit, Control latch, provides mechanism through which software indefinitely disable complementary outputs. ODIS Stop perform similar functions, they provide means protect power devices from measurable system hazards such overcurrent, over-voltage, over-temperature etc. Software runaway system hazard that difficult impossible measure. Lock bit, Control latch, used protect system from software runaway and/or errors. Setting Lock prevents subsequent writes Control latch from having affect IXDP610's operating parameters. Setting Lock does prevent from asserting Stop bit. Once Lock set, impossible modify critical parameters, such dead-time delay waveform resolution. Control latch Control latch composed eight bits that determine IXDP610's operating parameters. Those bits summarized Table
Fig. Cycle Time DeadTime Definition transition, between first half second half cycle, there very short period time when both upper transistor lower transistor could both transistors this short period time, they will effectively short high voltage supply ground-this undesirable situation. IXDP610's programmable deadtime feature prevents this situation guaranteeing that both transistors
SEPI
Fig. Basic System Configuration
Fig. IXDP610 Servo Motor Full Bridge Block Diagram 1998 IXYS rights reserved
IXDP610
time without affecting base cycle time. dead-time period only inserted output changes from high off). Thus, duty cycle chosen such that output would period time equal less than dead-time period, switch associated with that output will turned during cycle. this special case, will observe only dead-time period cycle time, rather than dead-time periods shown Fig. Lock writing this prevents further writes bits control latch, except Stop bit. Thus, should written this until IXDP610 been programmed. Those writes that follow being written Lock have effect through locking feature provided this prevents modification control latch software error, thereby helping prevent damage bridge being controlled IXDP610. Asserting RESET only method which lock cleared. Divide this sets frequency internal clock. Writing this causes external CLOCK divided before being presented counter. Writing zero this results division external CLOCK before presented counter ("divide one"). Divide affect dead-time Counter. Resolution writing zero this chooses 7-bit counter resolution, while writing chooses 8-bit counter resolution. Choosing 7-bit resolution doubles achieveable base frequency expense decreased duty cycle resolution. combination Divide Resolution provides user with three different base periods given external CLOCK frequency. RESET programs IXDP610 operate 8-bit resolution mode. When IXDP610 programmed 8-bit mode, base period equal clock cycles. 7-bit mode base period equal clock cycles. clock cycle equal external CLOCK period when Divide control latch zero equal external CLOCK periods when Divide one. following formula used determine base period: ((7/8 (DIV base period CLOCK period else ((7/8 (DIV base period CLOCK period else ((7/8 (DIV base period CLOCK period else ((7/8 (DIV base period CLOCK period Pulse Width number that written Pulse Width latch represents high time OUT1 (the time OUT2). Dead-time Counter decreases on-time (output high) output dead-time period (tDT). Fig. description dead-time bits Control latch determine duration deadtime period. Stop writing zero this immediately disables complementary outputs (OUT1 OUT2 forced zero). long this zero, complementary outputs will disabled. This affected Lock bit. This equivalent function OUTPUT DISABLE input. outputs will re-enabled until start period which both Stop OUTPUT DISABLE input ones. latch binary number written latch represents duty cycle complementary outputs. Percent duty cycle defined follows: (assuming zero dead-time) OUT1: duty cycle OUT2: duty cycle time cycle time "PWM cycle time" tCYCLE Fig. time cycle time
Resulting Function Action Load D0-D7 into latch Load D0-D7 into Control Latch
Table Transaction Truth Table Dead-time counter bits these three bits determine dead-time period, defined Fig. Dead-time that period time when both OUT1 OUT2 low. binary number from through valid. Thus, eight different dead-time periods programmed. least significant most significant bit. binary means dead-time means maximum dead-time. Each dead-time count corresponds CLOCK periods. instance, binary three programmed into dead-time bits, dead-time will external CLOCK cycles long. dead-time provided preventing switch overlap. Deadtime Counter delays turning switch connected OUT1 until switch connected OUT2 sufficient time turn off; complement also true, dead-time counter delays turning switch connected OUT2 until switch connected OUT1 sufficient time turn off. Since dead-time counter programmable, user optimize dead-time delay suit their specific application. typical cycle (refer Fig. dead-time periods will occur. follows turnoff OUT2. deadtime counter triggered output turning off. During dead-time period, both outputs guaranteed dead-time periods occur during duty-cycle states). dead-time period overlaps ontime output, therefore, shortens onControl Bits Name Lock Stop Description
setting dead-time period, combinations valid, dead-time delay maximum dead-time. used, reserved; always write zero this setting this prevents further access bits Control latch, except Stop bit. determines frequency internal clock. chooses between 7-bit 8-bit resolution. disables (turns off) complementary outputs.
Table Control Latch Bits
1998 IXYS rights reserved
IXDP
Resolution Control latch determines whether number latch significant bits significant bits. following formulae used determine resulting waveform's duty cycle: 7-bit mode operation: duty cycle number 8-bit mode operation: duty cycle number formulae valid numbers except those extremes.
Number (binary) 7-Bit Resolution 0000 0001 -0000 0010 -0000 0011 -0000 0100 0100 0000 0111 1101 -0111 1110 -0111 1111 1XXX XXXX 0000 0000 Resulting Duty
following table illustrates resulting percent duty cycle several numbers. (The complete table would have entries, those entries that have been omitted calculated using above formulare.) duty cycle byte written time. outputs disabled either Stop Control latch OUTPUT DISABLE input, writing duty cycle byte will have effect outputs. When outputs reenabled, duty cycle will determined last byte written duty cycle byte.
8051 IXDP610 Interface Fig. example IXDP610 interfaced with Intel 8051 microcontroller. interface very simple ideally suited servo motor control applications. 11.059 clock allows 8051's built-in serial communication hardware standard baud rate. this clock frequency, IXDP610 configured 21.6 switching frequency dead-time between zero 1.26 which adjustable steps. 8088 IXDP610 Interface
Application Information
Introduction IXDP610 digital controller intended with generalpurpose microprocessors microcontrollers. Therefore, important understand microprocessor hardware software interacts with affects operation IXDP610. following pages will find discussions some most important hardware software interface issues. Among these issues hardware interface, choose IXDP610's clock, initialization DPWM, effect dead-time duty cycle, response IXDP610 changes Pulse Width latch number. following pages should studied carefully both hardware software designer. IXDP610 interfaced with virtually microprocessor microcontroller. Some interface examples shown below. Fig. just example IXDP610 interfaced with Intel 8088 microprocessor. Using clock crystal) IXDP610 configured 19.53 switching frequency. deadtime adjusted between steps. This configuration ideally suited driving servo motor amplifiers that MOSFET, IGBT, bipolar transistors. Frequency dead-time considerations Typical applications IXDP610 include full half bridge systems. Shown Fig. full bridge system. programmable dead-time feature IXDP610 aids preventing shorts power bridge allows either fast MOSFETs slower IGBTs bipolar transistors. Table shows some frequency dead-time combinations that obtained with IXDP610. various options shown table selected varying frequency Divide
8-Bit Cycle Resolution 0000 0001 0010 0011 0100 0101 0110 0111 1000 1000 0000 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 -0000 0000 0000 0000 0000 0000 0000 0000 0000 0.78125 1.171875 1.5625 1.953125 2.34375 2.734375 3.125 50.0 97.65625 98.046875 98.4375 98.828125 99.21875 100.0 100.0
Table Duty Cycle Function Number
Fig. 8051 IXDP610 Interface
Fig. 8088 IXDP610 Interface 1998 IXYS rights reserved
IXDP610
IXDP610's Control latch. columns express dead-time percent cycle time. zero written IXDP610 programmed 7-bit resolution, writing programs IXDP610 8-bit resolution. written Divide bit, external clock (CLK) divided before being presented Pulse Width counter; zero Divide passes directly Pulse Width Counter with division frequency. given frequency select three different frequencies: CLK/ 128, CLK/256, CLK/512. (CLK/256 selected either 7-bit 8-bit resolution. During write Control latch, bits modified simultaneously, including Lock bit. Thus, only write necessary deadtime: assert Lock bit; choose Divide state; choose resolution. most applications necessary change deadtime bit, Divide bit, fly". Therefore, recommended that Lock asserted during initialization Control latch. Setting Lock guarantees that software runaway will modify state dead-time bit, thereby preventing accidental short bridge. input accessible software (via bit, spare chip select, etc.), hardware associated with asserting input should designed minimize possibility resetting IXDP610 event software runaway, since asserting input clears Lock bit, allowing modification DPWM's Control latch. Software Overflow Protection many applications, Pulse Width number written microprocessor IXDP610's Pulse Width latch result closedloop numeric calculations. Depending algorithm used, calculated number susceptible overflow, i.e. calculated Frequency number could larger than available 8-bits 7-bits) provided Pulse Width latch. this case, important that software checks overflow conditions before writing number Pulse Width latch. Following example assuming 8-bit resolution: (PWM_num check underflow, PWM_num minimum limit else (PWM_num 255), check overflow, PWM_num 255; maximum limit Effect Dead-time Duty Cycle IXDP610 been designed generate signals that range from inclusive. When zero dead-time been selected writing dead-time bits) duty cycle cycle determined using formulae shown page 32/33. Fig. illustrates effect that nonzero deadtime waveform. dead-time feature built into IXDP610 guarantees that both OUT1 OUT2 remain duration dead-time period. dead-time period occurs each time either OUT1 OUT2 turns off; dead-time period overlaps on-time output (see Fig. 6c). Thus, desired duty cycle such that
Software Considerations
Initialization Lock After power-up, IXDP610 should reset input. Doing will guarantee initial state DPWM effectively write 01000111 binary Control latch. Thus, after asserting RST, IXDP610 following state: Stop asserted, disabling OUT1 OUT2 8-bit resolution selected divided (not divided two) Lock "UNLOCKED" Dead-time Counter maximum dead-time. Asserting only means which Lock "unlocked". lock must cleared order write other bits Control latch, except Stop bit. IXDP610 does undergo internal reset power-up; therefore, recommended that system reset connected DPWM, Fig. wishes allow software control over input, they should "OR" system reset together, DPWM known state following system reset. Before initializing Control latch, should first write valid number Pulse Width latch (i.e., number that results applied load). Asserting clears Pulse Width latch. 1998 IXYS rights reserved
Dead-time Options Min. Step 1.56 1.56 0.78 1.56 0.39 0.78 0.78 1.56 0.39 0.78 0.78 1.56 0.39 0.78 0.78 1.56 0.052 0.078 0.078 0.156 0.078 0.156 0.156 0.312 0.195 0.391 0.391 0.781 0.781 1.562 1.562 3.125 10.9 10.9 10.9 10.9 10.9 10.9 Max. 0.363 0.547 0.547 1.094 0.547 1.094 1.094 2.188 1.367 2.734 2.734 5.469 5.469 10.94 10.94 21.88 38.4 25.6 25.6 12.8 25.6 12.8 12.8 10.24 5.12 5.12 2.56 2.56 1.28 1.28 0.64
Table Sample Frequency Dead-time Options
IXDP
have only dead-time period inserted each cycle. Fig. desired ontime OUT1 less than dead-time period, therefore OUT1 never turn same true OUT2 Fig. Fig. normal situation, where both outputs turn during cycle and, result, dead-time periods inserted. Response Change Pulse Width Number change Pulse Width number time. necessary synchronize writes Pulse Width latch with cycle period. IXDP610 responds Pulse Width number three clock cycles after Pulse Width latch loaded cycles after goes high). Thus, OUT1 OUT2 will immediately reflect Pulse Width number. IXDP610 does wait until next cycle implement change Pulse Width number. (See Fig. resulting duty cycle somewhere between duty cycle. exact value resulting duty cycle depends when Width Latch loaded cycles after goes high). Thus, OUT1 OUT2 will immediately reflect Pulse Width number. IXDP610 does wait until next cycle implement change Pulse Width number. Fig. shows what happens when Pulse Width number changed from near middle cycle. Fig. shows reverse situation. resulting duty cycle somewhere between duty cycle. exact value resulting duty cycle depends when Width latch loaded cycles after goes high). Thus, OUT1 OUT2 will immediately reflect Pulse Width number. IXDP610 does wait until next cycle implement change Pulse Width number.
CYCL
CYCL tDT)
CYCL
Fig. Effect Nonzero Dead-time Waveform time output less than dead-time period, output will turn This shown Fig. Therefore, commanded duty cycle actual duty cycle differ slightly, especially extreme duty cycle values. Additionally, dead-time have effect voltage applied load switching power bridge; exact effect function direction current bridge architecture bridge. should choose smallest dead-time that will work with given switch configuration. Fig. illustrate duty cycle extremes, these instances there will never dead-time period, regardless value programmed dead-time bits, because neither output ever turns off. Fig.
Fig. Effect Changing Duty Cycle during Cycle
1998 IXYS rights reserved
High Performance Dual Microstepping Controller
Type IXMS150 Package 24-Pin Skinny Temperature Range -40°C +85°C racy, IXMS150 will allow designer implement control system with resolution excess microsteps step, 50,000 steps revolution with step revolution step motor. IXMS150 greatly improves positioning accuracy virtually eliminates speed velocity ripple resonance effects fraction cost board level microstepping system. Other applications which IXMS150 designed include control single-phase (DC) motors control synchronous reluctance motors. IXMS150 ideal robotics, printers, plotters, tables facilitate construction very sophisticated positioning control systems while significantly reducing component cost, board space, design time systems cost. Features
IXMS150 high performance monolithic 2-channel controller. Implemented CMOS, power IXMS150 precisely controls current each separate power H-bridge drivers using unique sampling signal processing techniques. Each channel contains error amplifier, PWM, feedback amplifier, protection circuitry. Protection features include over/excess current shutdown, min/max duty cycle clamp, under voltage lockout, dead time insertion, shutdown input over-temp other external fault circuitry. Other features include common oscillator, feedforward circuit motor supply compensation, onchip negative bias generator. IXMS150 been optimized microstep control phase step motors. high level accu-
complete, synchronous PWMs Command input range ±2.0 full scale ±0.625 full scale current feedback signal gain matching between channels without external trim 1.6% gain linearity Feedforward compensate motor supply variations Only sense resistor H-bridge needed Onboard level current limiting Undervoltage lockout assures proper behavior power power down Enable input external over temperature fault circuit input Duty cycles limited coupled gate drive Wide range built dead time. board negative power supply generator Single supply operation 24-pin package
Block diagram IXMS
Applications
Full, half quarter, microstepping 2-phase step motor position controller Dual servo motor torque controller Solenoid actuator force controller General 2-channel currentcommanded control
Symbol
Definition Supply voltage Operating range Common-mode-range Differential Input voltage Input voltage Output voltage Maximum power dissipation Ambient temperature range Storage temperature range
Max. Ratings -0.3.15 10.8.13.2 -15.15 -15.15 -0.3.VDD+0.3 -40.85 -55.125
Tstg
Input voltage exceed either supply rail more than time. IXYS reserves right change limits, test conditions dimensions.
1998 IXYS rights reserved
IXMS
Symbol Definition/Condition Characteristic Values (VDD 25°C unless otherwise specified) min. typ. max. Frequency Amplitude FFWD OPEN Output Impedance IOUT Resistance Range Capacitance Range FFWD Open 2000 Dimensions inch 25.4 24-Pin Skinny
Oscillator fOSC VA(p-p) ZOUT
Feed Forward VFFWD Feedforward Voltage ZINFF Impedance AGND Analog Inputs Input FullScale ZIN1 ZIN2 Comp2 Impedance Comp1 Comp2 Impedance VINA VINB
Sense Inputs SENSEA VSENSE Full Scale Input SENSEB ZINS Input Impedance Protection Circuit SENSEA VOV-1 Over Current SENSEB Voltage tOV-1 Reset Pulse Width VEX-1 tEX-1 Excess Current Voltage Reset Pulse Width
±0.625 3.45 0.95 11.2 -1.9 -2.4 11.2 16.1 3.75
Under Voltage Minimum OUTDIS Input High Current Input Current Outputs TMIN Output High VOUTA, VOUTA Voltage Output VOUTB, VOUTB Voltage Rise Time Fall Time Dead-Time Minimum Pulse Width
11.5
Generator VBBmin Minimum Negative Bias Negative Bias Voltage VREG Load Regulation Supply IDD1 IDD2 VBYPASS ZINBP Output High Volt. CPUMP Output Volt. Idle Current Operating Current Bypass Voltage BYPASS Impedance AGND
OUTDIS -1.4 IOUT -2.1 fOSC
1998 IXYS rights reserved
IXMS
Description IXMS
Nomenclature Dual Microstepping Controller
Sym. Description
IXMS
Negative Bias Generator Output: internal IXMS 150. Digital Ground
(Example) IXYS Dual Controller Package Type Plastic Skinny
AGND Analog Ground COMP Analog Compensation (see application notes recommendations). Analog Input: analog input range output pedance voltage source should drive these pins. input greater than
DGND
CPUMP Charge Pump Capacitor: Used internal Negative Bias Generator. OUTDIS Digital ENABLE input STATUS output: Forcing this causes pins low, disabling H-bridge. When uses output, state this indicates over current, excess current, insufficient +VDD error condition. Oscillator Frequency Dead-time set: Independent adjustment made oscillator frequency dead-time (see applications notes). Positive Supply Voltage
Temperature Range Industrial
SENSE Analog Sense: Each phases sense resistors connected these pins. Input range +0.625 FFWD FFWD, Motor High Voltage Compensation: voltage this sets oscillator amplitude. Input range 0.9-4 (see application notes recommendations). BYPASS Filter Cap: capacitor this provides filtering internal bias network. Output Stage: drive buffered power MOSFET H-Bridge.
numbers parantheses associated with channel
VOUT
1998 IXYS rights reserved
IXMS
Functional Description
Introduction IXMS150 designed with monolithic CMOS technology. primarily intended with twophase step motors microstepping mode also used control motors, audio amplifiers, application requiring synchronized PWMs. IXMS150 simultaneously controls currents each separate H-bridges. This device utilizes both analog digital functions. five fundamental sections: oscillator feedforward circuitry, analog section control motor currents, protection network protect H-bridges motor from abnormal conditions, digital logic control signals, power supply section which includes negative bias generator. Oscillator IXMS150 contains internal oscillator which controlled adjusting values These components determine switching frequency, amount dead time, minimum pulse width output pins minimum maximum values given Electrical Characteristics. oscillator also sets frequency charge pump circuit internal negative bias generator (VBB). lower frequencies (<40 kHz) value CPUMP must increased assure proper operation. Feedforward Compansation fixed frequency control systems open loop gain, motor current slew rate, motor current ripple proportional motor supply voltage. Gain variations supply voltage changes complicate design such systems restrict their bandwidth minimum worst case condition. this reason, advanced adaptive compensation scheme builtin using feedforward technique. This feature been designed such that open loop gain inversely proportional voltage applied FFWD pin, normally fraction motor supply. result, open loop gain made independent high voltage supply system bandwidth maximized. Analog Section analog section each channel IXMS150 consists signal processor error amplifier. signal processor required since voltage developed across sense resistor often contains transients associated with switching characteristics power devices. These transients need properly filtered system operate with desired degree precision. Because this, IXMS150 uses proprietary analog digital signal processing techniques that sense true average phase currents. Since this requires only sense resistor H-bridge avoids mismatches charge/discharge currents associated with sense resistor H-bridge topologies. instantaneous difference between motor current control input integrated comparator generate appropriate signals H-bridges. External compensation input sense signals provided comp1, comp2 comp3 pins. Protection Circuitry two-level Over/Excess Current protection circuit. Maximum current represented 0.625 SENSE input. SENSE voltage exceeds volts more than microsecond, switching outputs (VOUT) OUTDIS will forced low. This represents current that beyond full scale. SENSE voltage exceeds these outputs will forced immediately. This represents current that 500% beyond full scale. time delay lower level overcurrent avoids erroneous shutdowns result noise spikes that coupled from motor's Hbridges. Note that threshold voltages cited here assume supply Undervoltage Lockout third protection mechanism Under-Voltage Lockout. assures proper behavior power-up power-down avoids high power dissipation H-bridge insufficient gate voltage. uses zener reference trip point will also check make sure there sufficient negative bias insure proper operation. This typically -1.6 OUTDIS will held Lockout circuit until reach these values. Output Disable Feature enable external over-temperature protection, output disable (OUTDIS) available IXMS150. When pulled this disables output forcing output pins low. same output disable input also used status output. When pulled internal circuitry indicates error condition such undervoltage (VDD), insufficient negative bias voltage (VBB) over/excess current. This used status indicator smart systems. Section comparator generates complementary signals based output error amplifier. Dead-time then added which adjusted selection external oscillator capacitor. There also minimum duty cycle clamp circuit that allows coupled H-bridge. Supply Section main power supply (VDD) applied This typically Internal bias circuitry presents VDD/2 reference voltage BYPASS. capacitor should connected from analog ground noise immunity. Negative Bias Generator IXMS150 samples both positive negative voltages motor sense feedback resistor. addition, since errors input current around zero major contributor microstep positioning error, input control range bipolar specified full scale. these reasons desirable have both positive negative power supplies. order enable single supply operation, negative voltage generator regulator built into This charge pump circuit whose frequency that onboard oscillator. utilizes external pair capacitors diodes generate negative bias equal -VDD/5 approximately -2.4 1998 IXYS rights reserved
IXMS
Application Information
Introduction advantages step motors well known. They operated open loop fashion, accuracy which mostly dependent mechanical accuracy motor. They move quantized increments (steps) which lends them easily digitally controlled motion systems. addition, their drive signals square wave nature therefore easily generated with relatively high efficiency their ON/OFF characteristics. step motors free problems. Their large pulse drive waveforms create mechanical forces which excite aggravate mechanical resonances system. These load dependent difficult control since step motors have very little damping their own. resonance step motor system likely lose synchronization therefore skip gain step. Being open loop system, this would imply loss position information would unacceptable. common method solving this problem avoid band resonance frequencies altogether, this might severe limitations system performance. Steppers have steps revolution degrees step. highest resolution commercially available steppers have steps revolution degrees step. Microstepping Mode circumvent problems associated with step motors while still retaining their open loop advantages them microstepping mode. this mode each steps subdivided into smaller steps "microsteps". Applying currents both phases motor creates torque phaser which proportional vector both currents. When phasor completes "turn" (360 electrical degrees), motor moves exactly four full steps torque cycle. Similarly, when that phasor moves 22.5 electrical degrees motor will move (22.5/90) full step. Thus position motor determined angle torque phasor. When used with appropriate motor positioning accuracy full step achieved, equaling 0.036 degrees 1998 IXYS rights reserved full steps revolution motor. this manner motor positioned arbitrary angle. common control angle torque phasor applying motor's phases periodic waveforms shifted electrical degrees. phase current equations
Note that electrical position. resulting torque generated corresponding phases would then
where torque constant motor. Substituting Eqs. (1), into (3), doing vector summation resulting total generated torque measured motor shaft given Fig. Full Step Drive Waveforms accuracy, required resolution number microsteps step. Next, must determine accuracy required phase currents maintain accuracy complete system. Equations clearly indicate that errors absolute value phase phase currents will impact positioning accuracy. Another observation that keeping ratio phase currents iA/iB constant, errors their value will result Note that this case have zero torque ripple. Using this technique theoretically achieve infinite resolution with step motor. Since drive current waveforms sinusoidal instead square, step step oscillations eliminated associated velocity ripple. This greatly improves performance rotational speeds helps avoid resonance problems. actual application, extent which these things true depends sinusoidal reference waveforms generated. Seemingly have lost quantized motion feature stepper when used this mode. This regained defining term microsteps step. Each full step subdivided into microsteps applying motor's phases those intermediate current levels which their vector tracks circle Fig. divides full step electrical degrees) into require number microsteps. example required phase currents full step four microstep step operation shown Fig. respectively. Phase Current Matching Requirements Assuming microstepping being used resolution improvement resonance avoidance technique, step motor selected knowing torque needed, specified step
Fig. Four Microstep Step Drive Waveforms
IXMS
torque value errors positioning errors. question what upper bound current errors order keep position error within some given angle Referring Fig. assume required currents given Equations (1), respectively such that their vector points position phase currents vary small amount such that their vector lies within circle centered point having radius indicated Fig. H-bridge that must properly filtered system operate with desired degree precision. This presents significant engineering challenge that been solved IXYS's design team. Using proprietary analog digital signal processing techniques, IXYS developed control system that measures true average phase currents. Requiring only sense resistor H-bridge, this technique avoids errors mismatches charge/discharge currents associated with using sense resistor each H-bridge. This improves system performance well minimizing component count. sense resistor each H-bridge should selected based required peak motor current: 0.625 V/Impk
Fig. Simple Reference Waveform Generator tables stored DACs Fig. up/down counter used generate appropriate address locations ROMs data outputs used control DACs. user then need only supply down pulses counter control IXMS150 hence motor. higher performance systems microprocessor used place counter ROMs. micro perform look-up function calculate appropriate system responses, velocity profiles, etc. necessary total system operation. example this configuration shown Fig.
Fig. Effect Current Errors Position follows that worst case position error occurs cases where vector tangent circle such point which: i/l0
voltage developed across this resistor then applied corresponding sense input each H-bridge. Negative bias Generator today's cost cutting trends minimize number power supplies, implying single supply operation control section. current feedback reference inputs bipolar signals. Level shifting been used reference input past, that easily done feedback signal without impacting accuracy efficiency. practice finds that order generate true zero voltage having impedance drive there must negative power supply. Otherwise there will tradeoff sacrificing accuracy simpler system design. these reasons approach selected IXYS different. Taking advantage CMOS design, opted build into chip negative bias generator. This does stringent demands noise coupling results most flexible system having highest possible accuracy. built charge pump circuit requires capacitors diodes added externally. recommended component values oscillator frequency given below. 0.047 1N4148 Note: -(VDD/5) 1998 IXYS rights reserved
instance, keep position error less than full step, electrical angular error would 0.01 0.9° Fig. Microprocessor Based Referenced Waveform Generator Current Sensing Considerations Most commercially available monolithic controllers monitor control peak phase current comparing voltage across sense resistor with ramp voltage. This approach assumes that ripple current fix
Other recent searches
ZZ121 - ZZ121 ZZ121 Datasheet
X1286 - X1286 X1286 Datasheet
SN74CBT3126 - SN74CBT3126 SN74CBT3126 Datasheet
MC34726 - MC34726 MC34726 Datasheet
MAX791 - MAX791 MAX791 Datasheet
FBR610 - FBR610 FBR610 Datasheet
2SB1592 - 2SB1592 2SB1592 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
