The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

CMOS Gate Pinout CD4071BMS VIEW Features High-Volt


Datasheet Thumbnail

  

Download PDF



Top Searches for this datasheet



CD4071BMS, CD4072BMS CD4075BMS
CMOS Gate
Pinout
CD4071BMS VIEW
Features
High-Voltage Types (20V Rating) CD4071BMS Quad 2-Input Gate CD4072BMS Dual 4-Input Gate CD4075BMS Triple 3-Input Gate Medium Speed Operation: tPHL, tPLH 60ns (typ) 100% Tested Quiescent Current Maximum Input Current Over Full Package Temperature Range; 100nA +25oC Standardized Symmetrical Output Characteristics Noise Margin (Over Full Package Temperature Range): 2.5V Parametric Ratings Meets Requirements JEDEC Tentative Standard 13B, "Standard Specifications Description Series CMOS Devices"
J=A+B K=C+C
CD4072BMS VIEW
J=A+B+C+D
Description
CD4071BMS, CD4072BMS CD4075BMS gates provide system designer with direct implementation positive-logic function supplement existing family CMOS gates. CD4071BMS, CD4072BMS CD4075BMS supplied these lead outline packages: Braze Seal Frit Seal Ceramic Flatpack *CD4071, CD4072 *H4H CD4075 Only
CONNECTION
CD4075BMS VIEW
K=D+E+F
J=A+B+C
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
File Number
3323
7-444
CD4071BMS, CD4072BMS, CD4075BMS Functional Diagram
CD4071BMS
CD4072BMS
CD4075BMS
7-445
Specifications CD4071BMS, CD4072BMS, CD4075BMS
Absolute Maximum Ratings
Supply Voltage Range, (VDD) -0.5V +20V (Voltage Referenced Terminals) Input Voltage Range, Inputs .-0.5V +0.5V Input Current, Input .±10mA Operating Temperature Range -55oC +125oC Package Types Storage Temperature Range (TSTG) -65oC +150oC Lead Temperature (During Soldering) +265oC Distance 1/16 1/32 Inch (1.59mm 0.79mm) from case Maximum
Reliability Information
Thermal Resistance Ceramic FRIT Package 80oC/W 20oC/W Flatpack Package 70oC/W 20oC/W Maximum Package Power Dissipation (PD) +125 -55oC +100oC (Package Type 500mW +100oC +125oC (Package Type Derate Linearity 12mW/oC 200mW Device Dissipation Output Transistor 100mW Full Package Temperature Range (All Package Types) Junction Temperature +175oC
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP SUBGROUPS 18V, Input Leakage Current Input Leakage Current Output Voltage Output Voltage Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) Threshold Voltage Threshold Voltage Functional VOL15 VOH15 IOL5 IOL10 IOL15 IOH5A IOH5B IOH10 IOH15 VNTH VPTH 15V, Load 15V, Load (Note VOUT 0.4V 10V, VOUT 0.5V 15V, VOUT 1.5V VOUT 4.6V VOUT 2.5V 10V, VOUT 9.5V 15V, VOUT 13.5V 10V, -10µA 10µA 2.8V, 20V, 18V, Input Voltage (Note Input Voltage High (Note Input Voltage (Note Input Voltage High (Note 4.5V, 0.5V 4.5V, 0.5V 15V, 13.5V, 1.5V 15V, 13.5V, 1.5V +25oC, LIMITS TEMPERATURE +25oC +125oC -55oC +125oC -55oC +25oC +125oC -55oC +25oC, +125oC, -55oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +25oC +125oC -55oC +125oC, -55oC
PARAMETER Supply Current
SYMBOL
CONDITIONS (NOTE 20V,
-100 -1000 -100 0.53 -2.8
1000 -0.53 -1.8 -1.4 -3.5 -0.7
UNITS
+25oC, +125oC, -55oC 14.95
VDD/2 VDD/2
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC
NOTES: voltages referenced device GND, 100% testing being implemented. Go/No test with limits applied inputs.
accuracy, voltage measured differentially VDD. Limit 0.050V max.
7-446
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP SUBGROUPS TEMPERATURE +25oC +125oC, -55oC LIMITS UNITS
PARAMETER Propagation Delay
SYMBOL TPHL TPLH TTHL TTLH
CONDITIONS (NOTES
Transition Time
+25oC +125oC, -55oC
NOTES: 50pF, 200K, Input 20ns. -55oC +125oC limits guaranteed, 100% testing being implemented. TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE -55oC, +25oC +125 10V, +125oC 15V, -55oC, +25oC
4.95 9.95 0.36 0.64
0.25 -0.36 -0.64 -1.15 -2.0 -0.9 -2.6 -2.4 -4.2
UNITS
+125 Output Voltage Output Voltage Output Voltage Output Voltage Output Current (Sink) IOL5 Load 10V, Load Load 10V, Load VOUT 0.4V
+25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +125oC -55oC +25oC, +125oC, -55oC +25oC, +125oC, -55oC +25oC +25oC
Output Current (Sink)
IOL10
10V, VOUT 0.5V
Output Current (Sink)
IOL15
15V, VOUT 1.5V
Output Current (Source)
IOH5A
VOUT 4.6V
Output Current (Source)
IOH5B
VOUT 2.5V
Output Current (Source)
IOH10
10V, VOUT 9.5V
Output Current (Source)
IOH15
=15V, VOUT 13.5V
Input Voltage Input Voltage High Propagation Delay
TPHL TPLH
10V, 10V,
7-447
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Transition Time SYMBOL TTHL TTLH CONDITIONS Input NOTES TEMPERATURE +25oC +25oC
UNITS
Input Capacitance NOTES:
voltages referenced device GND. parameters listed Table controlled design process directly tested. These parameters characterized initial design release upon design changes which would affect these characteristics. 50pF, 200K, Input 20ns. TABLE POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current Threshold Voltage Threshold Voltage Delta Threshold Voltage Threshold Voltage Delta Functional SYMBOL VNTH CONDITIONS 20V, 10V, -10µA 10V, -10µA 10µA 10µA 18V, Propagation Delay Time TPHL TPLH +25oC NOTES TEMPERATURE +25oC +25oC +25oC +25oC +25oC
-2.8 VDD/2
-0.2 VDD/2 1.35 +25oC Limit
UNITS
NOTES: voltages referenced device GND. 50pF, 200K, Input 20ns.
Table +25oC limit. Read Record
TABLE BURN-IN LIFE TEST DELTA PARAMETERS +25OC PARAMETER Supply Current Output Current (Sink) Output Current (Source) SYMBOL IOL5 IOH5A ±0.1µA Pre-Test Reading Pre-Test Reading DELTA LIMIT
TABLE APPLICABLE SUBGROUPS CONFORMANCE GROUP Initial Test (Pre Burn-In) Interim Test (Post Burn-In) Interim Test (Post Burn-In) (Note Interim Test (Post Burn-In) (Note Final Test Group MIL-STD-883 METHOD 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 100% 5004 Sample 5005 GROUP SUBGROUPS Deltas Deltas IDD, IOL5, IOH5A READ RECORD IDD, IOL5, IOH5A IDD, IOL5, IOH5A IDD, IOL5, IOH5A
7-448
Specifications CD4071BMS, CD4072BMS, CD4075BMS
TABLE APPLICABLE SUBGROUPS (Continued) CONFORMANCE GROUP Group Subgroup Subgroup Group MIL-STD-883 METHOD Sample 5005 Sample 5005 Sample 5005 GROUP SUBGROUPS Deltas Subgroups READ RECORD Subgroups
NOTE: Parameteric, Functional; Cumulative Static
TABLE TOTAL DOSE IRRADIATION MIL-STD-883 METHOD 5005 TEST PRE-IRRAD POST-IRRAD Table READ RECORD PRE-IRRAD POST-IRRAD Table
CONFORMANCE GROUPS Group Subgroup
TABLE BURN-IN IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND -0.5V 50kHz 25kHz
PART NUMBER CD4071BMS Static Burn-In Note Static Burn-In Note Dynamic BurnIn Note Irradiation Note
PART NUMBER CD4072BMS Static Burn-In Note Static Burn-In Note Dynamic BurnIn Note Irradiation Note
PART NUMBER CD4075BMS Static Burn-In Note Static Burn-In Note Dynamic BurnIn Note Irradiation Note NOTE: Each except will have series resistor 0.5V Each except will have series resistor Group Subgroup sample size dice/wafer, failures, 0.5V
7-449
CD4071BMS, CD4072BMS, CD4075BMS
(5,9,
INPUTS PROTECTED CMOS PROTECTION NETWORK
FIGURE SCHEMATIC DIAGRAM CD4071BMS IDENTICAL GATES)
FIGURE LOGIC DIAGRAM CD4071BMS IDENTICAL GATES)
INV.1** (13)
(12)
(11)
(10)
INVERTERS IDENTICAL INVERTER
INPUTS PROTECTED CMOS PROTECTION NETWORK
FIGURE SCHEMATIC DIAGRAM CD4072BMS IDENTICAL GATES)
(12) (11) (10) (13)
FIGURE LOGIC DIAGRAM CD4072BMS IDENTICAL GATES)
7-450
CD4071BMS, CD4072BMS, CD4075BMS
INPUTS PROTECTED CMOS PROTECTION NETWORK
FIGURE SCHEMATIC DIAGRAM CD4075BMS IDENTICAL GATES)
FIGURE LOGIC DIAGRAM CD4075BMS IDENTICAL GATES)
Typical Performance Characteristics
PROPAGATION DELAY TIME (tPHL, tPLH) (ns) AMBIENT TEMPERATURE (TA) +25oC SUPPLY VOLTAGE (VDD) AMBIENT TEMPERATURE (TA) +25oC
OUTPUT VOLTAGE (VO)
SUPPLY VOLTAGE (VDD)
INPUT VOLTAGE (VIN)
LOAD CAPACITANCE (CL) (pF)
FIGURE TYPICAL VOLTAGE TRANSFER CHARACTERISTICS
FIGURE TYPICAL PROPAGATION DELAY TIME FUNCTION LOAD CAPACITANCE
7-451
CD4071BMS, CD4072BMS, CD4075BMS Typical Performance Characteristics
AMBIENT TEMPERATURE (TA) +25oC
(Continued)
OUTPUT (SINK) CURRENT (IOL) (mA)
OUTPUT (SINK) CURRENT (IOL) (mA)
AMBIENT TEMPERATURE (TA) +25oC
GATE-TO-SOURCE VOLTAGE (VGS)
15.0 GATE-TO-SOURCE VOLTAGE (VGS) 12.5 10.0
DRAIN-TO-SOURCE VOLTAGE (VDS)
DRAIN-TO-SOURCE VOLTAGE (VDS)
FIGURE TYPICAL OUTPUT (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) AMBIENT TEMPERATURE (TA) +25oC GATE-TO-SOURCE VOLTAGE (VGS)
FIGURE MINIMUM OUTPUT (SINK) CURRENT CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE (VDS) OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) +25oC GATE-TO-SOURCE VOLTAGE (VGS)
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-10V
-15V
-15V
FIGURE TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
FIGURE MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS
POWER DISSIPATION GATE (PD) (µW)
AMBIENT TEMPERATURE (TA) +25oC SUPPLY VOLTAGE (VDD)
AMBIENT TEMPERATURE (TA) TRANSITION TIME (tTHL, tTLH) (ns)
SUPPLY VOLTAGE (VDD)
50pF 15pF
LOAD CAPACITANCE (CL) (pF) INPUT FREQUENCY (fI) (kHz)
FIGURE TYPICAL TRANSITION TIME FUNCTION LOAD CAPACITANCE
FIGURE TYPICAL DYNAMIC POWER DISSIPATIONAS FUNCTION FREQUENCY
7-452
CD4071BMS, CD4072BMS, CD4075BMS Chip Dimensions Layouts
CD4071BMS
CD4072BMS
CD4075BMS Dimensions parentheses millimeters derived from basic inch dimensions indicated. Grid graduations mils (10-3 inch)
METALLIZATION: PASSIVATION:
Thickness:
Silane
BOND PADS: 0.004 inches 0.004 inches THICKNESS: 0.0198 inches 0.0218 inches
Intersil semiconductor products manufactured, assembled tested under ISO9000 quality systems certification.
Intersil products sold description only. Intersil Corporation reserves right make changes circuit design and/or specifications time without notice. Accordingly, reader cautioned verify that data sheets current before placing orders. Information furnished Intersil believed accurate reliable. However, responsibility assumed Intersil subsidiaries use; infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Intersil subsidiaries.
information regarding Intersil Corporation products, site http://www.intersil.com

Other recent searches


SPT7922 - SPT7922   SPT7922 Datasheet
LA-401 - LA-401   LA-401 Datasheet
HER301 - HER301   HER301 Datasheet
HER307 - HER307   HER307 Datasheet
GS71108ATP - GS71108ATP   GS71108ATP Datasheet
DA85xx - DA85xx   DA85xx Datasheet
CM50TF-28H - CM50TF-28H   CM50TF-28H Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive