This application note describes hardware software interface between 93

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Interfacing Intersil CDP68HC05 Microcontrollers with 93x6 Series Serial EEPROMs
This application note describes hardware software interface between 93x6 series serial EEPROMs Intersil CDP68HC05 microcontrollers. Serial EEPROMs excellent, cost solution storing data nonvolatile memory. Often, combination Intersil CDP68HC05 microcontroller serial EEPROM less expensive than buying with on-chip EEPROM. 93x6 serial EEPROMs industry standard devices manufactured many companies including Microchip, National Atmel. Serial EEPROMs available various memory sizes ranging from 1kbit 64kbit beyond. This application note deals only with 93x6 family EEPROMs; specifically 9346 (1kbit), 9356 (2kbit) 9366 (4kbit). These devices offered several manufacturers wide assortment packaging options, operating voltages temperatures. Advantages three-wire interface include compatibility with SIOP controllers available Intersil microcontrollers, fast (2MHz max. rates cost. Drawbacks many (four minimum) lines needed interface EEPROM. should noted that serial EEPROMs with interface also available. These devices have advantage using less interfacing (only port pins needed) larger memory sizes. systems where advantages three wire interface 93x6 EEPROM lost because lack SIOP, EEPROMs better solution because savings. more information interfacing Intersil MCUs with compatible EEPROMs, application note AN9704, "Interfacing Intersil CDP68HC05 Microcontroller With Serial EEPROMs". memory size interface serial EEPROM should, course, decided such factors price, availability, code size, performance ease use. data sheets downloaded internet http://www.intersil.com/68hc05. Data sheets EEPROMs available from their respective manufacturers.
Hardware
hardware interface EEPROMs quite simple. 93x6 EEPROMs require following four connections: Data where data being sent EEPROM enters device. This always high impedance input pin. Data where data being sent from EEPROM leaves device. This usually high impedance state except when EEPROM selected this outputting data result READ command) status condition. Serial ClocK input that used receive synchronizing clock generated MCU. Data being sent EEPROM latched internally rising edge SCK. Data being sent should latched falling edge. Chip Select active signal that used enable EEPROM synchronize start data transmission. Additionally, EEPROM must connected either GND. state determines memory organization EEPROM. When this logic level, EEPROM configures itself into array 16-bit words; data written read from EEPROM word size transfers. Conversely, logic "0", EEPROM configured into array 8-bit bytes. circuit diagram each interface methods shown figures below. Note that circuits shown below connected either 16-bit 8-bit position.
Overview
different methods hardware interfacing between Intersil CDP68HC05 microcontrollers 93x6 series EEPROMs described this application note. first technique uses Serial Peripheral Interface (SPI) system controller found higher 68HC05 devices like CDP68HC05C8B CDP68HC05C16B. second scheme interface which uses software manipulation pins (often referred "bit banging"). second interface implemented with member CDP68HC05 family. Please note that this application note intended detail interface Intersil CDP68HC05 93x6 series serial EEPROM; assumes user familiar with access technical data sheets microcontrollers EEPROMs described. Free copies Intersil 68HC05
68HC05 MOSI MISO
93x6
FIGURE 68HC05 93x6 EEPROM INTERFACE
http://www.intersil.com 407-727-9207 Copyright
Intersil Corporation 1999
Application Note 9793
auto-erasing erase erase commands exist.
68HC05
93x6
ERAL (Erase All). This command similar erase instruction just described, except that erases entire EEPROM memory, just specific location. Like erase instruction, this command will work EEPROM erase/write disable state. execute this command sends start bit, four "0010" opcode, followed many null clocks determined device configuration. WRITE write instruction writes either byte word (depending organization device) address specified command. This command will work EEPROM erase/write disabled mode. execute this command sends start bit, "01" opcode, address location written followed data written. WRAL (Write All). WRAL instruction similar ERAL command that affects data EEPROM. WRAL writes data sent after opcode every location memory. This command will work erases writes EEPROM disabled. execute this command sends start bit, four "0001" opcode, dummy bits, followed data written every memory location. EWDS (Erase/Write Disable). erase/write disable instruction puts EEPROM into state where data erased from written EEPROM. This good protection feature guard against inadvertent data corruption EEPROM noise program failure MCU. Once this command issued, write erase commands will ignored until EWEN command sent. EEPROM powers erase/write disabled state. execute this command sends start bit, four "0000" opcode, followed many null clocks determined device configuration. Using these seven basic commands data very easily stored read from EEPROM.
FIGURE 68HC05 93x6 EEPROM BANGING INTERFACE
EEPROM Command
93x6 series serial EEPROMs designed recognize series seven different commands. With these commands host read, write, erase, fill, enable disable EEPROM. Although implemented with different numbers cycles addressing methods from device device, functionality these commands uniform throughout entire family. Each command sent EEPROM begins with start bit, followed opcode (either four bits), either address null data and, data accessing instructions (read, write, etc.), data. short discussion each command follows. READ read command does exactly what name implies reads data from EEPROM. execute this command sends start bit, "10" opcode, followed address data read. Once address received EEPROM, data will shifted pin. EWEN (Erase/Write Enable). avoid accidental data corruption, 93x6 EEPROMs have ability disable data from being written erased from memory. When EEPROM erase/write disabled state, data still read from device, data altered until EWEN command sent. execute this command sends start bit, four "0011" opcode, followed many null clocks determined device configuration. should noted that these EEPROMs power erase/write disabled state. ERASE erase command erases location EEPROM memory specified address send during command. erased state EEPROM $FF. This command will work unless EWEN instruction been issued enable erases writes EEPROM. execute this command sends start bit, "11" opcode, followed address location erased. should noted that this command hold over from older members 93x6 family that required location erased before written. Almost modern 93x6 EEPROMs auto-erasing data written without erasing first. result erase erase instructions used little all. fact, some manufacturers have even removed them from instruction EEPROM. Check data sheets EEPROM find
Software
shown Figure hardware interface 93x6 EEPROMs very simple straight forward. responsibility software configure, address, read write EEPROM. this section will discuss seven commands recognized EEPROM. following sections provide details implement these commands with different hardware interfaces. listing software routines described this application note given Appendices OVERVIEW first step being able communicate with 93x6 series EEPROMs implementing seven commands listed previous section. Once this been done, more complex subroutines created using these com-
Application Note 9793
mands building blocks. next sections will detail implementation these seven commands polled port systems. Note that following explanations code listings, each command been implemented stand alone routine each device type, 68HC05 interface data length 16-bit). While this leads quite large number subroutines included listing file this application note each interface type, all!), this been done very specific reason. Many these subroutines could have been combined using assembler directives "IF-THEN-ELSE" clauses. While this would reduce amount code, would also complicate listing unnecessary code those wishing implement only type interface (e.g. 8-bit SIOP interface 9356 EEPROM), would usually case. subroutines listed here have been written that potential users simply copy them into their source code them as-is. subroutines have been named systematically according function they implement, device type, data length interface type. Thus, "read_46_16_bb" subroutine implements read command 9346 EEPROM using 16-bit data words bit-banging interface. subroutines named such. following discussion EEPROM subroutines, each type interface discussed general. When necessary, certain aspects subroutines discussed detail. most part, however, interface routines simple straight forward enough understood reading source file. following true subroutines listed appendices this application note pertinent understanding source code: address that being accessed EEPROM contained variables named "pcHi" "pcLo". EEPROM address formed concatenating "pcHi:pcLo". 8-bit organizations, data written data read passed from subroutines accumulator. 16-bit modes data passed from subroutines with high byte accumulator byte index register (i.e., A:X). routines interrupt driven enabling SPIE flag SPCR writing appropriate interrupt service routine (ISR). Since each seven subroutines would generate same interrupt, would have know which command currently executed that could complete command correctly. This approach substantially more involved than polled version generally used applications where processor time critical. code listing interface subroutines 9346, 9356 9366 included Appendix beginning each interface subroutines there call "spi_init" subroutine. "spi_init" subroutine sets system with 68HC05 master mode, frequency divide four (this code written CDP68HC05C16B running 8MHz), polarity phase appropriate (see below). "spi_init" also makes sure Port pins proper state (this necessary only C16B MCU; technical data sheet more information). 93x6 EEPROMs sample input data RISING edge SCK. such, should that either CPOL=CPHA=0 CPOL=CPHA=1. former preferred setting what implemented throughout this application note. However, when transferring data MCU, 68HC05 should latch incoming data FALLING edge SCK. such CPOL must inverted during slave transmission portion READ instruction. discussed previously, each command sent EEPROM consists start bit, opcode, either dummy cycles data. total number bits necessary complete successful transfer range from (using 9346 16-bit mode) (using 9366 8-bit mode). Note, however, that system transfers bits byte size packets only. This problem easily overcome, however, adding extra "0"s beginning data transfer until total number bits sent evenly divisible example, send EWEN command 9346 8-bit mode, following data must sent:
START 0011 XXXXX DUMMY BITS
OPCODE
Interface
SOFTWARE This section describes interface 93x6 series EEPROMs with Serial Peripheral Interface. This section assumes reader familiar with access documentation 68HC05 question. interface fastest arguably easier types implement. hardware 68HC05 takes care data shifting that software write data SPDR wait SPIF flag set. These routines operate polled basis, i.e., they continuously loop while polling SPIF whenever transmission progress. easily change these
send these bits EEPROM 8-bit chunks, beginning data stream with enough "0"s arrive bits, like
000000 0011 XXXXX
PADDING
START
OPCODE
DUMMY BITS
have bits send EEPROM. start data transfer, 68HC05 would write first bits, %00000010, SPDR. When this data shifted final bits, %011xxxxx, written SPDR sent. This transmission scheme works because EEPROM ignores everything until gets start bit. start
Application Note 9793
defined both pins being high rising edge SCK. Once this condition occurs does cycle data transfer this example) EEPROM begins shifting data executes whatever opcode sent. this that data transmission mode begin. Note that example code listed, "don't care" "dummy" bits, indicated with above, sent "0"s. While padding beginning every transfer adds unnecessary cycles transmission thus lengthens transfer time), transfer rate fastest method available interface with EEPROMs. EWDS, EWEN, ERAL ERASE These so-called "short commands" because they require additional data sent apart command. such, these shortest commands available given interface type. four these commands implemented similarly have same basic organization: start part opcode sent with appropriate number padding "0"s. After SPIF flag indicating that transmission done, rest opcode either dummy bits (EWDS, EWEN ERAL) address (ERASE) sent. Once second transmission completed, SPIF flag cleared, EEPROM line lowered subroutine returns main program. WRITE WRAL their names imply, these data modification instructions EEPROM. Both these instruction take same number cycles complete. WRAL includes several dummy bits does need address like WRITE. These commands implemented like start part opcode sent with appropriate number padding "0"s. After SPIF flag indicating that transmission done, rest opcode either dummy bits (WRAL) address (WRITE) sent. Once second transmission completed, data transferred subroutine sent EEPROM. EEPROM 8-bit mode, this requires only additional transfer. EEPROM 16-bit mode, more transfers necessary. Once data transmission completed, SPIF flag cleared, EEPROM line lowered subroutine returns main program. READ READ instruction quite different from other commands that only that receives data from EEPROM. mentioned previously, this data reception requires phase inverted from that transmission phase. READ command implemented such: start part opcode sent with appropriate number padding "0"s. After SPIF flag indicating that transmission done, rest opcode address sent. Once second transmission completed, changes polarity correctly receive data from EEPROM. Next dummy bytes written SPDR initiate transfer during which EEPROM shifts data. EEPROM ignores data sent during this phase, anything written SPDR start transfer. EEPROM 16-bit mode, this procedure must repeated receive both data bytes. Once data transmission completed, SPIF flag cleared, polarity reset transmission, EEPROM line lowered subroutine returns main program with data from EEPROM accumulator case 16-bit transmissions).
Standard Port ("Bit Bang") Interface
This section describes interface 93x6 series EEPROMs using standard bidirectional ports available every Intersil 68HC05 This interface more software intensive than interface detailed previous section. does, however, have advantage that implemented member 68HC05 family that required four free pins. This type interface especially attractive those using small, inexpensive MCUs with serial ports like CDP68HC05J4B CDP68HC05P1B. code listing bit-banging interface subroutines 9346, 9356 9366 included Appendix Along with subroutines which implement seven EEPROM commands, there four additional "common" subroutines that used command routines perform basic functions like setting I/O, transmitting bits, receiving bits, waiting EEPROM complete write operation. These routines need invoked whenever command subroutines used. When command routine called, must first call "eep_su" subroutine. This subroutine responsibility setting EEPROM interface properly rest functions. interface lines dedicated exclusively EEPROM altered between function calls, this subroutine call omitted from beginning each EEPROM function long before command routines called. discussed previously, each command sent EEPROM consists start bit, opcode, either dummy bits data. total number bits needed complete successful transfer range from (using 9346 16-bit mode) (using 9366 8-bit mode). Unlike interface, bit-bang interface send exact number bits required operation being preformed. Thus, there need "padding" bits transmitted part
Application Note 9793
transmission. "BBsend" subroutine, four basic routines mentioned earlier, takes care task shifting bits. This routine shifts upper bits byte passed accumulator. number bits sent, passed "BBsend" routine register. Data transmitted same fashion command routines: total number bits sent calculated. This number divided into many 8-bit "chunks" possible. remaining bits sent part first transmission. example: writing 9366 style EEPROM 16-bit mode requires bits sent (101 address bits data bits). These bits divided into many 8-bit packets possible this case). remaining three bits sent first transmission. next three transmissions EEPROM bits long. Similar "BBsend" function, `BBrecv" subroutine used shift data from EEPROM during read operation. This routine always shifts bits (all transmissions from EEPROM either bits wide) returns value accumulator. Note that only time "BBrecv" routine called from READ subroutine. decided make this function subroutine 16-bit interfaces which need call twice. implementing 8-bit interface replace "BBrecv" subroutine call READ function with code from subroutine itself. Doing will slightly reduce code size execution time bytes processor cycles will saved). 93x6 series EEPROMs require preform write (WRITE WRAL) erase (ERASE ERAL) instructions. During this time EEPROM will respond additional operations from MCU. When this state EEPORM signals that busy holding low. these routines, "waitBB" subroutine called. This function continuously polls line EEPROM waits high, indicating that internal operation complete. EWDS, EWEN, ERAL ERASE These so-called "short commands" because they require additional data sent apart command. such, these shortest commands available given interface type. three these commands implemented similarly have same basic organization: start part opcode sent using "BBsend" function. Because "BBsend" function send different amounts data (dictated contents register), number bits sent during this part operation depends device data interface selected. Upon return from "BBsend" routine remaining bits opcode either dummy bits (EWDS, EWEN ERAL) address (ERASE) sent using "BBsend" routine. Once second transmission completed, EEPROM line lowered deselect EEPROM. EWDS EWEN routines return main program while ERASE ERAL routines jump "waitBB" function before returning. WRITE WRAL their names imply, these data modification instructions EEPROM. Both these instructions take same number cycle complete. WRAL includes several dummy bits does need address like WRITE. These commands implemented like start part opcode sent. rest opcode either dummy bits (WRAL) address (WRITE) sent. Once second transmission completed, data transferred subroutine sent EEPROM. EEPROM 8-bit mode, this requires only additional transfer. EEPROM 16-bit mode, more transfers necessary. Once data transmission completed, EEPROM line lowered subroutine jumps "waitBB" function wait EEPROM complete write before returning main program. READ READ instruction quite different from other commands that only that receives data from EEPROM. mentioned previously, this data reception requires "BBrecv" subroutine, this only place where this function called. READ command implemented such: start part opcode sent. When transmission done, rest opcode address sent. "BBrecv" subroutine called receive data from EEPROM. BBrecv shifts data opposite clock edge. This done once 8-bit mode twice 16-bit mode. Once data transmission completed, EEPROM line lowered subroutine returns main program with data from EEPROM accumulator case 16-bit transmissions).
Conclusion
Serial EEPROMs small, inexpensive extensions CDP68HC05 microcontrollers without chip EEPROM. Often, chip solution will cheaper than purchasing 68HC05 variant with EEPROM. Serial EEPROMs easy require little external support circuitry. should noted many serial EEPROMs have additional capabilities beyond single byte read write detailed here. Depending upon device manufacturer, other functions such block reads, block writes, security options also available. Check technical data sheet EEPROM manufacturer more information about capabilities particular serial EEPROM.
Application Note 9793 Appendix Code Listing Interface Routines
INTERSIL Corporation (c)1990 1997 68HC05 Assembler Version 3.0.2 Filename: 93X6_SPI.LST Source Created:08/19/97, 10:34 Assembled: 08/19/97, 10:35 00001 00002 Three Wire Serial EEPROM Interface Routines 00003 00004 following subroutines written interface 00005 9346, 9356 9366 series serial EEPROMs with Intersil 00006 CDP68HC05 microcontroller using Serial Peripheral Interface 00007 polled manor. seven basic commands (READ, EWEN, 00008 ERASE, ERAL, WRITE, WRAL, EWDS) both configurations each 00009 EEPROM bit) included. Note that commands 00010 9356 9366 identical have been included only once 00011 both types. naming following subroutines defined 00012 fully describe their function: 00013 00014 00015 00016 00017 #include <c16b.s> START INCLUDE C:\6805\C16B.S -00001 #nolist 00142 #list 00018 00019 00020 00021 $0003 00022 $0000 00023 $0000 00024 $0004 00025 $0002 00026 $0003 00027 $0005 00028 00029 00030 00031 0050 00032 00033 0050 00034 0051 00035 0052 00036 0053 00037 00038 00039 00040 1000 00041 00042 00043 00044 00045 00046 00047 1000 CD13EA 00048 1003 A603 00049 1005 B70C 00050 1007 0F0BFD 00051 100A B651 00052 100C A47F 00053 100E B70C 00054 1010 0F0BFD INCLUDE C:\6805\C16B.S Define Statements spi_port eep_csp eep_cs miso mosi Variables section RAMvars, pcHi pclo tempa tempx Subroutines section Subs, $1000 93LC46 routines read_46_8_spi spi_init ;init #%00000011 ;read opcode dummy spdr ;send through brclr spif,spsr,* ;loop until done pclo ;get EEPROM address #$7F ;mask bits, MSB=0 spdr ;and send brclr spif,spsr,* ;loop until done ;High byte EEPROM data address ;Low byte EEPROM data address ;temp location ;temp location portd porta
Application Note 9793
00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 1013 1015 1017 101A 101C 101E 140A B70C 0F0BFD B60C 1100 bset brclr bclr ewen_46_8_spi brclr brclr bclr erase_46_8_spi brclr brclr bclr eral_46_8_spi brclr brclr bclr write_46_8_spi brclr brclr brclr bclr wral_46_8_spi cpha,spcr spdr spif,spsr,* spdr eep_cs,eep_csp ;set phase ;dummy write receive data ;loop until done ;get returned data from EEPROM ;disable eeprom ;and return
101F 1022 1024 1026 1029 102B 102D 1030 1032 1034
CD13EA A602 B70C 0F0BFD A660 B70C 0F0BFD B60C 1100
spi_init #%00000010 spdr spif,spsr,* #%01100000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewen opcode, part ;wait ;ewen opcode, part ;wait ;clear SPIF ;disable eeprom
1035 1038 103A 103C 103F 1041 1043 1045 1048 104A 104C
CD13EA A603 B70C 0F0BFD B651 AA80 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00000011 spdr spif,spsr,* pcLo #$80 spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;erase opcode ;wait ;erase address ;set (part opcode) ;wait ;clear SPIF ;disable eeprom
104F 1052 1054 1056 1059 105B 105D 1060 1062 1064
CD13EA A602 B70C 0F0BFD A640 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00000010 spdr spif,spsr,* #%01000000 spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;eral opcode, part ;wait ;eral opcode, part ;wait ;clear SPIF ;disable eeprom
1067 1069 106C 106E 1070 1073 1075 1077 1079 107C 107E 1080 1083 1085 1087 1089
B752 CD13EA A602 B70C 0F0BFD B651 AA80 B70C 0F0BFD B652 B70C 0F0BFD B60C B652 1100 CC13FD
tempA spi_init #%00000010 spdr spif,spsr,* pclo #$80 spdr spif,spsr,* tempA spdr spif,spsr,* spdr tempA eep_cs,eep_csp wait
;init ;write opcode dummy ;send through ;loop until done ;get EEPROM address ;set MSB=1 (part opcode) ;and send ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;return same data sent ;disable eeprom
108C 108E 1091 1093
B752 CD13EA A602 B70C
tempA spi_init #%00000010 spdr
;init ;wral opcode part ;send through
Application Note 9793
00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188 1095 1098 109A 109C 109F 10A1 10A3 10A6 10A8 10AA 10AC 0F0BFD A620 B70C 0F0BFD B652 B70C 0F0BFD B60C B652 1100 CC13FD brclr brclr brclr bclr ewds_46_8_spi brclr brclr bclr spif,spsr,* #%00100000 spdr spif,spsr,* tempA spdr spif,spsr,* spdr tempA eep_cs,eep_csp wait ;loop until done ;wral opcode, part ;and send ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;return same data sent ;disable eeprom
10AF 10B2 10B4 10B6 10B9 10BB 10BD 10C0 10C2 10C4
CD13EA A602 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100
spi_init #%00000010 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewds opcode, part ;wait ;ewds opcode, part ;wait ;clear SPIF ;disable eeprom
10C5 10C8 10CA 10CC 10CF 10D1 10D3 10D5 10D7 10DA 10DC 10DE 10E1 10E3 10E5 10E8 10EA 10EC
CD13EA A601 B70C 0F0BFD B651 A43F AB80 B70C 0F0BFD 140A B70C 0F0BFD B60C B70C 0F0BFD BE0C 1100
93LC46 routines read_46_16_spi spi_init ;init #%00000001 ;read opcode spdr ;send through brclr spif,spsr,* ;loop until done pclo ;get EEPROM address #$3F ;mask bits #%10000000 ;add rest opcode spdr ;and send brclr spif,spsr,* ;loop until done bset cpha,spcr ;set phase spdr ;dummy write receive data brclr spif,spsr,* ;loop until done spdr ;get returned data from EEPROM spdr ;dummy write receive data brclr spif,spsr,* ;loop until done spdr ;get returned data from EEPROM bclr eep_cs,eep_csp ;disable eeprom ;and return ewen_46_16_spi brclr brclr bclr erase_46_16_spi brclr
10ED 10F0 10F2 10F4 10F7 10F9 10FB 10FE 1100 1102
CD13EA A601 B70C 0F0BFD A630 B70C 0F0BFD B60C 1100
spi_init #%00000001 spdr spif,spsr,* #%00110000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewen opcode, part ;wait ;ewen opcode, part ;wait ;clear SPIF ;disable eeprom
1103 1106 1108 110A 110D
CD13EA A601 B70C 0F0BFD B651
spi_init #%00000001 spdr spif,spsr,* pcLo
;init ;erase opcode ;wait ;erase address
Application Note 9793
00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 00251 00252 00253 00254 00255 110F 1111 1113 1116 1118 111A AAC0 B70C 0F0BFD B60C 1100 CC13FD brclr bclr eral_46_16_spi brclr brclr bclr write_46_16_spi brclr brclr brclr brclr bclr wral_46_16_spi brclr brclr brclr brclr bclr ewds_46_16_spi brclr brclr bclr #$C0 spdr spif,spsr,* spdr eep_cs,eep_csp wait ;set bits opcode ;wait ;clear SPIF ;disable eeprom
111D 1120 1122 1124 1127 1129 112B 112E 1130 1132
CD13EA A601 B70C 0F0BFD A620 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00000001 spdr spif,spsr,* #%00100000 spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;eral opcode, part ;wait ;eral opcode, part ;wait ;clear SPIF ;disable eeprom
1135 1137 113A 113C 113E 1141 1143 1145 1147 1149 114C 114E 1150 1153 1155 1158 115A 115C
B752 CD13EA A601 B70C 0F0BFD B651 A43F AB40 B70C 0F0BFD B652 B70C 0F0BFD BF0C 0F0BFD B60C 1100 CC13FD
tempA spi_init #%00000001 spdr spif,spsr,* pclo #$3F #%01000000 spdr spif,spsr,* tempA spdr spif,spsr,* spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;write opcode dummy ;send through ;loop until done ;get EEPROM address ;mask ;add rest opcode ;and send ;loop until done ;write data EEPROM ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;disable eeprom
115F 1161 1164 1166 1168 116B 116D 116F 1172 1174 1176 1179 117B 117E 1180 1182
B752 CD13EA A601 B70C 0F0BFD A610 B70C 0F0BFD B652 B70C 0F0BFD BF0C 0F0BFD B60C 1100 CC13FD
tempA spi_init #%00000001 spdr spif,spsr,* #%00010000 spdr spif,spsr,* tempA spdr spif,spsr,* spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;wral opcode part ;send through ;loop until done ;wral opcode, part ;and send ;loop until done ;write data EEPROM ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;disable eeprom
1185 1188 118A 118C 118F 1191 1193 1196 1198
CD13EA A601 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100
spi_init #%00000001 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewds opcode, part ;wait ;ewds opcode, part ;wait ;clear SPIF ;disable eeprom
Application Note 9793
00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 119A
119B 119E 11A0 11A2 11A5 11A7 11A9 11AC 11AE 11B0 11B3 11B5 11B7
CD13EA A60C B70C 0F0BFD B651 B70C 0F0BFD 140A B70C 0F0BFD B60C 1100
93LC56 routines read_56_8_spi spi_init ;init #%00001100 ;read opcode dummy spdr ;send through brclr spif,spsr,* ;loop until done pclo ;get EEPROM address spdr ;and send brclr spif,spsr,* ;loop until done bset cpha,spcr ;set phase spdr ;dummy write receive data brclr spif,spsr,* ;loop until done spdr ;get returned data from EEPROM bclr eep_cs,eep_csp ;disable eeprom ;and return ewen_56_8_spi brclr brclr bclr erase_56_8_spi brclr brclr bclr eral_56_8_spi brclr brclr bclr write_56_8_spi brclr
11B8 11BB 11BD 11BF 11C2 11C4 11C6 11C9 11CB 11CD
CD13EA A609 B70C 0F0BFD A680 B70C 0F0BFD B60C 1100
spi_init #%00001001 spdr spif,spsr,* #%10000000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewen opcode, part ;wait ;ewen opcode, part ;wait ;clear SPIF ;disable eeprom
11CE 11D1 11D3 11D5 11D8 11DA 11DC 11DF 11E1 11E3
CD13EA A60E B70C 0F0BFD B651 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00001110 spdr spif,spsr,* pcLo spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;erase opcode ;wait ;erase address ;wait ;clear SPIF ;disable eeprom
11E6 11E9 11EB 11ED 11F0 11F2 11F4 11F7 11F9 11FB
CD13EA A609 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00001001 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;eral opcode, part ;wait ;eral opcode, part ;wait ;clear SPIF ;disable eeprom
11FE 1200 1203 1205 1207 120A 120C
B752 CD13EA A60A B70C 0F0BFD B651 B70C
tempA spi_init #%00001010 spdr spif,spsr,* pclo spdr
;init ;write opcode dummy ;send through ;loop until done ;get EEPROM address ;and send
Application Note 9793
00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 00386 00387 00388 00389 120E 1211 1213 1215 1218 121A 121C 121E 0F0BFD B652 B70C 0F0BFD B60C B652 1100 CC13FD brclr brclr bclr wral_56_8_spi brclr brclr brclr bclr ewds_56_8_spi brclr brclr bclr spif,spsr,* tempA spdr spif,spsr,* spdr tempA eep_cs,eep_csp wait ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;return same data sent ;disable eeprom
1221 1223 1226 1228 122A 122D 122F 1231 1234 1236 1238 123B 123D 123F 1241
B752 CD13EA A608 B70C 0F0BFD A680 B70C 0F0BFD B652 B70C 0F0BFD B60C B652 1100 CC13FD
tempA spi_init #%00001000 spdr spif,spsr,* #%10000000 spdr spif,spsr,* tempA spdr spif,spsr,* spdr tempA eep_cs,eep_csp wait
;init ;wral opcode part ;send through ;loop until done ;wral opcode, part ;and send ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;return same data sent ;disable eeprom
1244 1247 1249 124B 124E 1250 1252 1255 1257 1259
CD13EA A608 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100
spi_init #%00001000 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewds opcode, part ;wait ;ewds opcode, part ;wait ;clear SPIF ;disable eeprom
125A 125D 125F 1261 1263 1265 1268 126A 126C 126F 1271 1273 1276 1278 127A
CD13EA B650 A401 AB0C B70C 0F0BFD B651 B70C 0F0BFD 140A B70C 0F0BFD B60C 1100
93LC66 routines read_66_8_spi spi_init ;init pcHi ;get from pcHi #$01 ;mask #%00001100 ;read opcode dummy spdr ;send through brclr spif,spsr,* ;loop until done pclo ;get EEPROM address spdr ;and send brclr spif,spsr,* ;loop until done bset cpha,spcr ;set phase spdr ;dummy write receive data brclr spif,spsr,* ;loop until done spdr ;get returned data from EEPROM bclr eep_cs,eep_csp ;disable eeprom ;and return ewen_66_8_spi brclr
127B 127E 1280 1282 1285 1287
CD13EA A609 B70C 0F0BFD A680 B70C
spi_init #%00001001 spdr spif,spsr,* #%10000000 spdr
;init ;ewen opcode, part ;wait ;ewen opcode, part
Application Note 9793
00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 00448 00449 00450 00451 00452 00453 00454 00455 00456 1289 128C 128E 1290 0F0BFD B60C 1100 brclr bclr erase_66_8_spi brclr brclr bclr eral_66_8_spi brclr brclr bclr write_66_8_spi brclr brclr brclr bclr wral_66_8_spi brclr brclr brclr bclr spif,spsr,* spdr eep_cs,eep_csp ;wait ;clear SPIF ;disable eeprom
1291 1294 1296 1298 129A 129C 129F 12A1 12A3 12A6 12A8 12AA
CD13EA B650 A401 AB0E B70C 0F0BFD B651 B70C 0F0BFD B60C 1100 CC13FD
spi_init pcHi #$01 #%00001110 spdr spif,spsr,* pcLo spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;get from pcHi ;mask ;erase opcode ;wait ;erase address ;wait ;clear SPIF ;disable eeprom
12AD 12B0 12B2 12B4 12B7 12B9 12BB 12BE 12C0 12C2
CD13EA A609 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00001001 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;eral opcode, part ;wait ;eral opcode, part ;wait ;clear SPIF ;disable eeprom
12C5 12C7 12CA 12CC 12CE 12D0 12D2 12D5 12D7 12D9 12DC 12DE 12E0 12E3 12E5 12E7 12E9
B752 CD13EA B650 A401 AB0A B70C 0F0BFD B651 B70C 0F0BFD B652 B70C 0F0BFD B60C B652 1100 CC13FD
tempA spi_init pcHi #$01 #%00001010 spdr spif,spsr,* pclo spdr spif,spsr,* tempA spdr spif,spsr,* spdr tempA eep_cs,eep_csp wait
;init ;get from pcHi ;mask ;write opcode dummy ;send through ;loop until done ;get EEPROM address ;and send ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;return same data sent ;disable eeprom
12EC 12EE 12F1 12F3 12F5 12F8 12FA 12FC 12FF 1301 1303 1306 1308 130A 130C
B752 CD13EA A608 B70C 0F0BFD A680 B70C 0F0BFD B652 B70C 0F0BFD B60C B652 1100 CC13FD
tempA spi_init #%00001000 spdr spif,spsr,* #%10000000 spdr spif,spsr,* tempA spdr spif,spsr,* spdr tempA eep_cs,eep_csp wait
;init ;wral opcode part ;send through ;loop until done ;wral opcode, part ;and send ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;return same data sent ;disable eeprom
Application Note 9793
00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495 00496 00497 00498 00499 00500 00501 00502 00503 00504 00505 00506 00507 00508 00509 00510 00511 00512 00513 00514 00515 00516 00517 00518 00519* 00520 00521 00522 00523 130F 1312 1314 1316 1319 131B 131D 1320 1322 1324 CD13EA A608 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100 ewds_66_8_spi brclr brclr bclr spi_init #%00001000 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp ;init ;ewds opcode, part ;wait ;ewds opcode, part ;wait ;clear SPIF ;disable eeprom
1325 1328 132A 132C 132F 1331 1333 1336 1338 133A 133D 133F 1341 1344 1346 1348
CD13EA A606 B70C 0F0BFD B651 B70C 0F0BFD 140A B70C 0F0BFD B60C B70C 0F0BFD BE0C 1100
93LC56 93LC66 routines NOTE: These routines work both 9356 9366 equally without modification. read_566_16_spi spi_init ;init #%00000110 ;read opcode dummy spdr ;send through brclr spif,spsr,* ;loop until done pclo ;get EEPROM address spdr ;and send brclr spif,spsr,* ;loop until done bset cpha,spcr ;set phase spdr ;dummy write receive data brclr spif,spsr,* ;loop until done spdr ;get returned data from EEPROM spdr ;dummy write receive data brclr spif,spsr,* ;loop until done spdr ;get returned data from EEPROM bclr eep_cs,eep_csp ;disable eeprom ;and return ewen_566_16_spi brclr brclr bclr erase_566_16_spi brclr brclr bclr eral_566_16_spi brclr
1349 134C 134E 1350 1353 1355 1357 135A 135C 135E
CD13EA A604 B70C 0F0BFD A6C0 B70C 0F0BFD B60C 1100
spi_init #%00000100 spdr spif,spsr,* #%11000000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewen opcode, part ;wait ;ewen opcode, part ;wait ;clear SPIF ;disable eeprom
135F 1362 1364 1366 1369 136B 136D 1370 1372 1374
CD13EA A607 B70C 0F0BFD B651 B70C 0F0BFD B60C 1100 CC13FD
spi_init #%00000111 spdr spif,spsr,* pcLo spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;erase opcode ;wait ;erase address ;wait ;clear SPIF ;disable eeprom
1377 1379 137B 137D 1380
AD71 A604 B70C 0F0BFD A680
spi_init #%00000100 spdr spif,spsr,* #%10000000
;init ;eral opcode, part ;wait ;eral opcode, part
Application Note 9793
00524 00525 00526 00527 00528* 00529 00530 00531 00532* 00533 00534 00535 00536 00537 00538 00539 00540 00541 00542 00543 00544 00545 00546* 00547 00548 00549 00550* 00551 00552 00553 00554 00555 00556 00557 00558 00559 00560 00561 00562 00563 00564* 00565 00566 00567* 00568 00569 00570 00571 00572 00573 00574 00575 00576 00577 00578 00579 00580 00581 00582 00583 00584 00585 00586 00587 00588 00589 00590 1382 1384 1387 1389 138B B70C 0F0BFD B60C 1100 2070 brclr bclr write_566_16_spi brclr brclr brclr brclr bclr wral_566_16_spi brclr brclr brclr brclr bclr ewds_566_16_spi brclr brclr bclr spdr spif,spsr,* spdr eep_cs,eep_csp wait ;wait ;clear SPIF ;disable eeprom
138D 138F 1391 1393 1395 1398 139A 139C 139F 13A1 13A3 13A6 13A8 13AB 13AD 13AF
B752 AD59 A605 B70C 0F0BFD B651 B70C 0F0BFD B652 B70C 0F0BFD BF0C 0F0BFD B60C 1100 204C
tempA spi_init #%00000101 spdr spif,spsr,* pclo spdr spif,spsr,* tempA spdr spif,spsr,* spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;write opcode dummy ;send through ;loop until done ;get EEPROM address ;and send ;loop until done ;write data EEPROM ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;disable eeprom
13B1 13B3 13B5 13B7 13B9 13BC 13BE 13C0 13C3 13C5 13C7 13CA 13CC 13CF 13D1 13D3
B752 AD35 A604 B70C 0F0BFD A640 B70C 0F0BFD B652 B70C 0F0BFD BF0C 0F0BFD B60C 1100 2028
tempA spi_init #%00000100 spdr spif,spsr,* #%01000000 spdr spif,spsr,* tempA spdr spif,spsr,* spdr spif,spsr,* spdr eep_cs,eep_csp wait
;init ;wral opcode part ;send through ;loop until done ;wral opcode, part ;and send ;loop until done ;write data EEPROM ;loop until done ;write data EEPROM ;loop until done ;clear SPIF ;disable eeprom
13D5 13D7 13D9 13DB 13DE 13E0 13E2 13E5 13E7 13E9
AD13 A604 B70C 0F0BFD A600 B70C 0F0BFD B60C 1100
spi_init #%00000100 spdr spif,spsr,* #%00000000 spdr spif,spsr,* spdr eep_cs,eep_csp
;init ;ewds opcode, part ;wait ;ewds opcode, part ;wait ;clear SPIF ;disable eeprom
13EA 13EC 13EE 13F0 13F2 13F4 13F6
B607 AA38 B707 1A03 A651 B70A B60B
Serial EEPROM support routines spi_init spi_port+4 ;set port ddr's #(2!ss+2!sck+2!mosi) ;SS, SCK, MOSI outputs spi_port+4 bset ss,spi_port ;drive high #(2!spe+2!mstr+1) ;Master mode, spcr spsr
Application Note 9793
00591 00592 00593 00594 00595 00596 00597 00598 00599 00600 00601 00602 00603 13F8 13FA 13FC B60C 1000 wait 13FD 13FF 1401 1404 1406 1408 140A 1000 3F0C 0F0BFD B60C 27F5 1100 bset brclr bclr eep_cs,eep_csp spdr spif,spsr,* spdr wait eep_cs,eep_csp ;select eeprom ;send eeprom ;wait bset spdr eep_cs,eep_csp
Application Note 9793 Appendix Code Listing Standard Interface Routines
INTERSIL Corporation (c)1990 1997 68HC05 Assembler Version 3.0.2 Filename: 93X6_BB.LST Source Created:08/19/97, 10:37 Assembled: 08/19/97, 10:37 00001 00002 Standard Three Wire Serial EEPROM Interface Routines 00003 00004 following subroutines written interface 00005 9346, 9356 9366 series serial EEPROMs with Intersil 00006 CDP68HC05 microcontroller using standard, general purpose pins 00007 "bit-banging" fashion. seven basic commands (READ, EWEN, 00008 ERASE, ERAL, WRITE, WRAL, EWDS) both configurations each 00009 EEPROM bit) included. Note that commands 00010 9356 9366 identical have been included only once 00011 both types. naming following subroutines defined 00012 fully describe their function: 00013 00014 00015 00016 00017 #include <j4b.s> START INCLUDE C:\6805\J4B.S -00001 #nolist 00057 #list 00018 00019 00020 00021 $0000 00022 $0000 00023 $0000 00024 $0001 00025 $0002 00026 $0003 00027 00028 00029 00030 0050 00031 00032 0050 00033 0051 00034 0052 00035 0053 00036 00037 00038 00039 1000 00040 00041 00042 00043 00044 00045 00046 1000 CD13B1 00047 1003 1600 00048 1005 1200 00049 1007 1300 00050 1009 1600 00051 100B 1200 00052 100D 1300 00053 100F B651 00054 1011 A47F INCLUDE C:\6805\J4B.S Define Statements eep_port eep_csp eep_cs miso mosi Variables section RAMvars, pcHi pclo tempa tempx Subroutines section Subs, $1000 93LC46 banging routines read_46_8_bb eep_su ;set interface with eeprom bset mosi,eep_port ;send start condition bset sck,eep_port ;bset/bclr=5 cycles (fosc/10) bclr sck,eep_port bset mosi,eep_port ;send opcode bset sck,eep_port ;bset/bclr=5 cycles (fosc/10) bclr sck,eep_port pclo ;get EEPROM address #$7F ;mask bits, MSB=0 ;High byte EEPROM data address ;Low byte EEPROM data address ;temp location ;temp location porta porta
Application Note 9793
00055 00056 00057 00058 00059 00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103 00104 00105 00106 00107 00108 00109 00110 00111 00112 00113 00114 00115 00116 00117 00118 00119 00120 00121 1013 1015 1018 101B 101D AE08 CD13C2 CD13D3 1100 ewen_46_8_bb 101E 1021 1023 1025 1027 1029 102B 102D 102F 1031 1034 1036 CD13B1 1600 1200 1300 1700 1200 1300 A660 AE08 CD13C2 1100 bset bset bclr bclr bset bclr bclr erase_46_8_bb bset bset bclr bset bset bclr bclr eral_46_8_bb 1054 1057 1059 105B 105D 105F 1061 1063 1065 1067 106A 106C CD13B1 1600 1200 1300 1700 1200 1300 A640 AE08 CD13C2 1100 CC13E3 bset bset bclr bclr bset bclr bclr write_46_8_bb bset bset bclr bclr bset bclr bclr eep_su mosi,eep_port sck,eep_port sck,eep_port mosi,eep_port sck,eep_port sck,eep_port #%01000000 #$08 BBsend eep_cs,eep_csp waitBB ;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;send opcode ;bset/bclr=5 cycles (fosc/10) ;eral opcode, part ;bit bang ;disable eeprom eep_su mosi,eep_port sck,eep_port sck,eep_port mosi,eep_port sck,eep_port sck,eep_port #%01100000 #$08 BBsend eep_cs,eep_csp ;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;send opcode ;bset/bclr=5 cycles (fosc/10) ;ewen opcode, part ;bit bang ;disable eeprom bclr #$08 BBsend BBrecv eep_cs,eep_csp ;bit bang ;get data ;disable eeprom ;and return
1037 103A 103C 103E 1040 1042 1044 1046 1048 104A 104C 104F 1051
CD13B1 1600 1200 1300 1600 1200 1300 B651 AA80 AE08 CD13C2 1100 CC13E3
eep_su mosi,eep_port sck,eep_port sck,eep_port mosi,eep_port sck,eep_port sck,eep_port pclo #$80 #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;send opcode ;bset/bclr=5 cycles (fosc/10) ;get EEPROM address ;mask bits, MSB=0 ;bit bang ;disable eeprom
106F 1071 1074 1076 1078 107A 107C 107E 1080 1082 1084 1086 1089 108B 108D 1090 1092
B752 CD13B1 1600 1200 1300 1700 1200 1300 B651 AA80 AE08 CD13C2 B652 AE08 CD13C2 1100 CC13E3
tempA eep_su mosi,eep_port sck,eep_port sck,eep_port mosi,eep_port sck,eep_port sck,eep_port pcLo #$80 #$08 BBsend tempA #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;send opcode ;bset/bclr=5 cycles (fosc/10) ;get address ;MSB=1 (part opcode) ;bit bang ;send data ;bit bang ;disable eeprom
Application Note 9793
00122 00123 00124 00125 00126 00127 00128 00129 00130 00131 00132 00133 00134 00135 00136 00137 00138 00139 00140 00141 00142 00143 00144 00145 00146 00147 00148 00149 00150 00151 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181 00182 00183 00184 00185 00186 00187 00188 wral_46_8_bb 1095 1097 109A 109C 109E 10A0 10A2 10A4 10A6 10A8 10AA 10AD 10AF 10B1 10B4 10B6 B752 CD13B1 1600 1200 1300 1700 1200 1300 A620 AE08 CD13C2 B652 AE08 CD13C2 1100 CC13E3 ewds_46_8_bb 10B9 10BC 10BE 10C0 10C2 10C4 10C6 10C8 10CA 10CC 10CF 10D1 CD13B1 1600 1200 1300 1700 1200 1300 A600 AE08 CD13C2 1100 bset bset bclr bclr bset bclr bclr eep_su mosi,eep_port sck,eep_port sck,eep_port mosi,eep_port sck,eep_port sck,eep_port #%00000000 #$08 BBsend eep_cs,eep_csp ;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;send opcode ;bset/bclr=5 cycles (fosc/10) ;ewds opcode, part ;bit bang ;disable eeprom bset bset bclr bclr bset bclr bclr tempA eep_su mosi,eep_port sck,eep_port sck,eep_port mosi,eep_port sck,eep_port sck,eep_port #%00100000 #$08 BBsend tempA #$08 BBsend eep_cs,eep_csp waitBB ;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;send opcode ;bset/bclr=5 cycles (fosc/10)
;bit bang ;send data ;bit bang ;disable eeprom
10D2 10D5 10D7 10D9 10DB 10DD 10DF 10E1 10E3 10E6 10E9 10EB 10EE 10EF 10F1 10F3
CD13B1 1600 1200 1300 B651 A43F AA80 AE08 CD13C2 CD13D3 B752 CD13D3 B652 1100
93LC46 bit-banging routines read_46_16_bb eep_su ;set interface with eeprom bset mosi,eep_port ;send start condition bset sck,eep_port ;bset/bclr=5 cycles (fosc/10) bclr sck,eep_port pclo ;get EEPROM address #$3F ;mask bits, MSB=10 #$80 #$08 bbsend ;bit bang bbrecv ;get byte data tempA bbrecv ;get byte data byte returned tempA byte returned bclr eep_cs,eep_csp ;and return ewen_46_16_bb bset bset bclr bclr
10F4 10F7 10F9 10FB 10FD 10FF 1101 1104 1106
CD13B1 1600 1200 1300 A630 AE08 CD13C2 1100
eep_su mosi,eep_port sck,eep_port sck,eep_port #%00110000 #$08 BBsend eep_cs,eep_csp
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;ewen opcode, part ;bit bang ;disable eeprom
Application Note 9793
00189 00190 00191 00192 00193 00194 00195 00196 00197 00198 00199 00200 00201 00202 00203 00204 00205 00206 00207 00208 00209 00210 00211 00212 00213 00214 00215 00216 00217 00218 00219 00220 00221 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249 00250 00251 00252 00253 00254 00255 1107 110A 110C 110E 1110 1112 1114 1116 1119 111B CD13B1 1600 1200 1300 B651 AAC0 AE08 CD13C2 1100 CC13E3 erase_46_16_bb bset bset bclr bclr eral_46_16_bb bset bset bclr bclr write_46_16_bb bset bset bclr bclr wral_46_16_bb bset bset bclr bclr ewds_46_16_bb bset bset eep_su mosi,eep_port sck,eep_port sck,eep_port pclo #$C0 #$08 BBsend eep_cs,eep_csp waitBB ;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;get EEPROM address ;mask bits, MSB=11 ;bit bang ;disable eeprom
111E 1121 1123 1125 1127 1129 112B 112E 1130
CD13B1 1600 1200 1300 A620 AE08 CD13C2 1100 CC13E3
eep_su mosi,eep_port sck,eep_port sck,eep_port #%00100000 #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;eral opcode, part ;bit bang ;disable eeprom
1133 1135 1137 113A 113C 113E 1140 1142 1144 1146 1148 114B 114D 114F 1152 1154 1156 1159 115B
B752 BF53 CD13B1 1600 1200 1300 B651 A43F AA40 AE08 CD13C2 B652 AE08 CD13C2 B653 AE08 CD13C2 1100 CC13E3
tempA tempX eep_su mosi,eep_port sck,eep_port sck,eep_port pcLo #$3F #$40 #$08 BBsend tempA #$08 BBsend tempX #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10) ;get address ;mask bits ;MSB=01 (part opcode) ;bit bang ;send data ;bit bang high byte
;bit bang byte ;disable eeprom
115E 1160 1162 1165 1167 1169 116B 116D 116F 1172 1174 1176 1179 117B 117D 1180 1182
B752 BF53 CD13B1 1600 1200 1300 A610 AE08 CD13C2 B652 AE08 CD13C2 B653 AE08 CD13C2 1100 CC13E3
tempA tempX eep_su mosi,eep_port sck,eep_port sck,eep_port #%00010000 #$08 BBsend tempA #$08 BBsend tempX #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10)
;bit bang ;send data ;bit bang high byte
;bit bang byte ;disable eeprom
1185 1188 118A
CD13B1 1600 1200
eep_su mosi,eep_port sck,eep_port
;set interface with eeprom ;send start condition ;bset/bclr=5 cycles (fosc/10)
Application Note 9793
00256 00257 00258 00259 00260 00261 00262 00263 00264 00265 00266 00267 00268 00269 00270 00271 00272 00273 00274 00275 00276 00277 00278 00279 00280 00281 00282 00283 00284 00285 00286 00287 00288 00289 00290 00291 00292 00293 00294 00295 00296 00297 00298 00299 00300 00301 00302 00303 00304 00305 00306 00307 00308 00309 00310 00311 00312 00313 00314 00315 00316 00317 00318 00319 00320 00321 00322 118C 118E 1190 1192 1195 1197 1300 A600 AE08 CD13C2 1100 bclr bclr sck,eep_port #%00000000 #$08 BBsend eep_cs,eep_csp ;ewds opcode, part ;bit bang ;disable eeprom
1198 119B 119D 119F 11A2 11A4 11A6 11A9 11AC 11AE
CD13B1 A6C0 AE04 CD13C2 B651 AE08 CD13C2 CD13D3 1100
93LC56 bit-banging routines read_56_8_bb eep_su ;set interface with eeprom #%11000000 ;send read opcode dummy #$04 ;only send bits BBsend pclo ;get EEPROM address #$08 BBsend ;bit bang BBrecv ;get data bclr eep_cs,eep_csp ;disable eeprom ;and return ewen_56_8_bb
11AF 11B2 11B4 11B6 11B9 11BB 11BD 11C0 11C2
CD13B1 A690 AE04 CD13C2 A680 AE08 CD13C2 1100
bclr erase_56_8_bb bclr eral_56_8_bb
eep_su #%10010000 #$04 BBsend #%10000000 #$08 BBsend eep_cs,eep_csp
;set interface with eeprom ;send four bits ewen opcode ;only send bits ;ewen opcode, part ;bit bang ;disable eeprom
11C3 11C6 11C8 11CA 11CD 11CF 11D1 11D4 11D6
CD13B1 A6E0 AE04 CD13C2 B651 AE08 CD13C2 1100 CC13E3
eep_su #%11100000 #$04 BBsend pclo #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send erase opcode dummy ;only send bits ;get EEPROM address ;bit bang ;disable eeprom
11D9 11DC 11DE 11E0 11E3 11E5 11E7 11EA 11EC
CD13B1 A690 AE04 CD13C2 A600 AE08 CD13C2 1100 CC13E3
bclr write_56_8_bb
eep_su #%10010000 #$04 BBsend #%00000000 #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send eral opcode, part ;only send bits ;eral opcode, part ;bit bang ;disable eeprom
11EF 11F1 11F4 11F6 11F8 11FB 11FD 11FF 1202
B752 CD13B1 A6A0 AE04 CD13C2 B651 AE08 CD13C2 B652
tempA eep_su #%10100000 #$04 BBsend pcLo #$08 BBsend tempA
;set interface with eeprom ;send write opcode part ;only send bits ;get address ;bit bang ;send data
Application Note 9793
00323 00324 00325 00326 00327 00328 00329 00330 00331 00332 00333 00334 00335 00336 00337 00338 00339 00340 00341 00342 00343 00344 00345 00346 00347 00348 00349 00350 00351 00352 00353 00354 00355 00356 00357 00358 00359 00360 00361 00362 00363 00364 00365 00366 00367 00368 00369 00370 00371 00372 00373 00374 00375 00376 00377 00378 00379 00380 00381 00382 00383 00384 00385 00386 00387 00388 00389 1204 1206 1209 120B AE08 CD13C2 1100 CC13E3 wral_56_8_bb 120E 1210 1213 1215 1217 121A 121C 121E 1221 1223 1225 1228 122A B752 CD13B1 A680 AE04 CD13C2 A680 AE08 CD13C2 B652 AE08 CD13C2 1100 CC13E3 ewds_56_8_bb 122D 1230 1232 1234 1237 1239 123B 123E 1240 CD13B1 A680 AE04 CD13C2 A600 AE08 CD13C2 1100 bclr eep_su #%10000000 #$04 BBsend #%00000000 #$08 BBsend eep_cs,eep_csp ;set interface with eeprom ;send ewds opcode part ;only send bits ;ewds opcode, part ;bit bang ;disable eeprom bclr tempA eep_su #%10000000 #$04 BBsend #%10000000 #$08 BBsend tempA #$08 BBsend eep_cs,eep_csp waitBB ;set interface with eeprom ;send wral opcode part ;only send bits bclr #$08 BBsend eep_cs,eep_csp waitBB ;bit bang ;disable eeprom
;bit bang ;send data ;bit bang ;disable eeprom
1241 1244 1246 1248 1249 124A 124B 124C 124E 1250 1253 1255 1257 125A 125D 125F
CD13B1 B650 A401 ABC0 AE04 CD13C2 B651 AE08 CD13C2 CD13D3 1100
93LC66 bit-banging routines read_66_8_bb eep_su ;set interface with eeprom pcHi ;get address #$01 ;mask lsla lsla lsla lsla #%11000000 ;send read opcode dummy #$04 ;only send bits BBsend pclo ;get EEPROM address #$08 BBsend ;bit bang BBrecv ;get data bclr eep_cs,eep_csp ;disable eeprom ;and return ewen_66_8_bb
1260 1263 1265 1267 126A 126C 126E 1271 1273
CD13B1 A690 AE04 CD13C2 A680 AE08 CD13C2 1100
bclr erase_66_8_bb
eep_su #%10010000 #$04 BBsend #%10000000 #$08 BBsend eep_cs,eep_csp
;set interface with eeprom ;send four bits ewen opcode ;only send bits ;ewen opcode, part ;bit bang ;disable eeprom
1274
CD13B1
eep_su
;set interface with eeprom
Application Note 9793
00390 00391 00392 00393 00394 00395 00396 00397 00398 00399 00400 00401 00402 00403 00404 00405 00406 00407 00408 00409 00410 00411 00412 00413 00414 00415 00416 00417 00418 00419 00420 00421 00422 00423 00424 00425 00426 00427 00428 00429 00430 00431 00432 00433 00434 00435 00436 00437 00438 00439 00440 00441 00442 00443 00444 00445 00446 00447 00448 00449 00450 00451 00452 00453 00454 00455 00456 1277 1279 127B 127C 127D 127E 127F 1281 1283 1286 1288 128A 128D 128F B650 A401 ABE0 AE04 CD13C2 B651 AE08 CD13C2 1100 CC13E3 eral_66_8_bb 1292 1295 1297 1299 129C 129E 12A0 12A3 12A5 CD13B1 A690 AE04 CD13C2 A600 AE08 CD13C2 1100 CC13E3 bclr write_66_8_bb lsla lsla lsla lsla bclr wral_66_8_bb 12CF 12D1 12D4 12D6 12D8 12DB 12DD 12DF 12E2 12E4 12E6 12E9 12EB B752 CD13B1 A680 AE04 CD13C2 A680 AE08 CD13C2 B652 AE08 CD13C2 1100 CC13E3 ewds_66_8_bb 12EE 12F1 12F3 12F5 CD13B1 A680 AE04 CD13C2 eep_su #%10000000 #$04 BBsend ;set interface with eeprom ;send ewds opcode part ;only send bits bclr tempA eep_su #%10000000 #$04 BBsend #%10000000 #$08 BBsend tempA #$08 BBsend eep_cs,eep_csp waitBB ;set interface with eeprom ;send wral opcode part ;only send bits eep_su #%10010000 #$04 BBsend #%00000000 #$08 BBsend eep_cs,eep_csp waitBB ;set interface with eeprom ;send eral opcode, part ;only send bits ;eral opcode, part ;bit bang ;disable eeprom lsla lsla lsla lsla bclr pcHi #$01 ;get address ;mask
#%11100000 #$04 BBsend pclo #$08 BBsend eep_cs,eep_csp waitBB
;send erase opcode dummy ;only send bits ;get EEPROM address ;bit bang ;disable eeprom
12A8 12AA 12AD 12AF 12B1 12B2 12B3 12B4 12B5 12B7 12B9 12BC 12BE 12C0 12C3 12C5 12C7 12CA 12CC
B752 CD13B1 B650 A401 ABA0 AE04 CD13C2 B651 AE08 CD13C2 B652 AE08 CD13C2 1100 CC13E3
tempA eep_su pcHi #$01
;set interface with eeprom ;get address ;mask
#%10100000 #$04 BBsend pcLo #$08 BBsend tempA #$08 BBsend eep_cs,eep_csp waitBB
;send write opcode part ;only send bits ;get address ;bit bang ;send data ;bit bang ;disable eeprom
;bit bang ;send data ;bit bang ;disable eeprom
Application Note 9793
00457 00458 00459 00460 00461 00462 00463 00464 00465 00466 00467 00468 00469 00470 00471 00472 00473 00474 00475 00476 00477 00478 00479 00480 00481 00482 00483 00484 00485 00486 00487 00488 00489 00490 00491 00492 00493 00494 00495* 00496 00497 00498 00499 00500 00501* 00502 00503 00504 00505 00506* 00507 00508 00509* 00510 00511 00512* 00513 00514 00515 00516 00517 00518 00519* 00520 00521 00522* 00523 12F8 12FA 12FC 12FF 1301 A600 AE08 CD13C2 1100 #%00000000 ;ewds opcode, part #$08 BBsend ;bit bang bclr eep_cs,eep_csp ;disable eeprom 93LC56 93LC66 bit-banging routines read_566_16_bb eep_su ;set interface with eeprom #%11000000 ;send read opcode #$03 ;only send bits BBsend pclo ;get EEPROM address #$08 BBsend ;bit bang bbrecv ;get byte data tempA bbrecv ;get byte data byte returned tempA byte returned bclr eep_cs,eep_csp ;and return ewen_566_16_bb bclr erase_566_16_bb bclr eral_566_16_bb bclr write_566_16_bb
1302 1305 1307 1309 130C 130E 1310 1313 1316 1318 131B 131C 131E 1320
CD13B1 A6C0 AE03 CD13C2 B651 AE08 CD13C2 CD13D3 B752 CD13D3 B652 1100
1321 1324 1326 1328 132B 132D 132F 1332 1334
CD13B1 A680 AE03 CD13C2 A6C0 AE08 CD13C2 1100
eep_su #%10000000 #$03 BBsend #%11000000 #$08 BBsend eep_cs,eep_csp
;set interface with eeprom ;send ewen opcode ;only send bits ;ewen opcode, part ;bit bang ;disable eeprom
1335 1337 1339 133B 133E 1340 1342 1344 1346
AD7A A6E0 AE03 CD13C2 B651 AE08 AD7E 1100 CC13E3
eep_su #%11100000 #$03 BBsend pclo #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send erase opcode ;only send bits ;get EEPROM address ;bit bang ;disable eeprom
1349 134B 134D 134F 1351 1353 1355 1357 1359
AD66 A680 AE03 AD71 A680 AE08 AD6B 1100 CC13E3
eep_su #%10000000 #$03 BBsend #%10000000 #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send eral opcode ;only send bits ;eral opcode, part ;bit bang ;disable eeprom
135C 135E 1360 1362 1364 1366 1368
B752 BF53 AD4F A6A0 AE03 AD5A B651
tempA tempX eep_su #%10100000 #$03 BBsend pcLo
;set interface with eeprom ;send write opcode ;only send bits ;get address
Application Note 9793
00524 00525* 00526 00527 00528* 00529 00530 00531* 00532 00533* 00534 00535 00536 00537 00538* 00539 00540 00541* 00542 00543 00544* 00545 00546 00547* 00548 00549 00550* 00551 00552* 00553 00554 00555* 00556 00557 00558* 00559 00560 00561* 00562 00563 00564 00565 00566 00567 00568 00569 00570 00571 00572 00573 00574 00575 00576 00577 00578 00579 00580 00581 00582 00583 00584 00585 00586 00587 00588 00589 00590 136A 136C 136E 1370 1372 1374 1376 1378 137A 137C AE08 AD54 B652 AE08 AD4E B653 AE08 AD48 1100 2065 bclr wral_566_16_bb bclr ewds_566_16_bb bclr #$08 BBsend tempA #$08 BBsend tempX #$08 BBsend eep_cs,eep_csp waitBB ;bit bang ;send data ;bit bang high byte
;bit bang byte ;disable eeprom
137E 1380 1382 1384 1386 1388 138A 138C 138E 1390 1392 1394 1396 1398 139A 139C 139E
B752 BF53 AD2D A680 AE03 AD38 A640 AE08 AD32 B652 AE08 AD2C B653 AE08 AD26 1100 2043
tempA tempX eep_su #%10000000 #$03 BBsend #%01000000 #$08 BBsend tempA #$08 BBsend tempX #$08 BBsend eep_cs,eep_csp waitBB
;set interface with eeprom ;send erase opcode ;only send bits
;bit bang ;send data ;bit bang high byte
;bit bang byte ;disable eeprom
13A0 13A2 13A4 13A6 13A8 13AA 13AC 13AE 13B0
AD0F A680 AE03 AD1A A600 AE08 AD14 1100
eep_su #%10000000 #$03 BBsend #%00000000 #$08 BBsend eep_cs,eep_csp
;set interface with eeprom ;send erase opcode ;only send bits ;ewds opcode, part ;bit bang ;disable eeprom
Serial Three Wire EEPROM Banging support routines eep_su This routine sets standard port interfacing with 93x6 series EEPROMs. This routine written called beginning each command subroutine, also lowers line EEPROM before returning. eep_su eep_port+4 ;set port interface #(2!sck+2!mosi) ;set MOSI (EEP output #~(2!miso) ;set MISO input eep_port+4 eep_port #~(2!sck+2!mosi) ;data pins eep_port bset eep_cs,eep_csp ;send high
13B1 13B3 13B5 13B7 13B9 13BB 13BD 13BF 13C1
B604 AA0A A4FB B704 B600 A4F5 B700 1000
Application Note 9793
00591 00592 00593 00594 00595 00596 00597 00598 00599 00600 00601 00602 00603 00604 00605 00606 00607 00608 00609 00610 00611 00612 00613 00614 00615 00616 00617 00618 00619 00620 00621 00622 00623 00624 00625 00626 00627 00628 00629 00630 00631 00632 00633 00634 00635 00636 00637 00638 00639 00640 00641 00642 00643 00644 00645 bbSend This routine transmits bits throught defined "mosi" euate statements above. number bits sent maximum sent routine register data sent contained most significant positions accumulator. data bits sent beginning with ACCA. bbSend bclr mosi,eep_port rola ;rotate through carry clockIt carry clear, skip bset mosi,eep_port clockIt bset sck,eep_port ;clock data bclr sck,eep_port decx BBsend ;loop eight bits bclr mosi,eep_port bbRecv This routine receives bits data throught defined "miso". This data returned calling program accumulator. bbrecv ;receive data BBrxloop ;clear carry bset sck,eep_port ;send clock high bclr sck,eep_port ;data comes falling edge brclr miso,eep_port,itsLow ;read data itsLow rola ;rotate through decx ;dec counter BBrxloop ;get bits waitBB This routine called write erase command poll EEPROM wait until operation complete. waitBB bset eep_cs,eep_csp ;select eeprom brclr miso,eep_port,* ;wait until line goes bclr eep_cs,eep_csp
13C2 13C4 13C5 13C7 13C9 13CB 13CD 13CE 13D0 13D2
1700 2402 1600 1200 1300 26F2 1700
13D3 13D5 13D6 13D8 13DA 13DD 13DE 13DF 13E0 13E2
AE08 1200 1300 050001 26F3
13E3 13E5 13E8 13EA
1000 0500FD 1100
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This application note describes hardware software interface between 93

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