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Hardware / Software Interface Description for PRISM® Radio Design

Authors: John Fakatselis and Mike Paljug

Hardware / Software Interface Description for PRISM® Radio Design
Application Note January 1997 AN9617.1
Authors: John Fakatselis and Mike Paljug
Example Using the AM79C930 Media Access Controller
This document includes a description of the HW / SW interface for the IEEE802.11 target radio architecture based on the Intersil PRISM® chip set and the AMD Media Access Controller (MAC) AM79C930 processor. The information includes all the necessary interface requirements that can be used to control the PRISM radio with any other controller or processor that does not necessarily target IEEE802.11. The design example, though, addresses special design issues interfacing with the AM79C930.
Hardware Configuration
The block diagram in Figure 1 is intended to show a top level view of the basic hardware devices comprising the radio design. The detailed list of all signal interfaces required between MAC and the Physical Layer (PHY) or the PRISM radio are listed in Table 1 of this document.
List of Signals
Table 1 summarizes the signals that are required to control the PHY radio operations. The first column lists the PHY signal name, the second column indicates whether the signal is an output or an input to the MAC, the next column contains a brief description of each listed signal and the last two columns indicate the HW component part number and the pin connection for each of the listed signals at both the PHY and the MAC ends.
RSSI ANTENNA DS CHANNEL FILTER
OPTIONAL RSSI INPUT
HFA3624 RF - IF CONVERSION
HFA3724 IF - BB CONVERSION
HSP3824 DSSS BASEBAND PROCESSOR
MAC ENGINE
PC CARD INTERFACE
HFA3925 POWER AMP
FIGURE 1. PRISM® CHIPSET SYSTEM BLOCK DIAGRAM
Application Note 9617
Summary List of MAC-PHY Interface Signals
TABLE 1. MAC-PHY INTERFACE SIGNALS I / O FROM / TO MAC O O O O O O O O O O O I I O I I I O O O O I / O I O O O O MAC PIN NUMBER AM79C930 MAC (102) MAC (101) MAC (3) MAC (126) MAC (142) MAC (126) MAC (142) MAC (132) MAC (141) MAC (131) MAC (121) MAC (115) MAC (91) MAC (122) MAC (95) MAC (123) MAC (124) MAC (107) MAC (105) MAC (103) MAC (101) MAC (102) MAC (96) MAC (118) MAC (131) MAC (92) MAC (2)
DESCRIPTION Serial Data Bus (Synthesizer) Serial Control Clock (Synthesizer) Load Enable (Synthesizer) Receive Power Enable (RF / IF Converter) Transmit Power Enable (RF / IF Converter) Receive Power Enable (Qmodem) Transmit Power Enable (Qmodem) Low Pass Filter Control (Qmodem) Low Pass Filter Control (Qmodem) Transmit Power Enable (Transmit Port) Transmit Data (Transmit Port) Transmit Clock (Transmit Port) Transmit Data Ready (Transmit Port) Receiver Power Enable (Receive Port) MAC Data Ready (Receive Port) Receive Data (Receive Port) Receive Clock (Receive Port) Chip Select (Control Port) Address Strobe (Control Port) Read / write Strobe (Control Port) Serial Control Clock (Control Port) Bi-directional Serial Data Bus (Control Port) Clear Channel Assessment Master Reset Transmit Amplifier Power Enable (RFPA) VCO Enable Circuit Radio Power Enable
PHY PART / PIN NUMBER HFA3524 (12) HFA3524 (11) HFA3524 (13) HFA3624 (28) HFA3624 (15) HFA3724 (21, 43, 54, 74) HFA3724 (22, 41) HFA3724 (17) HFA3724 (16) HSP3824 (2) HSP3824 (3) HSP3824 (4) HSP3824 (5) HSP3824 (33) HSP3824 (34) HSP3824 (35) HSP3824 (36) HSP3824 (9) HSP3824 (23) HSP3824 (8) HSP3824 (24) HSP3824 (25) HSP3824 (32) HSP3824 (28) HFA3925 (11, 18, 23) VCO Startup Circuit RADIO
Application Note 9617
Interface Signal Description
Table 2 Consists of a functional description for each of the PHY signals that are part of the HW / SW interface.
SEL0, SEL1
RXD RXCLK
Application Note 9617
SCLK AS
RESET
HW / SW Interfaces
There are four primary HW / SW interfaces that are used for configuration and during normal operation of the device. The interfaces are power on initialization, transmit mode operation, receive mode operation and power shut down mode. These interfaces are summarized as follows · The Initialization & Control Interface, which is used to configure, write and / or read the status of the physical layer digital modem and the RF synthesizer. This interface is required to configure the programmable portions of the PHY during power up and coming out of certain power down modes. This interface is also used during operations for real time reconfiguration of PHY parameters and / or for reading PHY status. · The TX Interface, which is used to control the transmit data transfers between the MAC and the physical layer. It is also used to control all PHY devices for the transmit chain of the radio. · The RX Interface, which is used to control the receive data transfers between the MAC and the physical layer. It is also used to control all PHY devices for the receive chain of the radio. · The Power Down Interface, which is used to set the physical layer into one of three power savings modes.
Initialization & Control Interface
This HW / SW interface is used to configure and monitor the programmable registers of the PHY. There are two PHY devices that contain programmable registers: · The digital modem · The RF frequency synthesizer. This interface is required to configure the PHY radio upon power up initialization and to monitor status during normal operation. This interface is also used to select or switch the frequency channel as required for the transmit and receive operations. DIGITAL MODEM INTERFACE The signals necessary to accomplish the functions of this interface are: CS: Chip select AS: Address strobe R / W: Read / Write strobe SD: Serial Data. SCLK: Serial Data Clock. This HW / SW interface is required to configure the digital modem registers and performs all read and write operations to and from the digital modem. The serial control interface is used to serially write and read data to / from the digital modem. This serial interface can operate up to a 10MHz rate
Application Note 9617
or the maximum sampling clock rate of the PHY (whichever is lower). The sampling or master clock of the physical layer is designated as MCLK and must be running during programming. This interface is used to program and to read all internal registers. The first 8-bits always represent the address followed immediately by the 8 data bits for that register. The serial transfers are accomplished through the serial data signal (SD). SD is a bi-directional serial data bus. An Address Strobe (AS), Chip Select (CS), and Read / Write (R / W) are also required as handshake signals for this interface. The clock used in conjunction with the address and data on SD is SCLK. This clock is provided to the PHY. The timing relationships of these signals are illustrated in Figure 2. AS is active high during the clocking of the address bits. R / W is high when data is to be read, and low when it is to be written. CS must be active (low) during the entire data transfer cycle. CS selects the device. The serial control interface operates asynchronously from the TX and RX
CONTROL PORT READ TIMING
interfaces and can accomplish data transfers independent of the activity at the other digital or analog interfaces. CS does not effect the TX or RX operation of the device impacting only the operation of the Control interface. PHY MODEM CONFIGURATION The PHY modem has 57 internal registers that can be configured through the control interface. These registers are listed in Table 3 below. The table lists the configuration register number, a brief name describing the register, and the HEX address to access each of the registers. The type indicates whether the corresponding register is Read only (R) or Read / Write (R / W). Some registers are two bytes wide as indicated on the table (high & low bytes). Table 3 indicates the proper modem register configuration to implement the IEEE802.11 requirements as of the JULY 95 proposed draft.
ADDRESS IN
DATA OUT
CONTROL PORT WRITE TIMING
ADDRESS IN
DATA OUT
FIGURE 2. DIGITAL MODEM CONTROL INTERFACE TABLE 3. CONFIGURATION AND CONTROL PHY REGISTER LIST CONFIGURATION REGISTER CR0 CR1 CR2 CR3 CR4 CR5 NAME MODEM CONFIG. REG #1 MODEM CONFIG. REG #2 MODEM CONFIG. REG #3 ytd MODEM CONFIG. REG #4 INTERNAL TEST REGISTER #1 INTERNAL TEST REGISTER #2 TYPE R / W R / W R / W R / W R / W R / W REGISTER ADDRESS HEX 00 04 08 0C 10 14 REGISTER DATA HEX 1E 82 23 03 00 00
Application Note 9617
These signals are utilized to configure the RF frequency synthesizer. The synthesizer tunes the radio to the appropriate receive and transmit channels. Figure 3 illustrates the required timing to write the appropriate frequency to the PHY synthesizer.
N20:MSB (R20:MSB)
N19 (R19)
N10 (R8)
N9 (R7) (R6)
N1 (R1)
CONTROL BIT:LSB CONTROL BIT:LSB
CLOCK
FIGURE 3. SYNTHESIZER SERIAL DATA INTERFACE
16, 1801h 6, 60h 16, 4118h 6, 04h 16, 1801h 6, 68h
IF R Counter register initialization. IF N Counter register initialization. RF R Counter register initialization.
Application Note 9617
TX Interface
Application Note 9617
TXCLK
SEL0 SEL1
FIGURE 4. TRANSMIT TIMING DIAGRAM
RX Interface
Application Note 9617
RXCLK
FIGURE 5. RECEIVE TIMING DIAGRAM
The preamble and PHY header are always received at a 1 MBPS (BPSK) data rate. The MAC header and data that follows can be either at 1 MBPS (BPSK) or at 2 MBPS (QPSK). To avoid rate switching within any single packet reception between the MAC-PHY interface, the RXCLK will always be at the higher rate of 2 MBPS. This implies that each of the BPSK symbols is coming out of the PHY twice. The PHY sends to the MAC the same BPSK symbol twice at a rate of 2 MBPS and this action will make it equivalent to the required BPSK symbol rate of 1 MBPS. If QPSK data bits follow the PHY header, they will be sent to the MAC from the PHY only once at the 2 MBPS rate. If rate switching is not an issue for the controller (MAC) then the HSP3824 can be configured to rate switch within the packet. The HSP3824 can automatically switch from BPSK to the QPSK rate at the appropriate time.
Application Note 9617
Power Down Modes
Application Note 9617 Appendix A
Control Register Values for Single Antenna Acquisition
REGISTER ADDRESS IN HEX 00 04 08 0C 10 14 18 1C 20 24 28 2C 30 34 38 3C 40 44 48 4C 50 54 58 5C 60 64 68 6C 70 74 78 7C 80 84 88 8C 90
REGISTER CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 CR8 CR9 CR10 CR11 CR12 CR13 CR14 CR15 CR16 CR17 CR18 CR19 CR20 CR21 CR22 CR23 CR24 CR25 CR26 CR27 CR28 CR29 CR30 CR31 CR32 CR33 CR34 CR35 CR36 MODEM CONFIG. REG #1 MODEM CONFIG. REG#2 MODEM CONFIG. REG#3 MODEM CONFIG. REG#4
Application Note 9617 Appendix A
Control Register Values for Single Antenna Acquisition
(Continued) REGISTER ADDRESS IN HEX 94 98 9C A0 A4 A8 AC B0 B4 B8 BC C0 C4 C8 CC D0 D4 D8 DC E0
REGISTER CR37 CR38 CR39 CR40 CR41 CR42 CR43 CR44 CR45 CR46 CR47 CR48 CR49 CR50 CR51 CR52 CR53 CR54 CR55 CR56
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