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HSP43168 Configured Perform Multi-Channel Filtering
digital signal processing communication systems, multiple channels sometimes require different filters each channel. Traditionally, parallel filter structures have been used these multiple channel systems. This Application Note will demonstrate HSP43168 Dual filter used replace parallel filter structures, providing significant hardware savings. multi-channel application, HSP43168 three fundamental filtering configurations: even-symmetric, asymmetric, double-clocked asymmetric. examples given this Application Note cell simplicity; number filter taps these examples doubled when both cells used single filter configuration[1]. single cell mode, even-symmetric filter maximum 8-taps; asymmetric filter maximum 4taps; double-clocked asymmetric filter maximum 8-taps. Before HSP43168 used filter multiple channels; input samples N-channels must multiplexed. system diagram application HSP43168 shown last section this Application Note. following three sections this Application Note dedicated showing internal data flow timing diagrams associated with each fundamental filtering configuration. following example, number channels being filtered input samples from each channel multiplexed into stream before entering HSP43168. Figures show internal data flow diagram symmetric multi-channel filtering application HSP43168. MUX1-0 output mode (10) only filter cell shown internal data flow diagram. multi-channel filtering application relies decimation delay registers "demultiplex" input stream that each sequential output depends samples from particular channel. number decimation delay registers decimation factor programmed into control address 000H should equal number channels length symmetric filter multi-channel filtering application limited even number filter taps because multi-channel filtering application requires decimation delay registers between filter taps. HSP43168's odd-length symmetric filter configuration, delay register between last filter forward path first filter reverse path will result misaligned input data with respect center coefficient.
Even-Symmetric Multi-Channel Filtering
Since 8-tap even-symmetric filter only unique coefficients, HSP43168 forward reverse data paths pre-summed allowing HSP43168 resolve convolution single [1]. Thus, HSP43168 clocked same frequency multiplexed input data rate; this clocking scheme will referred regular clocking. corresponding Timing Diagram regularly clocked even-symmetric multi-channel filtering application shown Figure
INPUT X2(0) X3(0) X1(1) X2(1) X3(1) X1(7) X2(7) X3(7)
CSEL0-4
ACCEN HELD LOW. FWRD RVRS PINS TIED LOW. SHFTEN ALSO TIED LOW.
FIGURE TIMING DIAGRAM EVEN-LENGTH SYMMETRIC MULTI-CHANNEL FILTERING
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. http://www.intersil.com 407-727-9207 Copyright Intersil Corporation 1999
Application Note 9421
X1(0) X2(0) X3(0) X1(1) X2(1) X3(1) X1(2) X2(2) X3(2) X1(3) X2(3) X3(3)
X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4) X1(4)
C1(0) C2(0)
C1(1)
C1(2) C2(2) C3(2)
C1(3) C3(3)
Y1(7)
FIGURE SYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
X2(0)
X3(0) X1(1)
X2(1) X3(1) X1(2)
X2(2) X3(2) X1(3)
X2(3)
X3(3) X1(4)
X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4)
C2(0) C3(0) C1(0)
C2(1) C1(1)
C3(2) C3(2) C1(2)
C2(3) C3(3) C1(3)
Y2(7)
FIGURE SYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Application Note 9421
X3(0) X1(1) X2(1) X3(1) X1(2) X2(2) X3(2) X1(3) X2(3) X3(3) X1(4) X2(4)
X2(8) X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4)
C3(0) C1(0) C2(0)
C3(1) C1(1) C2(1)
C3(2) C1(2) C2(2)
C3(3) C1(3) C2(3)
Y3(7)
FIGURE SYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Asymmetric Multi-Channel Filtering
Asymmetric multi-channel filtering almost identical symmetric filter application except reverse path disabled. HSP43168 regularly clocked asymmetric multi-channel filtering because 4-tap forward path filter convolution resolved CLK. Figure shows timing diagram asymmetric multi-channel filtering application. 4-tap asymmetric multi-channel filtering application demonstrated using three channel filtering configuration described previous section. Figures show internal Data Flow Diagram asymmetric multi-channel filtering application with HSP43168 single filter cell mode. Like even-symmetric multi-channel filtering example, HSP43168 programmed decimation delay registers between filter taps that only data from channel used compute that channel's filtered output.
INPUT X2(0)
X3(0)
X1(1)
X2(1)
X3(1)
X1(7)
X2(7)
X3(7)
CSEL0-4
ACCEN HELD LOW. FWRD RVRS PINS TIED LOW. SHFTEN ALSO TIED LOW.
FIGURE TIMING DIAGRAM ASYMMETRIC MULTI-CHANNEL FILTERING
Application Note 9421
X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4) X1(4)
C1(0) C2(0) C3(0)
C1(1) C2(1) C3(1)
C1(2) C2(2) C3(2)
C1(3) C2(3) C3(3)
Y1(7)
Y3(6)
FIGURE ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4)
C2(0) C3(0) C1(0)
C2(1) C3(1) C1(1)
C2(2) C3(2) C1(2)
C2(3) C3(3) C1(3)
Y2(7)
Y1(7)
FIGURE ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Application Note 9421
X2(8) X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4)
C3(0) C1(0) C2(0)
C3(1) C1(1) C2(1)
C3(2) C1(2) C2(2)
C3(3) C1(3) C2(3)
Y3(7)
Y2(7)
Y1(7)
FIGURE ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Double-Clocked Asymmetric Multi-Channel Filtering
asymmetric filter applications, number filter taps HSP43168 doubled clocking dual part times faster than input data rate (called double clocking). limits data rate clock rate will described next section. HSP43168 uses additional clock pulse compute accumulate previously unused reverse path, achieving 8-tap filter convolution. SHFTEN input used halt data from shifting through Decimation Registers that convolution carried over clocks. first clock, data from reverse path used filter computation. second clock, data from forward path used computation. Figures 6A-F show internal data paths HSP43168 asymmetric multi-channel filtering application given channel multiplex input sequence. doubleclocked timing diagram asymmetric multi-channel filtering applications shown Figure Again, decimation factor providing three decimation delay registers between each filter tap. These delay registers allow HSP43618 process data from channel each clock interval.
INPUT
X1(0)
X2(0)
X3(0)
X2(7)
X3(7)
CSEL0-4
FWRD
RVRS
ACCEN
SHFTEN
FIGURE TIMING DIAGRAM DOUBLE-CLOCKED ASYMMETRIC MULTICHANNEL FILTERING APPLICATION
Application Note 9421
X1(0) X2(0) X3(0) X1(1) X2(1) X3(1) X1(2) X2(2) X3(2) X1(3) X2(3) X3(3)
X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4) X1(4)
C1(7) C1(0) C2(7)
C1(6) C1(1) C2(6)
C1(5) C1(2) C2(5)
C1(4) C1(3) C2(4)
ACC1(7)
FIGURE DOUBLE-CLOCKED ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
X1(0)
X2(0) X3(0)
X1(1) X2(1) X3(1)
X1(2) X2(2) X3(2)
X1(3) X2(3) X3(3)
X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4) X1(4)
C1(0) C2(7) C2(0)
C1(1) C2(6) C2(1)
C1(2) C2(5) C2(2)
C1(3) C2(4) C2(3)
Y1(7)
FIGURE DOUBLE-CLOCKED ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Application Note 9421
X2(0) X3(0) X1(1) X2(1) X3(1) X1(2) X2(2) X3(2) X1(3) X2(3) X3(3) X1(4)
X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4)
C2(7) C2(0) C3(7)
C2(6) C2(1) C3(6)
C2(5) C2(2) C3(5)
C2(4) C2(3) C3(4)
ACC2(7)
Y1(7)
Y3(6)
FIGURE DOUBLE-CLOCKED ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
X2(0)
X3(0) X1(1)
X2(1) X3(1) X1(2)
X2(2) X3(2) X1(3)
X2(3) X3(3) X1(4)
X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4) X2(4)
C2(0) C3(7) C3(0)
C2(1) C3(6) C3(1)
C2(2) C3(5) C3(2)
C2(3) C3(4) C3(3)
Y2(7)
FIGURE DOUBLE-CLOCKED ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Application Note 9421
X3(0) X1(1) X2(1) X3(1) X1(2) X2(2) X3(2) X1(3) X2(3) X3(3) X1(4) X2(4)
X2(8) X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4)
C3(7) C3(0) C1(7)
C3(6) C3(1) C1(6)
C3(5) C3(2) C1(5)
C3(4) C3(3) C1(4)
ACC3(7)
Y2(7)
Y1(7)
FIGURE DOUBLE-CLOCKED ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
X3(0)
X1(1) X2(1)
X3(1) X1(2) X2(2)
X3(2) X1(3) X2(3)
X3(3) X1(4) X2(4)
X2(8) X1(8) X3(7) X2(7) X1(7) X3(6) X2(6) X1(6) X3(5) X2(5) X1(5) X3(4)
C3(0) C1(7) C1(0)
C3(1) C1(6) C1(1)
C3(2) C1(5) C1(2)
C3(3) C1(4) C1(3)
Y3(7)
Y2(7)
Y1(7)
FIGURE DOUBLE-CLOCKED ASYMMETRIC MULTI-CHANNEL DATA FLOW DIAGRAM STEP
Application Note 9421 Multi-Filter Configuration Using Single HSP43168
multiple channel filtering application demonstrated previous sections using even-symmetric, asymmetric, double-clocked asymmetric filter configuration given 3-channel multiplexed input data stream. Assuming that input output rates each channel same, then independent filters implemented. number independent filters limited maximum decimation delay registers that decimation factor 000H Control Word. multi-filter application, decimation delay registers used align multiplexed input samples that only coefficients particular channel input data from particular channel convolved. there channels, then alignment accomplished programming decimation factor equal block diagram Figure illustrates level design required implement multi-channel filtering with single HSP43168. shown Figure channels multiplexed into single device. input data rate each channel assumed same each N-channels, data rate multiplexed input exceed 45MHz. Thus multiplexed input data rate, bounded
45MHz
example, 3-channel 16-tap asymmetric filter with sample rate 7MHz channel realized, then HSP43168 must configured MUX0-1 mode must double clocked achieve taps. Thus, must equal 7MHz 42MHz; this 3-channel system filtered using HSP43168VC-45 which maximum 45MHz clock. FOUT 7MHz.
Appendix: Features HSP43168
HSP43168 following features: HSP43168 dual filter function 16-tap filter 8-tap filters summarized [1]. 10-bit filter coefficients separated into 4-tap sets designated coefficient sets stored memory each 4-tap When clocked, 10-bit filter coefficient CIN0-9 written four taps specified A0-1, either specified respectively, available coefficient sets specified A7-3. taps from particular coefficient selected CSEL0-4. output equal either (MUX1-0 00); (MUX1-0 01); (MUX1-0 10); (MUX1-0 11). symmetric filters, FWRD RVRS tied that forward reverse input paths pre-summed. ACCEN used accumulated data when high dump data output holding when low. decimation factor fixed Control Word 000H specifies many delay registers asserted between coefficient taps. SHFTEN used enable shifting data dual filter. Some common mistakes that have occurred using dual are: Setting decimation factor HSP43168 does cause filter decimate factor decimation factor only sets number delay registers between each filter tap. When delay registers decimation factor, length symmetric filter lengths longer implemented. Refer Figure p.3-27 symmetric filter implementation; seen that delay between forward reverse paths will cause input data center coefficient misaligned.
where number channels. denotes many times faster compare input data rate. equals regularly-clocked applications double-clocked applications. HSP43124 configured with MUX0-1 (output then maximum 16-taps even-symmetric double-clocked asymmetric filter maximum 8-taps regularly-clocked asymmetric filter achieved. Note that HSP43168 store coefficient sets each tap, limiting MN<33.
X1(n) X2(n) XN(n) Y1(n) Y2(n)
X1(n) X2(n)
FOUT Y1(n) Y2(n)
HSP43168 INA0-9 CSEL0-4
XN(n)
YN(n)
YN(n)
COUNTER
FUNDAMENTAL CLOCK CHANNEL RATE (SEE NOTE)
Reference
Intersil documents available web, http://www.Intersil.com/ Intersil AnswerFAX (407) 724-7800. Digital Signal Processing Data Book (DB302B), Intersil Corporation, 2401 Palm Rd., Palm Bay, 32905, 1994.
NOTE: Total number channels. regularly double clocked cases respectively. FIGURE BLOCK DIAGRAM MULTI-FILTER APPLICATION
Application Note 9421
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